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arm64: mops: detect and enable FEAT_MOPS
The Arm v8.8/9.3 FEAT_MOPS feature provides new instructions that perform a memory copy or set. Wire up the cpufeature code to detect the presence of FEAT_MOPS and enable it. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Link: https://lore.kernel.org/r/20230509142235.3284028-10-kristina.martsenko@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -288,6 +288,8 @@ infrastructure:
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+------------------------------+---------+---------+
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+------------------------------+---------+---------+
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| Name | bits | visible |
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| Name | bits | visible |
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+------------------------------+---------+---------+
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+------------------------------+---------+---------+
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| MOPS | [19-16] | y |
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+------------------------------+---------+---------+
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| RPRES | [7-4] | y |
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| RPRES | [7-4] | y |
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+------------------------------+---------+---------+
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+------------------------------+---------+---------+
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| WFXT | [3-0] | y |
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| WFXT | [3-0] | y |
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@ -302,6 +302,9 @@ HWCAP2_SMEB16B16
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HWCAP2_SMEF16F16
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HWCAP2_SMEF16F16
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Functionality implied by ID_AA64SMFR0_EL1.F16F16 == 0b1
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Functionality implied by ID_AA64SMFR0_EL1.F16F16 == 0b1
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HWCAP2_MOPS
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Functionality implied by ID_AA64ISAR2_EL1.MOPS == 0b0001.
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4. Unused AT_HWCAP bits
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4. Unused AT_HWCAP bits
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-----------------------
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-----------------------
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@ -137,6 +137,7 @@
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#define KERNEL_HWCAP_SME_BI32I32 __khwcap2_feature(SME_BI32I32)
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#define KERNEL_HWCAP_SME_BI32I32 __khwcap2_feature(SME_BI32I32)
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#define KERNEL_HWCAP_SME_B16B16 __khwcap2_feature(SME_B16B16)
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#define KERNEL_HWCAP_SME_B16B16 __khwcap2_feature(SME_B16B16)
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#define KERNEL_HWCAP_SME_F16F16 __khwcap2_feature(SME_F16F16)
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#define KERNEL_HWCAP_SME_F16F16 __khwcap2_feature(SME_F16F16)
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#define KERNEL_HWCAP_MOPS __khwcap2_feature(MOPS)
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/*
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/*
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* This yields a mask that user programs can use to figure out what
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* This yields a mask that user programs can use to figure out what
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@ -102,5 +102,6 @@
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#define HWCAP2_SME_BI32I32 (1UL << 40)
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#define HWCAP2_SME_BI32I32 (1UL << 40)
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#define HWCAP2_SME_B16B16 (1UL << 41)
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#define HWCAP2_SME_B16B16 (1UL << 41)
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#define HWCAP2_SME_F16F16 (1UL << 42)
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#define HWCAP2_SME_F16F16 (1UL << 42)
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#define HWCAP2_MOPS (1UL << 43)
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#endif /* _UAPI__ASM_HWCAP_H */
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#endif /* _UAPI__ASM_HWCAP_H */
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@ -223,6 +223,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
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ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
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FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
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FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
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ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
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@ -2187,6 +2188,11 @@ static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused)
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set_pstate_dit(1);
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set_pstate_dit(1);
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}
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}
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static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)
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{
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sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
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}
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/* Internal helper functions to match cpu capability type */
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/* Internal helper functions to match cpu capability type */
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static bool
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static bool
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cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
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cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
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@ -2649,6 +2655,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.cpu_enable = cpu_enable_dit,
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.cpu_enable = cpu_enable_dit,
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ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
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ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
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},
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},
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{
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.desc = "Memory Copy and Memory Set instructions",
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.capability = ARM64_HAS_MOPS,
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_cpuid_feature,
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.cpu_enable = cpu_enable_mops,
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ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP)
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},
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{},
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{},
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};
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};
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@ -2777,6 +2791,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),
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HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),
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HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
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HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
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HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
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HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
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HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS),
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#ifdef CONFIG_ARM64_SME
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#ifdef CONFIG_ARM64_SME
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HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
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HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
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HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
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HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
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@ -125,6 +125,7 @@ static const char *const hwcap_str[] = {
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[KERNEL_HWCAP_SME_BI32I32] = "smebi32i32",
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[KERNEL_HWCAP_SME_BI32I32] = "smebi32i32",
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[KERNEL_HWCAP_SME_B16B16] = "smeb16b16",
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[KERNEL_HWCAP_SME_B16B16] = "smeb16b16",
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[KERNEL_HWCAP_SME_F16F16] = "smef16f16",
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[KERNEL_HWCAP_SME_F16F16] = "smef16f16",
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[KERNEL_HWCAP_MOPS] = "mops",
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};
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};
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#ifdef CONFIG_COMPAT
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#ifdef CONFIG_COMPAT
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@ -35,6 +35,7 @@ HAS_GIC_PRIO_RELAXED_SYNC
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HAS_HCX
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HAS_HCX
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HAS_LDAPR
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HAS_LDAPR
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HAS_LSE_ATOMICS
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HAS_LSE_ATOMICS
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HAS_MOPS
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HAS_NESTED_VIRT
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HAS_NESTED_VIRT
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HAS_NO_FPSIMD
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HAS_NO_FPSIMD
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HAS_NO_HW_PREFETCH
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HAS_NO_HW_PREFETCH
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