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dt-bindings: mailbox: Add a binding for the sun6i msgbox
This mailbox hardware is present in Allwinner sun6i, sun8i, sun9i, and sun50i SoCs. Add a device tree binding for it. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/allwinner,sun6i-a31-msgbox.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner sunxi Message Box
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maintainers:
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- Samuel Holland <samuel@sholland.org>
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description: |
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The hardware message box on sun6i, sun8i, sun9i, and sun50i SoCs is a
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two-user mailbox controller containing 8 unidirectional FIFOs. An interrupt
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is raised for received messages, but software must poll to know when a
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transmitted message has been acknowledged by the remote user. Each FIFO can
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hold four 32-bit messages; when a FIFO is full, clients must wait before
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attempting more transmissions.
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Refer to ./mailbox.txt for generic information about mailbox device-tree
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bindings.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- allwinner,sun8i-a83t-msgbox
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- allwinner,sun8i-h3-msgbox
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- allwinner,sun9i-a80-msgbox
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- allwinner,sun50i-a64-msgbox
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- allwinner,sun50i-h6-msgbox
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- const: allwinner,sun6i-a31-msgbox
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- const: allwinner,sun6i-a31-msgbox
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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description: bus clock
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resets:
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maxItems: 1
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description: bus reset
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interrupts:
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maxItems: 1
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'#mbox-cells':
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const: 1
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description: first cell is the channel number (0-7)
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required:
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- compatible
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- reg
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- clocks
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- resets
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- interrupts
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- '#mbox-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sun8i-h3-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/sun8i-h3-ccu.h>
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msgbox: mailbox@1c17000 {
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compatible = "allwinner,sun8i-h3-msgbox",
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"allwinner,sun6i-a31-msgbox";
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reg = <0x01c17000 0x1000>;
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clocks = <&ccu CLK_BUS_MSGBOX>;
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resets = <&ccu RST_BUS_MSGBOX>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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};
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...
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