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drm/nvc0/gr: enable 0xc8/0xce support, no idea if it works or not..
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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e1b89b1ca5
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b53a2d0649
@ -82,13 +82,14 @@ nvc0_graph_class(struct drm_device *dev)
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case 0xc0:
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case 0xc3:
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case 0xc4:
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case 0xce: /* guess, mmio trace shows only 0x9097 state */
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return 0x9097;
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#if 0
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case 0xc1:
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return 0x9197;
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#endif
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case 0xc8:
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return 0x9297;
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#endif
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default:
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return 0;
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}
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@ -1642,8 +1642,8 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
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nv_wr32(dev, 0x419a14, 0x00000200);
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nv_wr32(dev, 0x419a1c, 0x00000000);
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nv_wr32(dev, 0x419a20, 0x00000800);
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if (dev_priv->chipset != 0xc0)
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nv_wr32(dev, 0x00419ac4, 0x0007f440); /* 0xc3 */
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if (dev_priv->chipset != 0xc0 && dev_priv->chipset != 0xc8)
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nv_wr32(dev, 0x00419ac4, 0x0007f440);
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nv_wr32(dev, 0x419b00, 0x0a418820);
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nv_wr32(dev, 0x419b04, 0x062080e6);
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nv_wr32(dev, 0x419b08, 0x020398a4);
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@ -1657,7 +1657,7 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
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nv_wr32(dev, 0x419c04, 0x00000006);
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nv_wr32(dev, 0x419c08, 0x00000002);
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nv_wr32(dev, 0x419c20, 0x00000000);
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nv_wr32(dev, 0x419cb0, 0x00060048);
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nv_wr32(dev, 0x419cb0, 0x00060048); //XXX: 0xce 0x00020048
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nv_wr32(dev, 0x419ce8, 0x00000000);
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nv_wr32(dev, 0x419cf4, 0x00000183);
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nv_wr32(dev, 0x419d20, 0x02180000);
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@ -1687,11 +1687,11 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
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nv_wr32(dev, 0x419e8c, 0x00000000);
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nv_wr32(dev, 0x419e90, 0x00000000);
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nv_wr32(dev, 0x419e98, 0x00000000);
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if (dev_priv->chipset != 0xc0)
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if (dev_priv->chipset != 0xc0 && dev_priv->chipset != 0xc8)
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nv_wr32(dev, 0x419ee0, 0x00011110);
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nv_wr32(dev, 0x419f50, 0x00000000);
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nv_wr32(dev, 0x419f54, 0x00000000);
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if (dev_priv->chipset != 0xc0)
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if (dev_priv->chipset != 0xc0 && dev_priv->chipset != 0xc8)
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nv_wr32(dev, 0x419f58, 0x00000000);
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}
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