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mfd: hi655x: Add MFD driver for hi655x
Add PMIC MFD driver to support hisilicon hi665x. Signed-off-by: Chen Feng <puck.chen@hisilicon.com> Signed-off-by: Fei Wang <w.f@huawei.com> Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com> Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Chen Feng
Lee Jones
parent
68b21094ef
commit
b52207ef4e
@ -319,6 +319,16 @@ config MFD_HI6421_PMIC
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menus in order to enable them.
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We communicate with the Hi6421 via memory-mapped I/O.
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config MFD_HI655X_PMIC
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tristate "HiSilicon Hi655X series PMU/Codec IC"
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depends on ARCH_HISI || COMPILE_TEST
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depends on OF
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select MFD_CORE
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select REGMAP_MMIO
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select REGMAP_IRQ
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help
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Select this option to enable Hisilicon hi655x series pmic driver.
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config HTC_EGPIO
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bool "HTC EGPIO support"
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depends on GPIOLIB && ARM
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@ -196,6 +196,7 @@ obj-$(CONFIG_MFD_STW481X) += stw481x.o
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obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o
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obj-$(CONFIG_MFD_MENF21BMC) += menf21bmc.o
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obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o
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obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o
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obj-$(CONFIG_MFD_DLN2) += dln2.o
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obj-$(CONFIG_MFD_RT5033) += rt5033.o
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obj-$(CONFIG_MFD_SKY81452) += sky81452.o
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162
drivers/mfd/hi655x-pmic.c
Normal file
162
drivers/mfd/hi655x-pmic.c
Normal file
@ -0,0 +1,162 @@
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/*
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* Device driver for MFD hi655x PMIC
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*
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* Copyright (c) 2016 Hisilicon.
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*
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* Authors:
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* Chen Feng <puck.chen@hisilicon.com>
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* Fei Wang <w.f@huawei.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/hi655x-pmic.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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static const struct mfd_cell hi655x_pmic_devs[] = {
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{ .name = "hi655x-regulator", },
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};
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static const struct regmap_irq hi655x_irqs[] = {
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{ .reg_offset = 0, .mask = OTMP_D1R_INT },
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{ .reg_offset = 0, .mask = VSYS_2P5_R_INT },
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{ .reg_offset = 0, .mask = VSYS_UV_D3R_INT },
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{ .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT },
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{ .reg_offset = 0, .mask = PWRON_D4SR_INT },
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{ .reg_offset = 0, .mask = PWRON_D20F_INT },
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{ .reg_offset = 0, .mask = PWRON_D20R_INT },
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{ .reg_offset = 0, .mask = RESERVE_INT },
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};
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static const struct regmap_irq_chip hi655x_irq_chip = {
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.name = "hi655x-pmic",
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.irqs = hi655x_irqs,
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.num_regs = 1,
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.num_irqs = ARRAY_SIZE(hi655x_irqs),
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.status_base = HI655X_IRQ_STAT_BASE,
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.mask_base = HI655X_IRQ_MASK_BASE,
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};
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static struct regmap_config hi655x_regmap_config = {
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.reg_bits = 32,
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.reg_stride = HI655X_STRIDE,
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.val_bits = 8,
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.max_register = HI655X_BUS_ADDR(0xFFF),
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};
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static void hi655x_local_irq_clear(struct regmap *map)
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{
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int i;
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regmap_write(map, HI655X_ANA_IRQM_BASE, HI655X_IRQ_CLR);
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for (i = 0; i < HI655X_IRQ_ARRAY; i++) {
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regmap_write(map, HI655X_IRQ_STAT_BASE + i * HI655X_STRIDE,
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HI655X_IRQ_CLR);
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}
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}
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static int hi655x_pmic_probe(struct platform_device *pdev)
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{
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int ret;
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struct hi655x_pmic *pmic;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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void __iomem *base;
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pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
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if (!pmic)
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return -ENOMEM;
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pmic->dev = dev;
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pmic->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!pmic->res)
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return -ENOENT;
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base = devm_ioremap_resource(dev, pmic->res);
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if (!base)
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return -ENOMEM;
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pmic->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
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&hi655x_regmap_config);
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regmap_read(pmic->regmap, HI655X_BUS_ADDR(HI655X_VER_REG), &pmic->ver);
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if ((pmic->ver < PMU_VER_START) || (pmic->ver > PMU_VER_END)) {
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dev_warn(dev, "PMU version %d unsupported\n", pmic->ver);
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return -EINVAL;
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}
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hi655x_local_irq_clear(pmic->regmap);
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pmic->gpio = of_get_named_gpio(np, "pmic-gpios", 0);
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if (!gpio_is_valid(pmic->gpio)) {
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dev_err(dev, "Failed to get the pmic-gpios\n");
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return -ENODEV;
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}
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ret = devm_gpio_request_one(dev, pmic->gpio, GPIOF_IN,
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"hi655x_pmic_irq");
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if (ret < 0) {
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dev_err(dev, "Failed to request gpio %d ret = %d\n",
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pmic->gpio, ret);
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return ret;
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}
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ret = regmap_add_irq_chip(pmic->regmap, gpio_to_irq(pmic->gpio),
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IRQF_TRIGGER_LOW | IRQF_NO_SUSPEND, 0,
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&hi655x_irq_chip, &pmic->irq_data);
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if (ret) {
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dev_err(dev, "Failed to obtain 'hi655x_pmic_irq' %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, pmic);
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ret = mfd_add_devices(dev, PLATFORM_DEVID_AUTO, hi655x_pmic_devs,
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ARRAY_SIZE(hi655x_pmic_devs), NULL, 0, NULL);
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if (ret) {
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dev_err(dev, "Failed to register device %d\n", ret);
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regmap_del_irq_chip(gpio_to_irq(pmic->gpio), pmic->irq_data);
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return ret;
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}
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return 0;
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}
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static int hi655x_pmic_remove(struct platform_device *pdev)
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{
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struct hi655x_pmic *pmic = platform_get_drvdata(pdev);
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regmap_del_irq_chip(gpio_to_irq(pmic->gpio), pmic->irq_data);
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mfd_remove_devices(&pdev->dev);
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return 0;
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}
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static const struct of_device_id hi655x_pmic_match[] = {
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{ .compatible = "hisilicon,hi655x-pmic", },
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{},
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};
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static struct platform_driver hi655x_pmic_driver = {
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.driver = {
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.name = "hi655x-pmic",
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.of_match_table = of_match_ptr(hi655x_pmic_match),
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},
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.probe = hi655x_pmic_probe,
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.remove = hi655x_pmic_remove,
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};
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module_platform_driver(hi655x_pmic_driver);
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MODULE_AUTHOR("Chen Feng <puck.chen@hisilicon.com>");
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MODULE_DESCRIPTION("Hisilicon hi655x PMIC driver");
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MODULE_LICENSE("GPL v2");
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55
include/linux/mfd/hi655x-pmic.h
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55
include/linux/mfd/hi655x-pmic.h
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@ -0,0 +1,55 @@
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/*
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* Device driver for regulators in hi655x IC
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*
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* Copyright (c) 2016 Hisilicon.
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*
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* Authors:
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* Chen Feng <puck.chen@hisilicon.com>
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* Fei Wang <w.f@huawei.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __HI655X_PMIC_H
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#define __HI655X_PMIC_H
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/* Hi655x registers are mapped to memory bus in 4 bytes stride */
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#define HI655X_STRIDE 4
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#define HI655X_BUS_ADDR(x) ((x) << 2)
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#define HI655X_BITS 8
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#define HI655X_NR_IRQ 32
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#define HI655X_IRQ_STAT_BASE (0x003 << 2)
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#define HI655X_IRQ_MASK_BASE (0x007 << 2)
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#define HI655X_ANA_IRQM_BASE (0x1b5 << 2)
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#define HI655X_IRQ_ARRAY 4
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#define HI655X_IRQ_MASK 0xFF
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#define HI655X_IRQ_CLR 0xFF
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#define HI655X_VER_REG 0x00
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#define PMU_VER_START 0x10
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#define PMU_VER_END 0x38
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#define RESERVE_INT BIT(7)
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#define PWRON_D20R_INT BIT(6)
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#define PWRON_D20F_INT BIT(5)
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#define PWRON_D4SR_INT BIT(4)
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#define VSYS_6P0_D200UR_INT BIT(3)
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#define VSYS_UV_D3R_INT BIT(2)
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#define VSYS_2P5_R_INT BIT(1)
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#define OTMP_D1R_INT BIT(0)
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struct hi655x_pmic {
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struct resource *res;
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struct device *dev;
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struct regmap *regmap;
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int gpio;
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unsigned int ver;
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struct regmap_irq_chip_data *irq_data;
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};
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#endif
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