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Pin control bulk changes for the v5.10 kernel cycle

Browse Source 
Core changes:
 
 - NONE whatsoever, we don't even touch the core files this
   time around.
 
 New drivers:
 
 - New driver for the Toshiba Visconti SoC.
 
 - New subdriver for the Qualcomm MSM8226 SoC.
 
 - New subdriver for the Actions Semiconductor S500 SoC.
 
 - New subdriver for the Mediatek MT8192 SoC.
 
 - New subdriver for the Microchip SAMA7G5 SoC.
 
 Driver enhancements:
 
 - Intel Cherryview and Baytrail cleanups and refactorings.
 
 - Enhanced support for the Renesas R8A7790, more pins and
   groups.
 
 - Some optimizations for the MCP23S08 MCP23x17 variant.
 
 - Some cleanups around the Actions Semiconductor subdrivers.
 
 - A bunch of cleanups around the SH-PFC and Emma Mobile
   drivers.
 
 - The "SH-PFC" (literally SuperH pin function controller, I
   think) subdirectory is now renamed to the more neutral
   "renesas", as these are not very much centered around
   SuperH anymore.
 
 - Non-critical fixes for the Aspeed driver.
 
 - Non-critical fixes for the Ingenic (MIPS!) driver.
 
 - Fix a bunch of missing pins on the AMD pinctrl driver.
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Merge tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Core changes:

   - NONE whatsoever, we don't even touch the core files this time
     around.

  New drivers:

   - New driver for the Toshiba Visconti SoC.

   - New subdriver for the Qualcomm MSM8226 SoC.

   - New subdriver for the Actions Semiconductor S500 SoC.

   - New subdriver for the Mediatek MT8192 SoC.

   - New subdriver for the Microchip SAMA7G5 SoC.

  Driver enhancements:

   - Intel Cherryview and Baytrail cleanups and refactorings.

   - Enhanced support for the Renesas R8A7790, more pins and groups.

   - Some optimizations for the MCP23S08 MCP23x17 variant.

   - Some cleanups around the Actions Semiconductor subdrivers.

   - A bunch of cleanups around the SH-PFC and Emma Mobile drivers.

   - The "SH-PFC" (literally SuperH pin function controller, I think)
     subdirectory is now renamed to the more neutral "renesas", as these
     are not very much centered around SuperH anymore.

   - Non-critical fixes for the Aspeed driver.

   - Non-critical fixes for the Ingenic (MIPS!) driver.

   - Fix a bunch of missing pins on the AMD pinctrl driver"

* tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (78 commits)
  pinctrl: amd: Add missing pins to the pin group list
  dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks
  pinctrl: visconti: PINCTRL_TMPV7700 should depend on ARCH_VISCONTI
  pinctrl: mediatek: Free eint data on failure
  pinctrl: single: fix debug output when #pinctrl-cells = 2
  pinctrl: single: fix pinctrl_spec.args_count bounds check
  pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent
  pinctrl: cannonlake: Modify COMMUNITY macros to be consistent
  pinctrl: tigerlake: Fix register offsets for TGL-H variant
  pinctrl: Document pinctrl-single,pins when #pinctrl-cells = 2
  pinctrl: mediatek: use devm_platform_ioremap_resource_byname()
  pinctrl: nuvoton: npcm7xx: Constify static ops structs
  pinctrl: mediatek: mt7622: add antsel pins/groups
  pinctrl: ocelot: simplify the return expression of ocelot_gpiochip_register()
  pinctrl: at91-pio4: add support for sama7g5 SoC
  dt-bindings: pinctrl: at91-pio4: add microchip,sama7g5
  pinctrl: spear: simplify the return expression of tvc_connect()
  pinctrl: spear: simplify the return expression of spear310_pinctrl_probe
  pinctrl: sprd: use module_platform_driver to simplify the code
  pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs.
  ...
This commit is contained in:
Linus Torvalds 2020-10-14 15:25:04 -07:00
commit b4e1bce85f
120 changed files with 13025 additions and 1157 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

240
Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml Normal file
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@ -0,0 +1,240 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Actions Semi S500 SoC pinmux & GPIO controller
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
description: |
Pinmux & GPIO controller manages pin multiplexing & configuration including
GPIO function selection & GPIO attributes configuration. Please refer to
pinctrl-bindings.txt in this directory for common binding part and usage.
properties:
compatible:
const: actions,s500-pinctrl
reg:
items:
- description: GPIO Output + GPIO Input + GPIO Data
- description: Multiplexing Control
- description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control
- description: PAD Drive Capacity Select
minItems: 1
maxItems: 4
clocks:
maxItems: 1
gpio-controller: true
gpio-ranges:
maxItems: 1
'#gpio-cells':
description:
Specifies the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
interrupt-controller: true
'#interrupt-cells':
description:
Specifies the pin number and flags, as defined in
include/dt-bindings/interrupt-controller/irq.h
const: 2
interrupts:
description:
One interrupt per each of the 5 GPIO ports supported by the controller,
sorted by port number ascending order.
minItems: 5
maxItems: 5
patternProperties:
'-pins$':
type: object
patternProperties:
'^(.*-)?pinmux$':
type: object
description:
Pinctrl node's client devices specify pin muxes using subnodes,
which in turn use the standard properties below.
$ref: pinmux-node.yaml#
properties:
groups:
description:
List of gpio pin groups affected by the functions specified in
this subnode.
items:
oneOf:
- enum: [lcd0_d18_mfp, rmii_crs_dv_mfp, rmii_txd0_mfp,
rmii_txd1_mfp, rmii_txen_mfp, rmii_rxen_mfp, rmii_rxd1_mfp,
rmii_rxd0_mfp, rmii_ref_clk_mfp, i2s_d0_mfp, i2s_pcm1_mfp,
i2s0_pcm0_mfp, i2s1_pcm0_mfp, i2s_d1_mfp, ks_in2_mfp,
ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, ks_out0_mfp,
ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
dsi_dp2_mfp, lcd0_d17_mfp, dsi_dp3_mfp, dsi_dn3_mfp,
dsi_dp0_mfp, lvds_ee_pn_mfp, spi0_i2c_pcm_mfp,
spi0_i2s_pcm_mfp, dsi_dnp1_cp_mfp, lvds_e_pn_mfp,
dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp,
uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp,
pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp,
dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp,
nand_ceb3_mfp]
minItems: 1
maxItems: 32
function:
description:
Specify the alternative function to be configured for the
given gpio pin groups.
enum: [nor, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0,
i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
p0, sd0, sd1, sd2, i2c0, i2c1, i2c3, dsi, lvds, usb30, clko_25m,
mipi_csi, nand, spdif, ts, lcd0]
required:
- groups
- function
additionalProperties: false
'^(.*-)?pinconf$':
type: object
description:
Pinctrl node's client devices specify pin configurations using
subnodes, which in turn use the standard properties below.
$ref: pincfg-node.yaml#
properties:
groups:
description:
List of gpio pin groups affected by the drive-strength property
specified in this subnode.
items:
oneOf:
- enum: [sirq_drv, rmii_txd01_txen_drv, rmii_rxer_drv,
rmii_crs_drv, rmii_rxd10_drv, rmii_ref_clk_drv,
smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv,
i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv,
lcd_dsi_drv, dsi_drv, sd0_d0_d3_drv, sd1_d0_d3_drv,
sd0_cmd_drv, sd0_clk_drv, sd1_cmd_drv, sd1_clk_drv,
spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv,
i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv,
sens0_ckout_drv, uart3_all_drv]
minItems: 1
maxItems: 32
pins:
description:
List of gpio pins affected by the bias-pull-* and
input-schmitt-* properties specified in this subnode.
items:
oneOf:
- enum: [dnand_dqs, dnand_dqsn, eth_txd0, eth_txd1, eth_txen,
eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_ref_clk,
eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1,
i2s_mclk1, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0, ks_out1,
ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep,
lvds_een, lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp,
lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, lcd0_d17, dsi_dp3,
dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0,
dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0,
sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
uart0_tx, i2c0_sclk, i2c0_sdata, sensor0_pclk,
sensor0_ckout, dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1,
dnand_ceb2, dnand_ceb3, uart2_rx, uart2_tx, uart2_rtsb,
uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb,
pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, i2c1_sclk,
i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0,
csi_dn1, csi_dp1, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
csi_cn, csi_cp, dnand_d0, dnand_d1, dnand_d2, dnand_d3,
dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_rb, dnand_rdb,
dnand_rdbn, dnand_wrb, porb, clko_25m, bsel, pkg0, pkg1,
pkg2, pkg3]
minItems: 1
maxItems: 64
bias-pull-up: true
bias-pull-down: true
drive-strength:
description:
Selects the drive strength for the specified pins, in mA.
enum: [2, 4, 8, 12]
input-schmitt-enable: true
input-schmitt-disable: true
additionalProperties: false
additionalProperties: false
required:
- compatible
- reg
- clocks
- gpio-controller
- gpio-ranges
- '#gpio-cells'
- interrupt-controller
- '#interrupt-cells'
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl: pinctrl@b01b0000 {
compatible = "actions,s500-pinctrl";
reg = <0xb01b0000 0x40>, <0xb01b0040 0x10>,
<0xb01b0060 0x18>, <0xb01b0080 0xc>;
clocks = <&cmu 55>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 132>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
mmc0_pins: mmc0-pins {
pinmux {
groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
"sd0_cmd_mfp", "sd0_clk_mfp";
function = "sd0";
};
drv-pinconf {
groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
drive-strength = <8>;
};
bias-pinconf {
pins = "sd0_d0", "sd0_d1", "sd0_d2",
"sd0_d3", "sd0_cmd";
bias-pull-up;
};
};
};
...

129
Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
View File

@ -48,6 +48,8 @@ properties:
- allwinner,sun9i-a80-r-pinctrl
- allwinner,sun50i-a64-pinctrl
- allwinner,sun50i-a64-r-pinctrl
- allwinner,sun50i-a100-pinctrl
- allwinner,sun50i-a100-r-pinctrl
- allwinner,sun50i-h5-pinctrl
- allwinner,sun50i-h6-pinctrl
- allwinner,sun50i-h6-r-pinctrl
@ -59,7 +61,7 @@ properties:
interrupts:
minItems: 1
maxItems: 5
maxItems: 7
description:
One interrupt per external interrupt bank supported on the
controller, sorted by bank number ascending order.
@ -143,6 +145,18 @@ allOf:
# boards are defining it at the moment so it would generate a lot of
# warnings.
- if:
properties:
compatible:
enum:
- allwinner,sun50i-a100-pinctrl
then:
properties:
interrupts:
minItems: 7
maxItems: 7
- if:
properties:
compatible:
@ -155,62 +169,75 @@ allOf:
minItems: 5
maxItems: 5
else:
if:
properties:
compatible:
enum:
- allwinner,sun6i-a31-pinctrl
- allwinner,sun6i-a31s-pinctrl
- allwinner,sun50i-h6-pinctrl
- if:
properties:
compatible:
enum:
- allwinner,sun6i-a31-pinctrl
- allwinner,sun6i-a31s-pinctrl
- allwinner,sun50i-h6-pinctrl
then:
properties:
interrupts:
minItems: 4
maxItems: 4
then:
properties:
interrupts:
minItems: 4
maxItems: 4
else:
if:
properties:
compatible:
enum:
- allwinner,sun8i-a23-pinctrl
- allwinner,sun8i-a83t-pinctrl
- allwinner,sun50i-a64-pinctrl
- allwinner,sun50i-h5-pinctrl
- allwinner,suniv-f1c100s-pinctrl
- if:
properties:
compatible:
enum:
- allwinner,sun8i-a23-pinctrl
- allwinner,sun8i-a83t-pinctrl
- allwinner,sun50i-a64-pinctrl
- allwinner,sun50i-h5-pinctrl
- allwinner,suniv-f1c100s-pinctrl
then:
properties:
interrupts:
minItems: 3
maxItems: 3
then:
properties:
interrupts:
minItems: 3
maxItems: 3
else:
if:
properties:
compatible:
enum:
- allwinner,sun6i-a31-r-pinctrl
- allwinner,sun8i-a33-pinctrl
- allwinner,sun8i-h3-pinctrl
- allwinner,sun8i-v3-pinctrl
- allwinner,sun8i-v3s-pinctrl
- allwinner,sun9i-a80-r-pinctrl
- allwinner,sun50i-h6-r-pinctrl
- if:
properties:
compatible:
enum:
- allwinner,sun6i-a31-r-pinctrl
- allwinner,sun8i-a33-pinctrl
- allwinner,sun8i-h3-pinctrl
- allwinner,sun8i-v3-pinctrl
- allwinner,sun8i-v3s-pinctrl
- allwinner,sun9i-a80-r-pinctrl
- allwinner,sun50i-h6-r-pinctrl
then:
properties:
interrupts:
minItems: 2
maxItems: 2
then:
properties:
interrupts:
minItems: 2
maxItems: 2
else:
properties:
interrupts:
minItems: 1
maxItems: 1
- if:
properties:
compatible:
enum:
- allwinner,sun4i-a10-pinctrl
- allwinner,sun5i-a10s-pinctrl
- allwinner,sun5i-a13-pinctrl
- allwinner,sun7i-a20-pinctrl
- allwinner,sun8i-a23-r-pinctrl
- allwinner,sun8i-a83t-r-pinctrl
- allwinner,sun8i-h3-r-pinctrl
- allwinner,sun8i-r40-pinctrl
- allwinner,sun50i-a64-r-pinctrl
- allwinner,sun50i-a100-r-pinctrl
- nextthing,gr8-pinctrl
then:
properties:
interrupts:
minItems: 1
maxItems: 1
additionalProperties: false

4
Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
View File

@ -4,7 +4,9 @@ The Atmel PIO4 controller is used to select the function of a pin and to
configure it.
Required properties:
- compatible: "atmel,sama5d2-pinctrl".
- compatible:
"atmel,sama5d2-pinctrl"
"microchip,sama7g5-pinctrl"
- reg: base address and length of the PIO controller.
- interrupts: interrupt outputs from the controller, one for each bank.
- interrupt-controller: mark the device node as an interrupt controller.

1
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
View File

@ -10,6 +10,7 @@ Required properties:
"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
"mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to

155
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml Normal file
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@ -0,0 +1,155 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT8192 Pin Controller
maintainers:
- Sean Wang <sean.wang@mediatek.com>
description: |
The Mediatek's Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8192-pinctrl
gpio-controller: true
'#gpio-cells':
description: |
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
const: 2
gpio-ranges:
description: gpio valid number range.
maxItems: 1
reg:
description: |
Physical address base for gpio base registers. There are 11 GPIO
physical address base in mt8192.
maxItems: 11
reg-names:
description: |
Gpio base register names.
maxItems: 11
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
description: The interrupt outputs to sysirq.
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'^pins':
type: object
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and
input schmitt.
An example of using macro:
pincontroller {
/* GPIO0 set as multifunction GPIO0 */
state_0_node_a {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
};
/* GPIO1 set as multifunction PWM */
state_0_node_b {
pinmux = <PINMUX_GPIO1__FUNC_PWM_1>;
};
};
$ref: "pinmux-node.yaml"
properties:
pinmux:
description: |
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
drive-strength:
description: |
It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
enum: [2, 4, 6, 8, 10, 12, 14, 16]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pio: pinctrl@10005000 {
compatible = "mediatek,mt8192-pinctrl";
reg = <0x10005000 0x1000>,
<0x11c20000 0x1000>,
<0x11d10000 0x1000>,
<0x11d30000 0x1000>,
<0x11d40000 0x1000>,
<0x11e20000 0x1000>,
<0x11e70000 0x1000>,
<0x11ea0000 0x1000>,
<0x11f20000 0x1000>,
<0x11f30000 0x1000>,
<0x1000b000 0x1000>;
reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
"iocfg_bl", "iocfg_br", "iocfg_lm",
"iocfg_lb", "iocfg_rt", "iocfg_lt",
"iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 220>;
interrupt-controller;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
pins {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
output-low;
};
};

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@ -94,16 +94,23 @@ pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
specified in the pinctrl-bindings.txt document in this directory.
The pin configuration nodes for pinctrl-single are specified as pinctrl
register offset and value pairs using pinctrl-single,pins. Only the bits
specified in pinctrl-single,function-mask are updated. For example, setting
a pin for a device could be done with:
register offset and values using pinctrl-single,pins. Only the bits specified
in pinctrl-single,function-mask are updated.
When #pinctrl-cells = 1, then setting a pin for a device could be done with:
pinctrl-single,pins = <0xdc 0x118>;
Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, and 0x118 contains the desired value of the
pinctrl register. See the device example and static board pins example
below for more information.
Where 0xdc is the offset from the pinctrl register base address for the device
pinctrl register, and 0x118 contains the desired value of the pinctrl register.
When #pinctrl-cells = 2, then setting a pin for a device could be done with:
pinctrl-single,pins = <0xdc 0x30 0x07>;
Where 0x30 is the pin configuration value and 0x07 is the pin mux mode value.
These two values are OR'd together to produce the value stored at offset 0xdc.
See the device example and static board pins example below for more information.
In case when one register changes more than one pin's mux the
pinctrl-single,bits need to be used which takes three parameters:

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. MSM8226 TLMM block
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
This binding describes the Top Level Mode Multiplexer block found in the
MSM8226 platform.
properties:
compatible:
const: qcom,msm8226-pinctrl
reg:
description: Specifies the base address and size of the TLMM register space
maxItems: 1
interrupts:
description: Specifies the TLMM summary IRQ
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
description: Specifies the PIN numbers and Flags, as defined in
include/dt-bindings/interrupt-controller/irq.h
const: 2
gpio-controller: true
'#gpio-cells':
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
gpio-ranges:
maxItems: 1
gpio-reserved-ranges:
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins. Functions are only valid for gpio pins.
enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c5, blsp_spi1,
blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
blsp_uart3, blsp_uart5, cam_mclk0, cam_mclk1, wlan ]
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
msmgpio: pinctrl@fd510000 {
compatible = "qcom,msm8226-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&msmgpio 0 0 117>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
serial-pins {
pins = "gpio8", "gpio9";
function = "blsp_uart3";
drive-strength = <8>;
bias-disable;
};
};

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* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0,
R8A73A4 and R8A7740 it also acts as a GPIO controller.
Pin Control
-----------
Required Properties:
- compatible: should be one of the following.
- "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller.
- "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
- "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller.
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
- "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.
- "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller.
- "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.
- "renesas,pfc-r8a774e1": for R8A774E1 (RZ/G2H) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
- "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller.
- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A77960 (R-Car M3-W) compatible pin-controller.
- "renesas,pfc-r8a77961": for R8A77961 (R-Car M3-W+) compatible pin-controller.
- "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
- "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.
- "renesas,pfc-r8a77990": for R8A77990 (R-Car E3) compatible pin-controller.
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
controller hardware module.
Optional properties:
- #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden
otherwise. Should be 3.
- interrupts-extended: Specify the interrupts associated with external
IRQ pins. This property is mandatory when the PFC handles GPIOs and
forbidden otherwise. When specified, it must contain one interrupt per
external IRQ, sorted by external IRQ number.
The PFC node also acts as a container for pin configuration nodes. Please refer
to pinctrl-bindings.txt in this directory for the definition of the term "pin
configuration node" and for the common pinctrl bindings used by client devices.
Each pin configuration node represents a desired configuration for a pin, a
pin group, or a list of pins or pin groups. The configuration can include the
function to select on those pin(s) and pin configuration parameters (such as
pull-up and pull-down).
Pin configuration nodes contain pin configuration properties, either directly
or grouped in child subnodes. Both pin muxing and configuration parameters can
be grouped in that way and referenced as a single pin configuration node by
client devices.
A configuration node or subnode must reference at least one pin (through the
pins or pin groups properties) and contain at least a function or one
configuration parameter. When the function is present only pin groups can be
used to reference pins.
All pin configuration nodes and subnodes names are ignored. All of those nodes
are parsed through phandles and processed purely based on their content.
Pin Configuration Node Properties:
- pins : An array of strings, each string containing the name of a pin.
- groups : An array of strings, each string containing the name of a pin
group.
- function: A string containing the name of the function to mux to the pin
group(s) specified by the groups property.
Valid values for pin, group and function names can be found in the group and
function arrays of the PFC data file corresponding to the SoC
(drivers/pinctrl/sh-pfc/pfc-*.c)
The pin configuration parameters use the generic pinconf bindings defined in
pinctrl-bindings.txt in this directory. The supported parameters are
bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For
pins that have a configurable I/O voltage, the power-source value should be the
nominal I/O voltage in millivolts.
GPIO
----
On SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller node.
Required Properties:
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
The syntax of the gpio specifier used by client nodes should be the following
with values derived from the SoC user manual.
<[phandle of the gpio controller node]
[pin number within the gpio controller]
[flags]>
On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver.
Please refer to Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml
for documentation of the GPIO device tree bindings on those platforms.
Examples
--------
Example 1: SH73A0 (SH-Mobile AG5) pin controller node
pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-sh73a0";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;
gpio-controller;
#gpio-cells = <2>;
interrupts-extended =
<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
};
Example 2: A GPIO LED node that references a GPIO
#include <dt-bindings/gpio/gpio.h>
leds {
compatible = "gpio-leds";
led1 {
gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
};
};
Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
for the MMCIF and SCIFA4 devices
&pfc {
pinctrl-0 = <&scifa4_pins>;
pinctrl-names = "default";
mmcif_pins: mmcif {
mux {
groups = "mmc0_data8_0", "mmc0_ctrl_0";
function = "mmc0";
};
cfg {
groups = "mmc0_data8_0";
pins = "PORT279";
bias-pull-up;
};
};
scifa4_pins: scifa4 {
groups = "scifa4_data", "scifa4_ctrl";
function = "scifa4";
};
};
Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
&mmcif {
pinctrl-0 = <&mmcif_pins>;
pinctrl-names = "default";
bus-width = <8>;
vmmc-supply = <&reg_1p8v>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,pfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Pin Function Controller (GPIO and Pin Mux/Config)
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The Pin Function Controller (PFC) is a Pin Mux/Config controller.
On SH/R-Mobile SoCs it also acts as a GPIO controller.
properties:
compatible:
enum:
- renesas,pfc-emev2 # EMMA Mobile EV2
- renesas,pfc-r8a73a4 # R-Mobile APE6
- renesas,pfc-r8a7740 # R-Mobile A1
- renesas,pfc-r8a7742 # RZ/G1H
- renesas,pfc-r8a7743 # RZ/G1M
- renesas,pfc-r8a7744 # RZ/G1N
- renesas,pfc-r8a7745 # RZ/G1E
- renesas,pfc-r8a77470 # RZ/G1C
- renesas,pfc-r8a774a1 # RZ/G2M
- renesas,pfc-r8a774b1 # RZ/G2N
- renesas,pfc-r8a774c0 # RZ/G2E
- renesas,pfc-r8a774e1 # RZ/G2H
- renesas,pfc-r8a7778 # R-Car M1
- renesas,pfc-r8a7779 # R-Car H1
- renesas,pfc-r8a7790 # R-Car H2
- renesas,pfc-r8a7791 # R-Car M2-W
- renesas,pfc-r8a7792 # R-Car V2H
- renesas,pfc-r8a7793 # R-Car M2-N
- renesas,pfc-r8a7794 # R-Car E2
- renesas,pfc-r8a7795 # R-Car H3
- renesas,pfc-r8a7796 # R-Car M3-W
- renesas,pfc-r8a77961 # R-Car M3-W+
- renesas,pfc-r8a77965 # R-Car M3-N
- renesas,pfc-r8a77970 # R-Car V3M
- renesas,pfc-r8a77980 # R-Car V3H
- renesas,pfc-r8a77990 # R-Car E3
- renesas,pfc-r8a77995 # R-Car D3
- renesas,pfc-sh73a0 # SH-Mobile AG5
reg:
minItems: 1
maxItems: 2
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges:
minItems: 1
maxItems: 16
interrupts-extended:
minItems: 32
maxItems: 64
description:
Specify the interrupts associated with external IRQ pins on SoCs where
the PFC acts as a GPIO controller. It must contain one interrupt per
external IRQ, sorted by external IRQ number.
power-domains:
maxItems: 1
required:
- compatible
- reg
if:
properties:
compatible:
items:
enum:
- renesas,pfc-r8a73a4
- renesas,pfc-r8a7740
- renesas,pfc-sh73a0
then:
required:
- interrupts-extended
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- power-domains
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
Client device subnodes use below standard properties.
properties:
phandle: true
function: true
groups: true
pins: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength:
enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of supported values
power-source:
enum: [ 1800, 3300 ]
gpio-hog: true
gpios: true
input: true
output-high: true
output-low: true
additionalProperties: false
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
examples:
- |
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a7740";
reg = <0xe6050000 0x8000>,
<0xe605800c 0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 0 212>;
interrupts-extended =
<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
power-domains = <&pd_c5>;
lcd0-mux-hog {
/* DBGMD/LCDC0/FSIA MUX */
gpio-hog;
gpios = <176 0>;
output-high;
};
};
- |
pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7795";
reg = <0xe6060000 0x50c>;
avb_pins: avb {
mux {
groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb";
};
pins_mdio {
groups = "avb_mdio";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC",
"PIN_AVB_TD0", "PIN_AVB_TD1", "PIN_AVB_TD2",
"PIN_AVB_TD3";
drive-strength = <12>;
};
};
keys_pins: keys {
pins = "GP_5_17", "GP_5_20", "GP_5_22", "GP_2_1";
bias-pull-up;
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
};

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Renesas RZ/A1 combined Pin and GPIO controller
The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
named "Ports" in the hardware reference manual.
Pin multiplexing and GPIO configuration is performed on a per-pin basis
writing configuration values to per-port register sets.
Each "port" features up to 16 pins, each of them configurable for GPIO
function (port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
Pin controller node
-------------------
Required properties:
- compatible: should be:
- "renesas,r7s72100-ports": for RZ/A1H
- "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
- "renesas,r7s72102-ports": for RZ/A1L
- reg
address base and length of the memory area where the pin controller
hardware is mapped to.
Example:
Pin controller node for RZ/A1H SoC (r7s72100)
pinctrl: pin-controller@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
};
Sub-nodes
---------
The child nodes of the pin controller node describe a pin multiplexing
function or a GPIO controller alternatively.
- Pin multiplexing sub-nodes:
A pin multiplexing sub-node describes how to configure a set of
(or a single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
A few alternate function require special pin configuration flags to be
supplied along with the alternate function configuration number.
The hardware reference manual specifies when a pin function requires
"software IO driven" mode to be specified. To do so use the generic
properties from the <include/linux/pinctrl/pinconf_generic.h> header file
to instruct the pin controller to perform the desired pin configuration
operation.
Please refer to pinctrl-bindings.txt to get to know more on generic
pin properties usage.
The allowed generic formats for a pin multiplexing sub-node are the
following ones:
node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
node-2 {
sub-node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
sub-node-2 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
...
sub-node-n {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
};
Use the second format when pins part of the same logical group need to have
different generic pin configuration flags applied.
Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
of the most external one.
Eg.
client-1 {
...
pinctrl-0 = <&node-1>;
...
};
client-2 {
...
pinctrl-0 = <&node-2>;
...
};
Required properties:
- pinmux:
integer array representing pin number and pin multiplexing configuration.
When a pin has to be configured in alternate function mode, use this
property to identify the pin by its global index, and provide its
alternate function configuration number along with it.
When multiple pins are required to be configured as part of the same
alternate function they shall be specified as members of the same
argument list of a single "pinmux" property.
Helper macros to ease assembling the pin index from its position
(port where it sits on and pin number) and alternate function identifier
are provided by the pin controller header file at:
<include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
Integers values in "pinmux" argument list are assembled as:
((PORT * 16 + PIN) | MUX_FUNC << 16)
Optional generic properties:
- input-enable:
enable input bufer for pins requiring software driven IO input
operations.
- output-high:
enable output buffer for pins requiring software driven IO output
operations. output-low can be used alternatively, as line value is
ignored by the driver.
The hardware reference manual specifies when a pin has to be configured to
work in bi-directional mode and when the IO direction has to be specified
by software. Bi-directional pins are managed by the pin controller driver
internally, while software driven IO direction has to be explicitly
selected when multiple options are available.
Example:
A serial communication interface with a TX output pin and an RX input pin.
&pinctrl {
scif2_pins: serial2 {
pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
};
};
Pin #0 on port #3 is configured as alternate function #6.
Pin #2 on port #3 is configured as alternate function #4.
Example 2:
I2c master: both SDA and SCL pins need bi-directional operations
&pinctrl {
i2c2_pins: i2c2 {
pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
};
};
Pin #4 on port #1 is configured as alternate function #1.
Pin #5 on port #1 is configured as alternate function #1.
Both need to work in bi-directional mode, the driver manages this internally.
Example 3:
Multi-function timer input and output compare pins.
Configure TIOC0A as software driven input and TIOC0B as software driven
output.
&pinctrl {
tioc0_pins: tioc0 {
tioc0_input_pins {
pinumx = <RZA1_PINMUX(4, 0, 2)>;
input-enable;
};
tioc0_output_pins {
pinmux = <RZA1_PINMUX(4, 1, 1)>;
output-enable;
};
};
};
&tioc0 {
...
pinctrl-0 = <&tioc0_pins>;
...
};
Pin #0 on port #4 is configured as alternate function #2 with IO direction
specified by software as input.
Pin #1 on port #4 is configured as alternate function #1 with IO direction
specified by software as output.
- GPIO controller sub-nodes:
Each port of the r7s72100 pin controller hardware is itself a GPIO controller.
Different SoCs have different numbers of available pins per port, but
generally speaking, each of them can be configured in GPIO ("port") mode
on this hardware.
Describe GPIO controllers using sub-nodes with the following properties.
Required properties:
- gpio-controller
empty property as defined by the GPIO bindings documentation.
- #gpio-cells
number of cells required to identify and configure a GPIO.
Shall be 2.
- gpio-ranges
Describes a GPIO controller specifying its specific pin base, the pin
base in the global pin numbering space, and the number of controlled
pins, as defined by the GPIO bindings documentation. Refer to
Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed
description.
Example:
A GPIO controller node, controlling 16 pins indexed from 0.
The GPIO controller base in the global pin indexing space is pin 48, thus
pins [0 - 15] on this controller map to pins [48 - 63] in the global pin
indexing space.
port3: gpio-3 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 48 16>;
};
A device node willing to use pins controlled by this GPIO controller, shall
refer to it as follows:
led1 {
gpios = <&port3 10 GPIO_ACTIVE_LOW>;
};

190
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@ -0,0 +1,190 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/A1 combined Pin and GPIO controller
maintainers:
- Jacopo Mondi <jacopo+renesas@jmondi.org>
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
controller, named "Ports" in the hardware reference manual.
Pin multiplexing and GPIO configuration is performed on a per-pin basis
writing configuration values to per-port register sets.
Each "port" features up to 16 pins, each of them configurable for GPIO
function (port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
properties:
compatible:
oneOf:
- const: renesas,r7s72100-ports # RZ/A1H
- items:
- const: renesas,r7s72101-ports # RZ/A1M
- const: renesas,r7s72100-ports # fallback
- const: renesas,r7s72102-ports # RZ/A1L
reg:
maxItems: 1
required:
- compatible
- reg
patternProperties:
"^gpio-[0-9]*$":
type: object
description:
Each port of the r7s72100 pin controller hardware is itself a GPIO
controller.
Different SoCs have different numbers of available pins per port, but
generally speaking, each of them can be configured in GPIO ("port") mode
on this hardware.
Describe GPIO controllers using sub-nodes with the following properties.
properties:
gpio-controller: true
'#gpio-cells':
const: 2
gpio-ranges:
maxItems: 1
required:
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
A pin multiplexing sub-node describes how to configure a set of (or a
single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
A few alternate function require special pin configuration flags to be
supplied along with the alternate function configuration number.
The hardware reference manual specifies when a pin function requires
"software IO driven" mode to be specified. To do so use the generic
properties from the <include/linux/pinctrl/pinconf_generic.h> header
file to instruct the pin controller to perform the desired pin
configuration operation.
The hardware reference manual specifies when a pin has to be configured
to work in bi-directional mode and when the IO direction has to be
specified by software. Bi-directional pins must be managed by the pin
controller driver internally, while software driven IO direction has to
be explicitly selected when multiple options are available.
properties:
pinmux:
description: |
Integer array representing pin number and pin multiplexing
configuration.
When a pin has to be configured in alternate function mode, use
this property to identify the pin by its global index, and provide
its alternate function configuration number along with it.
When multiple pins are required to be configured as part of the
same alternate function they shall be specified as members of the
same argument list of a single "pinmux" property.
Helper macros to ease assembling the pin index from its position
(port where it sits on and pin number) and alternate function
identifier are provided by the pin controller header file at:
<include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
Integers values in "pinmux" argument list are assembled as:
((PORT * 16 + PIN) | MUX_FUNC << 16)
phandle: true
input-enable: true
output-enable: true
required:
- pinmux
additionalProperties: false
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
examples:
- |
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
pinctrl: pinctrl@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
/*
* A GPIO controller node, controlling 16 pins indexed from 0.
* The GPIO controller base in the global pin indexing space is pin
* 48, thus pins [0 - 15] on this controller map to pins [48 - 63]
* in the global pin indexing space.
*/
port3: gpio-3 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 48 16>;
};
/*
* A serial communication interface with a TX output pin and an RX
* input pin.
* Pin #0 on port #3 is configured as alternate function #6.
* Pin #2 on port #3 is configured as alternate function #4.
*/
scif2_pins: serial2 {
pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
};
/*
* I2c master: both SDA and SCL pins need bi-directional operations
* Pin #4 on port #1 is configured as alternate function #1.
* Pin #5 on port #1 is configured as alternate function #1.
* Both need to work in bi-directional mode, the driver must manage
* this internally.
*/
i2c2_pins: i2c2 {
pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
};
/*
* Multi-function timer input and output compare pins.
*/
tioc0_pins: tioc0 {
/*
* Configure TIOC0A as software driven input
* Pin #0 on port #4 is configured as alternate function #2
* with IO direction specified by software as input.
*/
tioc0_input_pins {
pinmux = <RZA1_PINMUX(4, 0, 2)>;
input-enable;
};
/*
* Configure TIOC0B as software driven output
* Pin #1 on port #4 is configured as alternate function #1
* with IO direction specified by software as output.
*/
tioc0_output_pins {
pinmux = <RZA1_PINMUX(4, 1, 1)>;
output-enable;
};
};
};

2
Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml
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@ -84,7 +84,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
pinctrl: pin-controller@fcffe000 {
pinctrl: pinctrl@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;

153
Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt
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@ -1,153 +0,0 @@
Renesas RZ/N1 SoC Pinctrl node description.
Pin controller node
-------------------
Required properties:
- compatible: SoC-specific compatible string "renesas,<soc-specific>-pinctrl"
followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible
strings must be one of:
"renesas,r9a06g032-pinctrl" for RZ/N1D
"renesas,r9a06g033-pinctrl" for RZ/N1S
- reg: Address base and length of the memory area where the pin controller
hardware is mapped to.
- clocks: phandle for the clock, see the description of clock-names below.
- clock-names: Contains the name of the clock:
"bus", the bus clock, sometimes described as pclk, for register accesses.
Example:
pinctrl: pin-controller@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
clock-names = "bus";
};
Sub-nodes
---------
The child nodes of the pin controller node describe a pin multiplexing
function.
- Pin multiplexing sub-nodes:
A pin multiplexing sub-node describes how to configure a set of
(or a single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
Please refer to pinctrl-bindings.txt to get to know more on generic
pin properties usage.
The allowed generic formats for a pin multiplexing sub-node are the
following ones:
node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
node-2 {
sub-node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
sub-node-2 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
...
sub-node-n {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
};
node-3 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
sub-node-1 {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
...
sub-node-n {
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
GENERIC_PINCONFIG;
};
};
Use the latter two formats when pins part of the same logical group need to
have different generic pin configuration flags applied. Note that the generic
pinconfig in node-3 does not apply to the sub-nodes.
Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
of the most external one.
Eg.
client-1 {
...
pinctrl-0 = <&node-1>;
...
};
client-2 {
...
pinctrl-0 = <&node-2>;
...
};
Required properties:
- pinmux:
integer array representing pin number and pin multiplexing configuration.
When a pin has to be configured in alternate function mode, use this
property to identify the pin by its global index, and provide its
alternate function configuration number along with it.
When multiple pins are required to be configured as part of the same
alternate function they shall be specified as members of the same
argument list of a single "pinmux" property.
Integers values in the "pinmux" argument list are assembled as:
(PIN | MUX_FUNC << 8)
where PIN directly corresponds to the pl_gpio pin number and MUX_FUNC is
one of the alternate function identifiers defined in:
<include/dt-bindings/pinctrl/rzn1-pinctrl.h>
These identifiers collapse the IO Multiplex Configuration Level 1 and
Level 2 numbers that are detailed in the hardware reference manual into a
single number. The identifiers for Level 2 are simply offset by 10.
Additional identifiers are provided to specify the MDIO source peripheral.
Optional generic pinconf properties:
- bias-disable - disable any pin bias
- bias-pull-up - pull up the pin with 50 KOhm
- bias-pull-down - pull down the pin with 50 KOhm
- bias-high-impedance - high impedance mode
- drive-strength - sink or source at most 4, 6, 8 or 12 mA
Example:
A serial communication interface with a TX output pin and an RX input pin.
&pinctrl {
pins_uart0: pins_uart0 {
pinmux = <
RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
>;
};
};
Example 2:
Here we set the pull up on the RXD pin of the UART.
&pinctrl {
pins_uart0: pins_uart0 {
pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>; /* TXD */
pins_uart6_rx {
pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>; /* RXD */
bias-pull-up;
};
};
};

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@ -0,0 +1,129 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/N1 Pin Controller
maintainers:
- Gareth Williams <gareth.williams.jx@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
items:
- enum:
- renesas,r9a06g032-pinctrl # RZ/N1D
- renesas,r9a06g033-pinctrl # RZ/N1S
- const: renesas,rzn1-pinctrl # Generic RZ/N1
reg:
items:
- description: GPIO Multiplexing Level1 Register Block
- description: GPIO Multiplexing Level2 Register Block
clocks:
maxItems: 1
clock-names:
const: bus
description:
The bus clock, sometimes described as pclk, for register accesses.
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
A pin multiplexing sub-node describes how to configure a set of (or a
single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
properties:
pinmux:
description: |
Integer array representing pin number and pin multiplexing
configuration.
When a pin has to be configured in alternate function mode, use
this property to identify the pin by its global index, and provide
its alternate function configuration number along with it.
When multiple pins are required to be configured as part of the
same alternate function they shall be specified as members of the
same argument list of a single "pinmux" property.
Integers values in the "pinmux" argument list are assembled as:
(PIN | MUX_FUNC << 8)
where PIN directly corresponds to the pl_gpio pin number and
MUX_FUNC is one of the alternate function identifiers defined in:
<include/dt-bindings/pinctrl/rzn1-pinctrl.h>
These identifiers collapse the IO Multiplex Configuration Level 1
and Level 2 numbers that are detailed in the hardware reference
manual into a single number. The identifiers for Level 2 are simply
offset by 10. Additional identifiers are provided to specify the
MDIO source peripheral.
phandle: true
bias-disable: true
bias-pull-up:
description: Pull up the pin with 50 kOhm
bias-pull-down:
description: Pull down the pin with 50 kOhm
bias-high-impedance: true
drive-strength:
enum: [ 4, 6, 8, 12 ]
required:
- pinmux
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
examples:
- |
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
pinctrl: pinctrl@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
clock-names = "bus";
/*
* A serial communication interface with a TX output pin and an RX
* input pin.
*/
pins_uart0: pins_uart0 {
pinmux = <
RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
>;
};
/*
* Set the pull-up on the RXD pin of the UART.
*/
pins_uart0_alt: pins_uart0_alt {
pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;
pins_uart6_rx {
pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
bias-pull-up;
};
};
};

92
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@ -0,0 +1,92 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Toshiba Visconti TMPV770x pin mux/config controller
maintainers:
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
description:
Toshiba's Visconti ARM SoC a pin mux/config controller.
properties:
compatible:
enum:
- toshiba,tmpv7708-pinctrl
reg:
maxItems: 1
required:
- compatible
- reg
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength.
$ref: "pinmux-node.yaml"
properties:
function:
description:
Function to mux.
$ref: "/schemas/types.yaml#/definitions/string"
enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8,
spi0, spi1, spi2, spi3, spi4, spi5, spi6,
uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in]
groups:
description:
Name of the pin group to use for the functions.
$ref: "/schemas/types.yaml#/definitions/string"
enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp,
i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp,
spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp,
spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp,
uart0_grp, uart1_grp, uart2_grp, uart3_grp,
pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp,
pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp,
pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp,
pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp,
pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp,
pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp]
drive-strength:
enum: [2, 4, 6, 8, 16, 24, 32]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
bias-pull-up: true
bias-pull-down: true
bias-disable: true
additionalProperties: false
examples:
# Pinmux controller node
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pmux: pmux@24190000 {
compatible = "toshiba,tmpv7708-pinctrl";
reg = <0 0x24190000 0 0x10000>;
spi0_pins: spi0-pins {
function = "spi0";
groups = "spi0_grp";
};
};
};

7
MAINTAINERS
View File

@ -1538,7 +1538,7 @@ F: Documentation/devicetree/bindings/dma/owl-dma.txt
F: Documentation/devicetree/bindings/i2c/i2c-owl.txt
F: Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
F: Documentation/devicetree/bindings/mmc/owl-mmc.yaml
F: Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt
F: Documentation/devicetree/bindings/pinctrl/actions,*
F: Documentation/devicetree/bindings/power/actions,owl-sps.txt
F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt
F: arch/arm/boot/dts/owl-*
@ -13738,10 +13738,9 @@ PIN CONTROLLER - RENESAS
M: Geert Uytterhoeven <geert+renesas@glider.be>
L: linux-renesas-soc@vger.kernel.org
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-pinctrl
F: Documentation/devicetree/bindings/pinctrl/renesas,*
F: drivers/pinctrl/pinctrl-rz*
F: drivers/pinctrl/sh-pfc/
F: drivers/pinctrl/renesas/
PIN CONTROLLER - SAMSUNG
M: Tomasz Figa <tomasz.figa@gmail.com>

2
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@ -316,7 +316,7 @@
};
pcie_reset_pins: pcie-reset-pins {
groups = "pcie1";
groups = "pcie1"; /* this actually controls "pcie1_reset" */
function = "gpio";
};

37
drivers/pinctrl/Kconfig
View File

@ -208,42 +208,12 @@ config PINCTRL_OXNAS
config PINCTRL_ROCKCHIP
bool
depends on OF
select PINMUX
select GENERIC_PINCONF
select GENERIC_IRQ_CHIP
select MFD_SYSCON
config PINCTRL_RZA1
bool "Renesas RZ/A1 gpio and pinctrl driver"
depends on OF
depends on ARCH_R7S72100 || COMPILE_TEST
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects pinctrl driver for Renesas RZ/A1 platforms.
config PINCTRL_RZA2
bool "Renesas RZ/A2 gpio and pinctrl driver"
depends on OF
depends on ARCH_R7S9210 || COMPILE_TEST
select GPIOLIB
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_RZN1
bool "Renesas RZ/N1 pinctrl driver"
depends on OF
depends on ARCH_RZN1 || COMPILE_TEST
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
This selects pinctrl driver for Renesas RZ/N1 devices.
select OF_GPIO
config PINCTRL_SINGLE
tristate "One-register-per-pin type device tree based pinctrl driver"
@ -415,8 +385,8 @@ source "drivers/pinctrl/nomadik/Kconfig"
source "drivers/pinctrl/nuvoton/Kconfig"
source "drivers/pinctrl/pxa/Kconfig"
source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/sh-pfc/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sprd/Kconfig"
source "drivers/pinctrl/stm32/Kconfig"
@ -429,6 +399,7 @@ source "drivers/pinctrl/mediatek/Kconfig"
source "drivers/pinctrl/zte/Kconfig"
source "drivers/pinctrl/meson/Kconfig"
source "drivers/pinctrl/cirrus/Kconfig"
source "drivers/pinctrl/visconti/Kconfig"
config PINCTRL_XWAY
bool

6
drivers/pinctrl/Makefile
View File

@ -30,9 +30,6 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
@ -62,8 +59,8 @@ obj-y += nomadik/
obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/
obj-$(CONFIG_PINCTRL_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_PINCTRL_STM32) += stm32/
@ -74,3 +71,4 @@ obj-$(CONFIG_ARCH_VT8500) += vt8500/
obj-y += mediatek/
obj-$(CONFIG_PINCTRL_ZX) += zte/
obj-y += cirrus/
obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/

6
drivers/pinctrl/actions/Kconfig
View File

@ -10,6 +10,12 @@ config PINCTRL_OWL
help
Say Y here to enable Actions Semi OWL pinctrl driver
config PINCTRL_S500
bool "Actions Semi S500 pinctrl driver"
depends on PINCTRL_OWL
help
Say Y here to enable Actions Semi S500 pinctrl driver
config PINCTRL_S700
bool "Actions Semi S700 pinctrl driver"
depends on PINCTRL_OWL

1
drivers/pinctrl/actions/Makefile
View File

@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PINCTRL_OWL) += pinctrl-owl.o
obj-$(CONFIG_PINCTRL_S500) += pinctrl-s500.o
obj-$(CONFIG_PINCTRL_S700) += pinctrl-s700.o
obj-$(CONFIG_PINCTRL_S900) += pinctrl-s900.o

4
drivers/pinctrl/actions/pinctrl-owl.c
View File

@ -125,7 +125,7 @@ static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
seq_printf(s, "%s", dev_name(pctrl->dev));
}
static struct pinctrl_ops owl_pinctrl_ops = {
static const struct pinctrl_ops owl_pinctrl_ops = {
.get_groups_count = owl_get_groups_count,
.get_group_name = owl_get_group_name,
.get_group_pins = owl_get_group_pins,
@ -212,7 +212,7 @@ static int owl_set_mux(struct pinctrl_dev *pctrldev,
return 0;
}
static struct pinmux_ops owl_pinmux_ops = {
static const struct pinmux_ops owl_pinmux_ops = {
.get_functions_count = owl_get_funcs_count,
.get_function_name = owl_get_func_name,
.get_function_groups = owl_get_func_groups,

1727
drivers/pinctrl/actions/pinctrl-s500.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/pinctrl/actions/pinctrl-s700.c
View File

@ -1685,7 +1685,7 @@ static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1);
static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1);
/* Pad info table for the pinmux subsystem */
static struct owl_padinfo s700_padinfo[NUM_PADS] = {
static const struct owl_padinfo s700_padinfo[NUM_PADS] = {
[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
[ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
[ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),

2
drivers/pinctrl/actions/pinctrl-s900.c
View File

@ -1556,7 +1556,7 @@ static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
/* Pad info table */
static struct owl_padinfo s900_padinfo[NUM_PADS] = {
static const struct owl_padinfo s900_padinfo[NUM_PADS] = {
[ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
[ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
[ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),

17
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
View File

@ -19,6 +19,7 @@
#define SCU400 0x400 /* Multi-function Pin Control #1 */
#define SCU404 0x404 /* Multi-function Pin Control #2 */
#define SCU40C 0x40C /* Multi-function Pin Control #3 */
#define SCU410 0x410 /* Multi-function Pin Control #4 */
#define SCU414 0x414 /* Multi-function Pin Control #5 */
#define SCU418 0x418 /* Multi-function Pin Control #6 */
@ -2591,6 +2592,22 @@ static struct aspeed_pin_config aspeed_g6_configs[] = {
/* MAC4 */
{ PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)},
{ PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},
/* GPIO18E */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, Y4, SCU40C, 4),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, Y4, SCU40C, 4),
/* GPIO18D */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AB4, AC5, SCU40C, 3),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AB4, AC5, SCU40C, 3),
/* GPIO18C */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E4, E1, SCU40C, 2),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E4, E1, SCU40C, 2),
/* GPIO18B */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D3, SCU40C, 1),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D3, SCU40C, 1),
/* GPIO18A */
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C6, A2, SCU40C, 0),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C6, A2, SCU40C, 0),
};
/**

8
drivers/pinctrl/aspeed/pinctrl-aspeed.c
View File

@ -534,14 +534,14 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
val = pmap->val << __ffs(pconf->mask);
rc = regmap_update_bits(pdata->scu, pconf->reg,
pmap->mask, val);
pconf->mask, val);
if (rc < 0)
return rc;
pr_debug("%s: Set SCU%02X[%lu]=%d for param %d(=%d) on pin %d\n",
__func__, pconf->reg, __ffs(pconf->mask),
pmap->val, param, arg, offset);
pr_debug("%s: Set SCU%02X[0x%08X]=0x%X for param %d(=%d) on pin %d\n",
__func__, pconf->reg, pconf->mask,
val, param, arg, offset);
}
return 0;

5
drivers/pinctrl/devicetree.c
View File

@ -130,9 +130,8 @@ static int dt_to_map_one_config(struct pinctrl *p,
if (!np_pctldev || of_node_is_root(np_pctldev)) {
of_node_put(np_pctldev);
ret = driver_deferred_probe_check_state(p->dev);
/* keep deferring if modules are enabled unless we've timed out */
if (IS_ENABLED(CONFIG_MODULES) && !allow_default &&
(ret == -ENODEV))
/* keep deferring if modules are enabled */
if (IS_ENABLED(CONFIG_MODULES) && !allow_default && ret < 0)
ret = -EPROBE_DEFER;
return ret;
}

5
drivers/pinctrl/freescale/Kconfig
View File

@ -1,13 +1,14 @@
# SPDX-License-Identifier: GPL-2.0-only
config PINCTRL_IMX
bool
tristate
depends on OF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
select REGMAP
config PINCTRL_IMX_SCU
bool
tristate
depends on IMX_SCU
select PINCTRL_IMX

13
drivers/pinctrl/freescale/pinctrl-imx.c
View File

@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
@ -373,7 +374,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
const struct imx_pinctrl_soc_info *info = ipctl->info;
if (info->flags & IMX_USE_SCU)
return imx_pinconf_get_scu(pctldev, pin_id, config);
return info->imx_pinconf_get(pctldev, pin_id, config);
else
return imx_pinconf_get_mmio(pctldev, pin_id, config);
}
@ -423,7 +424,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
const struct imx_pinctrl_soc_info *info = ipctl->info;
if (info->flags & IMX_USE_SCU)
return imx_pinconf_set_scu(pctldev, pin_id,
return info->imx_pinconf_set(pctldev, pin_id,
configs, num_configs);
else
return imx_pinconf_set_mmio(pctldev, pin_id,
@ -440,7 +441,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
int ret;
if (info->flags & IMX_USE_SCU) {
ret = imx_pinconf_get_scu(pctldev, pin_id, &config);
ret = info->imx_pinconf_get(pctldev, pin_id, &config);
if (ret) {
dev_err(ipctl->dev, "failed to get %s pinconf\n",
pin_get_name(pctldev, pin_id));
@ -629,7 +630,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
for (i = 0; i < grp->num_pins; i++) {
pin = &((struct imx_pin *)(grp->data))[i];
if (info->flags & IMX_USE_SCU)
imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i],
info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i],
pin, &list);
else
imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
@ -898,3 +899,7 @@ const struct dev_pm_ops imx_pinctrl_pm_ops = {
imx_pinctrl_resume)
};
EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);
MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
MODULE_DESCRIPTION("NXP i.MX common pinctrl driver");
MODULE_LICENSE("GPL v2");

57
drivers/pinctrl/freescale/pinctrl-imx.h
View File

@ -75,6 +75,21 @@ struct imx_cfg_params_decode {
bool invert;
};
/**
* @dev: a pointer back to containing device
* @base: the offset to the controller in virtual memory
*/
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
struct imx_pin_reg *pin_regs;
unsigned int group_index;
struct mutex mutex;
};
struct imx_pinctrl_soc_info {
const struct pinctrl_pin_desc *pins;
unsigned int npins;
@ -98,21 +113,13 @@ struct imx_pinctrl_soc_info {
struct pinctrl_gpio_range *range,
unsigned offset,
bool input);
};
/**
* @dev: a pointer back to containing device
* @base: the offset to the controller in virtual memory
*/
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
void __iomem *input_sel_base;
const struct imx_pinctrl_soc_info *info;
struct imx_pin_reg *pin_regs;
unsigned int group_index;
struct mutex mutex;
int (*imx_pinconf_get)(struct pinctrl_dev *pctldev, unsigned int pin_id,
unsigned long *config);
int (*imx_pinconf_set)(struct pinctrl_dev *pctldev, unsigned int pin_id,
unsigned long *configs, unsigned int num_configs);
void (*imx_pinctrl_parse_pin)(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
const __be32 **list_p);
};
#define IMX_CFG_PARAMS_DECODE(p, m, o) \
@ -137,7 +144,6 @@ struct imx_pinctrl {
int imx_pinctrl_probe(struct platform_device *pdev,
const struct imx_pinctrl_soc_info *info);
#ifdef CONFIG_PINCTRL_IMX_SCU
#define BM_PAD_CTL_GP_ENABLE BIT(30)
#define BM_PAD_CTL_IFMUX_ENABLE BIT(31)
#define BP_PAD_CTL_IFMUX 27
@ -150,23 +156,4 @@ int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id, struct imx_pin *pin,
const __be32 **list_p);
#else
static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
return -EINVAL;
}
static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *configs,
unsigned num_configs)
{
return -EINVAL;
}
static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
unsigned int *pin_id,
struct imx_pin *pin,
const __be32 **list_p)
{
}
#endif
#endif /* __DRIVERS_PINCTRL_IMX_H */

3
drivers/pinctrl/freescale/pinctrl-imx8dxl.c
View File

@ -159,6 +159,9 @@ static struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = {
.pins = imx8dxl_pinctrl_pads,
.npins = ARRAY_SIZE(imx8dxl_pinctrl_pads),
.flags = IMX_USE_SCU,
.imx_pinconf_get = imx_pinconf_get_scu,
.imx_pinconf_set = imx_pinconf_set_scu,
.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
};
static const struct of_device_id imx8dxl_pinctrl_of_match[] = {

3
drivers/pinctrl/freescale/pinctrl-imx8qm.c
View File

@ -292,6 +292,9 @@ static const struct imx_pinctrl_soc_info imx8qm_pinctrl_info = {
.pins = imx8qm_pinctrl_pads,
.npins = ARRAY_SIZE(imx8qm_pinctrl_pads),
.flags = IMX_USE_SCU,
.imx_pinconf_get = imx_pinconf_get_scu,
.imx_pinconf_set = imx_pinconf_set_scu,
.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
};
static const struct of_device_id imx8qm_pinctrl_of_match[] = {

3
drivers/pinctrl/freescale/pinctrl-imx8qxp.c
View File

@ -198,6 +198,9 @@ static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
.pins = imx8qxp_pinctrl_pads,
.npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
.flags = IMX_USE_SCU,
.imx_pinconf_get = imx_pinconf_get_scu,
.imx_pinconf_set = imx_pinconf_set_scu,
.imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu,
};
static const struct of_device_id imx8qxp_pinctrl_of_match[] = {

5
drivers/pinctrl/freescale/pinctrl-scu.c
View File

@ -7,6 +7,7 @@
#include <linux/err.h>
#include <linux/firmware/imx/sci.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
@ -123,3 +124,7 @@ void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
pin_scu->mux_mode, pin_scu->config);
}
EXPORT_SYMBOL_GPL(imx_pinctrl_parse_pin_scu);
MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
MODULE_DESCRIPTION("NXP i.MX SCU common pinctrl driver");
MODULE_LICENSE("GPL v2");

12
drivers/pinctrl/intel/Kconfig
View File

@ -6,11 +6,7 @@ if (X86 || COMPILE_TEST)
config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control"
depends on ACPI
select GPIOLIB
select GPIOLIB_IRQCHIP
select PINMUX
select PINCONF
select GENERIC_PINCONF
select PINCTRL_INTEL
help
driver for memory mapped GPIO functionality on Intel Baytrail
platforms. Supports 3 banks with 102, 28 and 44 gpios.
@ -22,11 +18,7 @@ config PINCTRL_BAYTRAIL
config PINCTRL_CHERRYVIEW
tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
depends on ACPI
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB_IRQCHIP
select PINCTRL_INTEL
help
Cherryview/Braswell pinctrl driver provides an interface that
allows configuring of SoC pins and using them as GPIOs.

24
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -1635,28 +1635,14 @@ static const struct acpi_device_id byt_gpio_acpi_match[] = {
static int byt_pinctrl_probe(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *soc_data = NULL;
const struct intel_pinctrl_soc_data **soc_table;
const struct intel_pinctrl_soc_data *soc_data;
struct device *dev = &pdev->dev;
struct acpi_device *acpi_dev;
struct intel_pinctrl *vg;
int i, ret;
int ret;
acpi_dev = ACPI_COMPANION(dev);
if (!acpi_dev)
return -ENODEV;
soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev);
for (i = 0; soc_table[i]; i++) {
if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
soc_data = soc_table[i];
break;
}
}
if (!soc_data)
return -ENODEV;
soc_data = intel_pinctrl_get_soc_data(pdev);
if (IS_ERR(soc_data))
return PTR_ERR(soc_data);
vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
if (!vg)

22
drivers/pinctrl/intel/pinctrl-cannonlake.c
View File

@ -30,12 +30,12 @@
.gpio_base = (g), \
}
#define CNL_COMMUNITY(b, s, e, o, g) \
#define CNL_COMMUNITY(b, s, e, ho, g) \
{ \
.barno = (b), \
.padown_offset = CNL_PAD_OWN, \
.padcfglock_offset = CNL_PADCFGLOCK, \
.hostown_offset = (o), \
.hostown_offset = (ho), \
.is_offset = CNL_GPI_IS, \
.ie_offset = CNL_GPI_IE, \
.pin_base = (s), \
@ -44,10 +44,10 @@
.ngpps = ARRAY_SIZE(g), \
}
#define CNLLP_COMMUNITY(b, s, e, g) \
#define CNL_LP_COMMUNITY(b, s, e, g) \
CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)
#define CNLH_COMMUNITY(b, s, e, g) \
#define CNL_H_COMMUNITY(b, s, e, g) \
CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)
/* Cannon Lake-H */
@ -449,10 +449,10 @@ static const struct intel_function cnlh_functions[] = {
};
static const struct intel_community cnlh_communities[] = {
CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
CNL_H_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
CNL_H_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
CNL_H_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
CNL_H_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
};
static const struct intel_pinctrl_soc_data cnlh_soc_data = {
@ -810,9 +810,9 @@ static const struct intel_padgroup cnllp_community4_gpps[] = {
};
static const struct intel_community cnllp_communities[] = {
CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
CNL_LP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
CNL_LP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
CNL_LP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
};
static const struct intel_pinctrl_soc_data cnllp_soc_data = {

170
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -74,35 +74,11 @@ struct intel_pad_context {
};
/**
* struct chv_pinctrl - CHV pinctrl private structure
* @dev: Pointer to the parent device
* @pctldesc: Pin controller description
* @pctldev: Pointer to the pin controller device
* @chip: GPIO chip in this pin controller
* @irqchip: IRQ chip in this pin controller
* @soc: Community specific pin configuration data
* @communities: All communities in this pin controller
* @ncommunities: Number of communities in this pin controller
* @context: Configuration saved over system sleep
* @irq: Our parent irq
* struct intel_community_context - community context for Cherryview
* @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
* @saved_intmask: Interrupt mask saved for system sleep
*
* The first group in @groups is expected to contain all pins that can be
* used as GPIOs.
*/
struct chv_pinctrl {
struct device *dev;
struct pinctrl_desc pctldesc;
struct pinctrl_dev *pctldev;
struct gpio_chip chip;
struct irq_chip irqchip;
const struct intel_pinctrl_soc_data *soc;
struct intel_community *communities;
size_t ncommunities;
struct intel_pinctrl_context context;
int irq;
struct intel_community_context {
unsigned int intr_lines[16];
u32 saved_intmask;
};
@ -588,14 +564,14 @@ static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
*/
static DEFINE_RAW_SPINLOCK(chv_lock);
static u32 chv_pctrl_readl(struct chv_pinctrl *pctrl, unsigned int offset)
static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset)
{
const struct intel_community *community = &pctrl->communities[0];
return readl(community->regs + offset);
}
static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32 value)
static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)
{
const struct intel_community *community = &pctrl->communities[0];
void __iomem *reg = community->regs + offset;
@ -605,7 +581,7 @@ static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32
readl(reg);
}
static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset,
unsigned int reg)
{
const struct intel_community *community = &pctrl->communities[0];
@ -617,12 +593,12 @@ static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
return community->pad_regs + offset + reg;
}
static u32 chv_readl(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset)
static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset)
{
return readl(chv_padreg(pctrl, pin, offset));
}
static void chv_writel(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
{
void __iomem *reg = chv_padreg(pctrl, pin, offset);
@ -632,14 +608,14 @@ static void chv_writel(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int
}
/* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset)
static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
{
return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
}
static int chv_get_groups_count(struct pinctrl_dev *pctldev)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->ngroups;
}
@ -647,7 +623,7 @@ static int chv_get_groups_count(struct pinctrl_dev *pctldev)
static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->groups[group].name;
}
@ -655,7 +631,7 @@ static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
const unsigned int **pins, unsigned int *npins)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->soc->groups[group].pins;
*npins = pctrl->soc->groups[group].npins;
@ -665,7 +641,7 @@ static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned int offset)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
u32 ctrl0, ctrl1;
bool locked;
@ -704,7 +680,7 @@ static const struct pinctrl_ops chv_pinctrl_ops = {
static int chv_get_functions_count(struct pinctrl_dev *pctldev)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->nfunctions;
}
@ -712,7 +688,7 @@ static int chv_get_functions_count(struct pinctrl_dev *pctldev)
static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->soc->functions[function].name;
}
@ -722,7 +698,7 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev,
const char * const **groups,
unsigned int * const ngroups)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctrl->soc->functions[function].groups;
*ngroups = pctrl->soc->functions[function].ngroups;
@ -732,7 +708,7 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev,
static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int group)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct intel_pingroup *grp;
unsigned long flags;
int i;
@ -790,7 +766,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
return 0;
}
static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl,
unsigned int offset)
{
u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
@ -816,7 +792,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
u32 value;
@ -830,12 +806,13 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
return -EBUSY;
}
} else {
struct intel_community_context *cctx = &pctrl->context.communities[0];
int i;
/* Reset the interrupt mapping */
for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
if (pctrl->intr_lines[i] == offset) {
pctrl->intr_lines[i] = 0;
for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
if (cctx->intr_lines[i] == offset) {
cctx->intr_lines[i] = 0;
break;
}
}
@ -869,7 +846,7 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
raw_spin_lock_irqsave(&chv_lock, flags);
@ -884,7 +861,7 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset, bool input)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
unsigned long flags;
u32 ctrl0;
@ -915,7 +892,7 @@ static const struct pinmux_ops chv_pinmux_ops = {
static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *config)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned long flags;
u32 ctrl0, ctrl1;
@ -992,7 +969,7 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
return 0;
}
static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
enum pin_config_param param, u32 arg)
{
unsigned long flags;
@ -1057,7 +1034,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
return 0;
}
static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
bool enable)
{
unsigned long flags;
@ -1080,7 +1057,7 @@ static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int nconfigs)
{
struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param;
int i, ret;
u32 arg;
@ -1181,7 +1158,7 @@ static struct pinctrl_desc chv_pinctrl_desc = {
static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
unsigned long flags;
u32 ctrl0, cfg;
@ -1199,7 +1176,7 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
unsigned long flags;
u32 ctrl0;
@ -1219,7 +1196,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
u32 ctrl0, direction;
unsigned long flags;
@ -1262,7 +1239,7 @@ static const struct gpio_chip chv_gpio_chip = {
static void chv_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
int pin = irqd_to_hwirq(d);
u32 intr_line;
@ -1279,7 +1256,7 @@ static void chv_gpio_irq_ack(struct irq_data *d)
static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
int pin = irqd_to_hwirq(d);
u32 value, intr_line;
unsigned long flags;
@ -1324,7 +1301,8 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
*/
if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
struct intel_community_context *cctx = &pctrl->context.communities[0];
unsigned int pin = irqd_to_hwirq(d);
irq_flow_handler_t handler;
unsigned long flags;
@ -1341,9 +1319,9 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
else
handler = handle_edge_irq;
if (!pctrl->intr_lines[intsel]) {
if (!cctx->intr_lines[intsel]) {
irq_set_handler_locked(d, handler);
pctrl->intr_lines[intsel] = pin;
cctx->intr_lines[intsel] = pin;
}
raw_spin_unlock_irqrestore(&chv_lock, flags);
}
@ -1355,7 +1333,8 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
struct intel_community_context *cctx = &pctrl->context.communities[0];
unsigned int pin = irqd_to_hwirq(d);
unsigned long flags;
u32 value;
@ -1400,7 +1379,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
value &= CHV_PADCTRL0_INTSEL_MASK;
value >>= CHV_PADCTRL0_INTSEL_SHIFT;
pctrl->intr_lines[value] = pin;
cctx->intr_lines[value] = pin;
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_handler_locked(d, handle_edge_irq);
@ -1415,8 +1394,9 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
static void chv_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
const struct intel_community *community = &pctrl->communities[0];
struct intel_community_context *cctx = &pctrl->context.communities[0];
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long pending;
unsigned long flags;
@ -1431,7 +1411,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
for_each_set_bit(intr_line, &pending, community->nirqs) {
unsigned int irq, offset;
offset = pctrl->intr_lines[intr_line];
offset = cctx->intr_lines[intr_line];
irq = irq_find_mapping(gc->irq.domain, offset);
generic_handle_irq(irq);
}
@ -1484,7 +1464,7 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip,
unsigned long *valid_mask,
unsigned int ngpios)
{
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
const struct intel_community *community = &pctrl->communities[0];
int i;
@ -1506,7 +1486,7 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip,
static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
{
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
const struct intel_community *community = &pctrl->communities[0];
/*
@ -1532,7 +1512,7 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
{
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
const struct intel_community *community = &pctrl->communities[0];
const struct intel_padgroup *gpp;
int ret, i;
@ -1551,7 +1531,7 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
return 0;
}
static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
{
const struct intel_community *community = &pctrl->communities[0];
const struct intel_padgroup *gpp;
@ -1617,7 +1597,7 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
acpi_physical_address address, u32 bits, u64 *value,
void *handler_context, void *region_context)
{
struct chv_pinctrl *pctrl = region_context;
struct intel_pinctrl *pctrl = region_context;
unsigned long flags;
acpi_status ret = AE_OK;
@ -1637,34 +1617,23 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
static int chv_pinctrl_probe(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *soc_data = NULL;
const struct intel_pinctrl_soc_data **soc_table;
const struct intel_pinctrl_soc_data *soc_data;
struct intel_community *community;
struct device *dev = &pdev->dev;
struct chv_pinctrl *pctrl;
struct acpi_device *adev;
struct acpi_device *adev = ACPI_COMPANION(dev);
struct intel_pinctrl *pctrl;
acpi_status status;
int ret, irq, i;
int ret, irq;
adev = ACPI_COMPANION(&pdev->dev);
if (!adev)
return -ENODEV;
soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev);
for (i = 0; soc_table[i]; i++) {
if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
soc_data = soc_table[i];
break;
}
}
if (!soc_data)
return -ENODEV;
soc_data = intel_pinctrl_get_soc_data(pdev);
if (IS_ERR(soc_data))
return PTR_ERR(soc_data);
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
pctrl->dev = &pdev->dev;
pctrl->dev = dev;
pctrl->soc = soc_data;
pctrl->ncommunities = pctrl->soc->ncommunities;
@ -1689,19 +1658,24 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
return -ENOMEM;
#endif
pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities,
sizeof(*pctrl->context.communities),
GFP_KERNEL);
if (!pctrl->context.communities)
return -ENOMEM;
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
pctrl->pctldesc = chv_pinctrl_desc;
pctrl->pctldesc.name = dev_name(&pdev->dev);
pctrl->pctldesc.name = dev_name(dev);
pctrl->pctldesc.pins = pctrl->soc->pins;
pctrl->pctldesc.npins = pctrl->soc->npins;
pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
pctrl);
pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
if (IS_ERR(pctrl->pctldev)) {
dev_err(&pdev->dev, "failed to register pinctrl driver\n");
dev_err(dev, "failed to register pinctrl driver\n");
return PTR_ERR(pctrl->pctldev);
}
@ -1714,7 +1688,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
chv_pinctrl_mmio_access_handler,
NULL, pctrl);
if (ACPI_FAILURE(status))
dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
dev_err(dev, "failed to install ACPI addr space handler\n");
platform_set_drvdata(pdev, pctrl);
@ -1723,7 +1697,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
static int chv_pinctrl_remove(struct platform_device *pdev)
{
struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
const struct intel_community *community = &pctrl->communities[0];
acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
@ -1736,13 +1710,14 @@ static int chv_pinctrl_remove(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP
static int chv_pinctrl_suspend_noirq(struct device *dev)
{
struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_community_context *cctx = &pctrl->context.communities[0];
unsigned long flags;
int i;
raw_spin_lock_irqsave(&chv_lock, flags);
pctrl->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
for (i = 0; i < pctrl->soc->npins; i++) {
const struct pinctrl_pin_desc *desc;
@ -1765,7 +1740,8 @@ static int chv_pinctrl_suspend_noirq(struct device *dev)
static int chv_pinctrl_resume_noirq(struct device *dev)
{
struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
struct intel_community_context *cctx = &pctrl->context.communities[0];
unsigned long flags;
int i;
@ -1809,7 +1785,7 @@ static int chv_pinctrl_resume_noirq(struct device *dev)
* the interrupt mask register as well.
*/
chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
chv_pctrl_writel(pctrl, CHV_INTMASK, pctrl->saved_intmask);
chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
raw_spin_unlock_irqrestore(&chv_lock, flags);

24
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -1414,9 +1414,6 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
struct intel_pinctrl *pctrl;
int i, ret, irq;
if (!soc_data)
return -EINVAL;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
@ -1505,11 +1502,26 @@ int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
const struct intel_pinctrl_soc_data *data;
data = device_get_match_data(&pdev->dev);
if (!data)
return -ENODATA;
return intel_pinctrl_probe(pdev, data);
}
EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *data;
data = intel_pinctrl_get_soc_data(pdev);
if (IS_ERR(data))
return PTR_ERR(data);
return intel_pinctrl_probe(pdev, data);
}
EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *data = NULL;
const struct intel_pinctrl_soc_data **table;
@ -1532,15 +1544,15 @@ int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
id = platform_get_device_id(pdev);
if (!id)
return -ENODEV;
return ERR_PTR(-ENODEV);
table = (const struct intel_pinctrl_soc_data **)id->driver_data;
data = table[pdev->id];
}
return intel_pinctrl_probe(pdev, data);
return data ?: ERR_PTR(-ENODATA);
}
EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);
#ifdef CONFIG_PM_SLEEP
static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)

7
drivers/pinctrl/intel/pinctrl-intel.h
View File

@ -10,12 +10,15 @@
#ifndef PINCTRL_INTEL_H
#define PINCTRL_INTEL_H
#include <linux/bits.h>
#include <linux/compiler_types.h>
#include <linux/gpio/driver.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/spinlock_types.h>
struct pinctrl_pin_desc;
struct platform_device;
struct device;
@ -194,6 +197,8 @@ struct intel_pinctrl_soc_data {
size_t ncommunities;
};
const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
struct intel_pad_context;
struct intel_community_context;

60
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View File

@ -22,21 +22,26 @@
#define SPT_GPI_IS 0x100
#define SPT_GPI_IE 0x120
#define SPT_COMMUNITY(b, s, e) \
#define SPT_COMMUNITY(b, s, e, pl, gs, gn, g, n) \
{ \
.barno = (b), \
.padown_offset = SPT_PAD_OWN, \
.padcfglock_offset = SPT_LP_PADCFGLOCK, \
.padcfglock_offset = (pl), \
.hostown_offset = SPT_HOSTSW_OWN, \
.is_offset = SPT_GPI_IS, \
.ie_offset = SPT_GPI_IE, \
.gpp_size = 24, \
.gpp_num_padown_regs = 4, \
.gpp_size = (gs), \
.gpp_num_padown_regs = (gn), \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = (n), \
}
#define SPTH_GPP(r, s, e, g) \
#define SPT_LP_COMMUNITY(b, s, e) \
SPT_COMMUNITY(b, s, e, SPT_LP_PADCFGLOCK, 24, 4, NULL, 0)
#define SPT_H_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
@ -44,19 +49,8 @@
.gpio_base = (g), \
}
#define SPTH_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = SPT_PAD_OWN, \
.padcfglock_offset = SPT_H_PADCFGLOCK, \
.hostown_offset = SPT_HOSTSW_OWN, \
.is_offset = SPT_GPI_IS, \
.ie_offset = SPT_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
#define SPT_H_COMMUNITY(b, s, e, g) \
SPT_COMMUNITY(b, s, e, SPT_H_PADCFGLOCK, 0, 0, g, ARRAY_SIZE(g))
/* Sunrisepoint-LP */
static const struct pinctrl_pin_desc sptlp_pins[] = {
@ -292,9 +286,9 @@ static const struct intel_function sptlp_functions[] = {
};
static const struct intel_community sptlp_communities[] = {
SPT_COMMUNITY(0, 0, 47),
SPT_COMMUNITY(1, 48, 119),
SPT_COMMUNITY(2, 120, 151),
SPT_LP_COMMUNITY(0, 0, 47),
SPT_LP_COMMUNITY(1, 48, 119),
SPT_LP_COMMUNITY(2, 120, 151),
};
static const struct intel_pinctrl_soc_data sptlp_soc_data = {
@ -554,27 +548,27 @@ static const struct intel_function spth_functions[] = {
};
static const struct intel_padgroup spth_community0_gpps[] = {
SPTH_GPP(0, 0, 23, 0), /* GPP_A */
SPTH_GPP(1, 24, 47, 24), /* GPP_B */
SPT_H_GPP(0, 0, 23, 0), /* GPP_A */
SPT_H_GPP(1, 24, 47, 24), /* GPP_B */
};
static const struct intel_padgroup spth_community1_gpps[] = {
SPTH_GPP(0, 48, 71, 48), /* GPP_C */
SPTH_GPP(1, 72, 95, 72), /* GPP_D */
SPTH_GPP(2, 96, 108, 96), /* GPP_E */
SPTH_GPP(3, 109, 132, 120), /* GPP_F */
SPTH_GPP(4, 133, 156, 144), /* GPP_G */
SPTH_GPP(5, 157, 180, 168), /* GPP_H */
SPT_H_GPP(0, 48, 71, 48), /* GPP_C */
SPT_H_GPP(1, 72, 95, 72), /* GPP_D */
SPT_H_GPP(2, 96, 108, 96), /* GPP_E */
SPT_H_GPP(3, 109, 132, 120), /* GPP_F */
SPT_H_GPP(4, 133, 156, 144), /* GPP_G */
SPT_H_GPP(5, 157, 180, 168), /* GPP_H */
};
static const struct intel_padgroup spth_community3_gpps[] = {
SPTH_GPP(0, 181, 191, 192), /* GPP_I */
SPT_H_GPP(0, 181, 191, 192), /* GPP_I */
};
static const struct intel_community spth_communities[] = {
SPTH_COMMUNITY(0, 0, 47, spth_community0_gpps),
SPTH_COMMUNITY(1, 48, 180, spth_community1_gpps),
SPTH_COMMUNITY(2, 181, 191, spth_community3_gpps),
SPT_H_COMMUNITY(0, 0, 47, spth_community0_gpps),
SPT_H_COMMUNITY(1, 48, 180, spth_community1_gpps),
SPT_H_COMMUNITY(2, 181, 191, spth_community3_gpps),
};
static const struct intel_pinctrl_soc_data spth_soc_data = {

42
drivers/pinctrl/intel/pinctrl-tigerlake.c
View File

@ -15,11 +15,13 @@
#include "pinctrl-intel.h"
#define TGL_PAD_OWN 0x020
#define TGL_PADCFGLOCK 0x080
#define TGL_HOSTSW_OWN 0x0b0
#define TGL_GPI_IS 0x100
#define TGL_GPI_IE 0x120
#define TGL_PAD_OWN 0x020
#define TGL_LP_PADCFGLOCK 0x080
#define TGL_H_PADCFGLOCK 0x090
#define TGL_LP_HOSTSW_OWN 0x0b0
#define TGL_H_HOSTSW_OWN 0x0c0
#define TGL_GPI_IS 0x100
#define TGL_GPI_IE 0x120
#define TGL_GPP(r, s, e, g) \
{ \
@ -29,12 +31,12 @@
.gpio_base = (g), \
}
#define TGL_COMMUNITY(b, s, e, g) \
#define TGL_COMMUNITY(b, s, e, pl, ho, g) \
{ \
.barno = (b), \
.padown_offset = TGL_PAD_OWN, \
.padcfglock_offset = TGL_PADCFGLOCK, \
.hostown_offset = TGL_HOSTSW_OWN, \
.padcfglock_offset = (pl), \
.hostown_offset = (ho), \
.is_offset = TGL_GPI_IS, \
.ie_offset = TGL_GPI_IE, \
.pin_base = (s), \
@ -43,6 +45,12 @@
.ngpps = ARRAY_SIZE(g), \
}
#define TGL_LP_COMMUNITY(b, s, e, g) \
TGL_COMMUNITY(b, s, e, TGL_LP_PADCFGLOCK, TGL_LP_HOSTSW_OWN, g)
#define TGL_H_COMMUNITY(b, s, e, g) \
TGL_COMMUNITY(b, s, e, TGL_H_PADCFGLOCK, TGL_H_HOSTSW_OWN, g)
/* Tiger Lake-LP */
static const struct pinctrl_pin_desc tgllp_pins[] = {
/* GPP_B */
@ -367,10 +375,10 @@ static const struct intel_padgroup tgllp_community5_gpps[] = {
};
static const struct intel_community tgllp_communities[] = {
TGL_COMMUNITY(0, 0, 66, tgllp_community0_gpps),
TGL_COMMUNITY(1, 67, 170, tgllp_community1_gpps),
TGL_COMMUNITY(2, 171, 259, tgllp_community4_gpps),
TGL_COMMUNITY(3, 260, 276, tgllp_community5_gpps),
TGL_LP_COMMUNITY(0, 0, 66, tgllp_community0_gpps),
TGL_LP_COMMUNITY(1, 67, 170, tgllp_community1_gpps),
TGL_LP_COMMUNITY(2, 171, 259, tgllp_community4_gpps),
TGL_LP_COMMUNITY(3, 260, 276, tgllp_community5_gpps),
};
static const struct intel_pinctrl_soc_data tgllp_soc_data = {
@ -723,11 +731,11 @@ static const struct intel_padgroup tglh_community5_gpps[] = {
};
static const struct intel_community tglh_communities[] = {
TGL_COMMUNITY(0, 0, 78, tglh_community0_gpps),
TGL_COMMUNITY(1, 79, 180, tglh_community1_gpps),
TGL_COMMUNITY(2, 181, 217, tglh_community3_gpps),
TGL_COMMUNITY(3, 218, 266, tglh_community4_gpps),
TGL_COMMUNITY(4, 267, 290, tglh_community5_gpps),
TGL_H_COMMUNITY(0, 0, 78, tglh_community0_gpps),
TGL_H_COMMUNITY(1, 79, 180, tglh_community1_gpps),
TGL_H_COMMUNITY(2, 181, 217, tglh_community3_gpps),
TGL_H_COMMUNITY(3, 218, 266, tglh_community4_gpps),
TGL_H_COMMUNITY(4, 267, 290, tglh_community5_gpps),
};
static const struct intel_pinctrl_soc_data tglh_soc_data = {

14
drivers/pinctrl/mediatek/Kconfig
View File

@ -119,6 +119,13 @@ config PINCTRL_MT7622
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE
config PINCTRL_MT8167
bool "Mediatek MT8167 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK
config PINCTRL_MT8173
bool "Mediatek MT8173 pin control"
depends on OF
@ -133,6 +140,13 @@ config PINCTRL_MT8183
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT8192
bool "Mediatek MT8192 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT8516
bool "Mediatek MT8516 pin control"
depends on OF

2
drivers/pinctrl/mediatek/Makefile
View File

@ -17,7 +17,9 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o

11
drivers/pinctrl/mediatek/pinctrl-moore.c
View File

@ -589,7 +589,6 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
const struct mtk_pin_soc *soc)
{
struct pinctrl_pin_desc *pins;
struct resource *res;
struct mtk_pinctrl *hw;
int err, i;
@ -612,14 +611,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
return -ENOMEM;
for (i = 0; i < hw->soc->nbase_names; i++) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
hw->soc->base_names[i]);
if (!res) {
dev_err(&pdev->dev, "missing IO resource\n");
return -ENXIO;
}
hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
hw->soc->base_names[i]);
if (IS_ERR(hw->base[i]))
return PTR_ERR(hw->base[i]);
}

103
drivers/pinctrl/mediatek/pinctrl-mt7622.c
View File

@ -263,6 +263,68 @@ static const struct mtk_pin_desc mt7622_pins[] = {
* hardware probably has multiple combinations of these pinouts.
*/
/* ANTSEL */
static int mt7622_antsel0_pins[] = { 91, };
static int mt7622_antsel0_funcs[] = { 5, };
static int mt7622_antsel1_pins[] = { 92, };
static int mt7622_antsel1_funcs[] = { 5, };
static int mt7622_antsel2_pins[] = { 93, };
static int mt7622_antsel2_funcs[] = { 5, };
static int mt7622_antsel3_pins[] = { 94, };
static int mt7622_antsel3_funcs[] = { 5, };
static int mt7622_antsel4_pins[] = { 95, };
static int mt7622_antsel4_funcs[] = { 5, };
static int mt7622_antsel5_pins[] = { 96, };
static int mt7622_antsel5_funcs[] = { 5, };
static int mt7622_antsel6_pins[] = { 97, };
static int mt7622_antsel6_funcs[] = { 5, };
static int mt7622_antsel7_pins[] = { 98, };
static int mt7622_antsel7_funcs[] = { 5, };
static int mt7622_antsel8_pins[] = { 99, };
static int mt7622_antsel8_funcs[] = { 5, };
static int mt7622_antsel9_pins[] = { 100, };
static int mt7622_antsel9_funcs[] = { 5, };
static int mt7622_antsel10_pins[] = { 101, };
static int mt7622_antsel10_funcs[] = { 5, };
static int mt7622_antsel11_pins[] = { 102, };
static int mt7622_antsel11_funcs[] = { 5, };
static int mt7622_antsel12_pins[] = { 73, };
static int mt7622_antsel12_funcs[] = { 5, };
static int mt7622_antsel13_pins[] = { 74, };
static int mt7622_antsel13_funcs[] = { 5, };
static int mt7622_antsel14_pins[] = { 75, };
static int mt7622_antsel14_funcs[] = { 5, };
static int mt7622_antsel15_pins[] = { 76, };
static int mt7622_antsel15_funcs[] = { 5, };
static int mt7622_antsel16_pins[] = { 77, };
static int mt7622_antsel16_funcs[] = { 5, };
static int mt7622_antsel17_pins[] = { 22, };
static int mt7622_antsel17_funcs[] = { 5, };
static int mt7622_antsel18_pins[] = { 79, };
static int mt7622_antsel18_funcs[] = { 5, };
static int mt7622_antsel19_pins[] = { 80, };
static int mt7622_antsel19_funcs[] = { 5, };
static int mt7622_antsel20_pins[] = { 81, };
static int mt7622_antsel20_funcs[] = { 5, };
static int mt7622_antsel21_pins[] = { 82, };
static int mt7622_antsel21_funcs[] = { 5, };
static int mt7622_antsel22_pins[] = { 14, };
static int mt7622_antsel22_funcs[] = { 5, };
static int mt7622_antsel23_pins[] = { 15, };
static int mt7622_antsel23_funcs[] = { 5, };
static int mt7622_antsel24_pins[] = { 16, };
static int mt7622_antsel24_funcs[] = { 5, };
static int mt7622_antsel25_pins[] = { 17, };
static int mt7622_antsel25_funcs[] = { 5, };
static int mt7622_antsel26_pins[] = { 18, };
static int mt7622_antsel26_funcs[] = { 5, };
static int mt7622_antsel27_pins[] = { 19, };
static int mt7622_antsel27_funcs[] = { 5, };
static int mt7622_antsel28_pins[] = { 20, };
static int mt7622_antsel28_funcs[] = { 5, };
static int mt7622_antsel29_pins[] = { 21, };
static int mt7622_antsel29_funcs[] = { 5, };
/* EMMC */
static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
@ -543,6 +605,36 @@ static int mt7622_wled_pins[] = { 85, };
static int mt7622_wled_funcs[] = { 0, };
static const struct group_desc mt7622_groups[] = {
PINCTRL_PIN_GROUP("antsel0", mt7622_antsel0),
PINCTRL_PIN_GROUP("antsel1", mt7622_antsel1),
PINCTRL_PIN_GROUP("antsel2", mt7622_antsel2),
PINCTRL_PIN_GROUP("antsel3", mt7622_antsel3),
PINCTRL_PIN_GROUP("antsel4", mt7622_antsel4),
PINCTRL_PIN_GROUP("antsel5", mt7622_antsel5),
PINCTRL_PIN_GROUP("antsel6", mt7622_antsel6),
PINCTRL_PIN_GROUP("antsel7", mt7622_antsel7),
PINCTRL_PIN_GROUP("antsel8", mt7622_antsel8),
PINCTRL_PIN_GROUP("antsel9", mt7622_antsel9),
PINCTRL_PIN_GROUP("antsel10", mt7622_antsel10),
PINCTRL_PIN_GROUP("antsel11", mt7622_antsel11),
PINCTRL_PIN_GROUP("antsel12", mt7622_antsel12),
PINCTRL_PIN_GROUP("antsel13", mt7622_antsel13),
PINCTRL_PIN_GROUP("antsel14", mt7622_antsel14),
PINCTRL_PIN_GROUP("antsel15", mt7622_antsel15),
PINCTRL_PIN_GROUP("antsel16", mt7622_antsel16),
PINCTRL_PIN_GROUP("antsel17", mt7622_antsel17),
PINCTRL_PIN_GROUP("antsel18", mt7622_antsel18),
PINCTRL_PIN_GROUP("antsel19", mt7622_antsel19),
PINCTRL_PIN_GROUP("antsel20", mt7622_antsel20),
PINCTRL_PIN_GROUP("antsel21", mt7622_antsel21),
PINCTRL_PIN_GROUP("antsel22", mt7622_antsel22),
PINCTRL_PIN_GROUP("antsel23", mt7622_antsel23),
PINCTRL_PIN_GROUP("antsel24", mt7622_antsel24),
PINCTRL_PIN_GROUP("antsel25", mt7622_antsel25),
PINCTRL_PIN_GROUP("antsel26", mt7622_antsel26),
PINCTRL_PIN_GROUP("antsel27", mt7622_antsel27),
PINCTRL_PIN_GROUP("antsel28", mt7622_antsel28),
PINCTRL_PIN_GROUP("antsel29", mt7622_antsel29),
PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
@ -663,6 +755,16 @@ static const struct group_desc mt7622_groups[] = {
/* Joint those groups owning the same capability in user point of view which
* allows that people tend to use through the device tree.
*/
static const char *mt7622_antsel_groups[] = { "antsel0", "antsel1", "antsel2",
"antsel3", "antsel4", "antsel5",
"antsel6", "antsel7", "antsel8",
"antsel9", "antsel10", "antsel11",
"antsel12", "antsel13", "antsel14",
"antsel15", "antsel16", "antsel17",
"antsel18", "antsel19", "antsel20",
"antsel21", "antsel22", "antsel23",
"antsel24", "antsel25", "antsel26",
"antsel27", "antsel28", "antsel29",};
static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
"esw_p2_p3_p4", "mdc_mdio",
@ -732,6 +834,7 @@ static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx",
static const char *mt7622_wdt_groups[] = { "watchdog", };
static const struct function_desc mt7622_functions[] = {
{"antsel", mt7622_antsel_groups, ARRAY_SIZE(mt7622_antsel_groups)},
{"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
{"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
{"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},

362
drivers/pinctrl/mediatek/pinctrl-mt8167.c Normal file
View File

@ -0,0 +1,362 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 MediaTek Inc.
* Author: Min.Guo <min.guo@mediatek.com>
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt8167.h"
static const struct mtk_drv_group_desc mt8167_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt8167_pin_drv[] = {
MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
};
static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
};
static int mt8167_spec_pull_set(struct regmap *regmap, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
{
return mtk_pctrl_spec_pull_set_samereg(regmap, mt8167_spec_pupd,
ARRAY_SIZE(mt8167_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
};
static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
};
static int mt8167_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg)
{
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_ies_set,
ARRAY_SIZE(mt8167_ies_set), pin, align, value);
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_smt_set,
ARRAY_SIZE(mt8167_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
.pins = mtk_pins_mt8167,
.npins = ARRAY_SIZE(mtk_pins_mt8167),
.grp_desc = mt8167_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt8167_drv_grp),
.pin_drv_grp = mt8167_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv),
.spec_pull_set = mt8167_spec_pull_set,
.spec_ies_smt_set = mt8167_ies_smt_set,
.dir_offset = 0x0000,
.pullen_offset = 0x0500,
.pullsel_offset = 0x0600,
.dout_offset = 0x0100,
.din_offset = 0x0200,
.pinmux_offset = 0x0300,
.type1_start = 125,
.type1_end = 125,
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.eint_hw = {
.port_mask = 7,
.ports = 6,
.ap_num = 169,
.db_cnt = 64,
},
};
static int mt8167_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt8167_pinctrl_data, NULL);
}
static const struct of_device_id mt8167_pctrl_match[] = {
{
.compatible = "mediatek,mt8167-pinctrl",
},
{}
};
MODULE_DEVICE_TABLE(of, mt8167_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8167_pinctrl_probe,
.driver = {
.name = "mediatek-mt8167-pinctrl",
.of_match_table = mt8167_pctrl_match,
.pm = &mtk_eint_pm_ops,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);

1409
drivers/pinctrl/mediatek/pinctrl-mt8192.c Normal file
View File

File diff suppressed because it is too large Load Diff

31
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
View File

@ -358,7 +358,7 @@ static const struct mtk_eint_xt mtk_eint_xt = {
int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *res;
int ret;
if (!IS_ENABLED(CONFIG_EINT_MTK))
return 0;
@ -370,22 +370,22 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
if (!hw->eint)
return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
if (!res) {
dev_err(&pdev->dev, "Unable to get eint resource\n");
return -ENODEV;
hw->eint->base = devm_platform_ioremap_resource_byname(pdev, "eint");
if (IS_ERR(hw->eint->base)) {
ret = PTR_ERR(hw->eint->base);
goto err_free_eint;
}
hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(hw->eint->base))
return PTR_ERR(hw->eint->base);
hw->eint->irq = irq_of_parse_and_map(np, 0);
if (!hw->eint->irq)
return -EINVAL;
if (!hw->eint->irq) {
ret = -EINVAL;
goto err_free_eint;
}
if (!hw->soc->eint_hw)
return -ENODEV;
if (!hw->soc->eint_hw) {
ret = -ENODEV;
goto err_free_eint;
}
hw->eint->dev = &pdev->dev;
hw->eint->hw = hw->soc->eint_hw;
@ -393,6 +393,11 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
hw->eint->gpio_xlate = &mtk_eint_xt;
return mtk_eint_do_init(hw->eint);
err_free_eint:
devm_kfree(hw->dev, hw->eint);
hw->eint = NULL;
return ret;
}
EXPORT_SYMBOL_GPL(mtk_build_eint);

1248
drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h Normal file
View File

File diff suppressed because it is too large Load Diff

2275
drivers/pinctrl/mediatek/pinctrl-mtk-mt8192.h Normal file
View File

File diff suppressed because it is too large Load Diff

11
drivers/pinctrl/mediatek/pinctrl-paris.c
View File

@ -940,7 +940,6 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev,
{
struct pinctrl_pin_desc *pins;
struct mtk_pinctrl *hw;
struct resource *res;
int err, i;
hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
@ -963,14 +962,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev,
return -ENOMEM;
for (i = 0; i < hw->soc->nbase_names; i++) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
hw->soc->base_names[i]);
if (!res) {
dev_err(&pdev->dev, "missing IO resource\n");
return -ENXIO;
}
hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
hw->soc->base_names[i]);
if (IS_ERR(hw->base[i]))
return PTR_ERR(hw->base[i]);
}

2
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
View File

@ -197,7 +197,7 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),

16
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View File

@ -931,11 +931,6 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
[NMK_GPIO_ALT_C+3] = "altC3",
[NMK_GPIO_ALT_C+4] = "altC4",
};
const char *pulls[] = {
"none ",
"pull down",
"pull up ",
};
clk_enable(nmk_chip->clk);
is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
@ -946,7 +941,7 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
if (is_out) {
seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
gpio,
label ?: "(none)",
data_out ? "hi" : "lo",
@ -954,11 +949,12 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
} else {
int irq = chip->to_irq(chip, offset);
struct irq_desc *desc = irq_to_desc(irq);
int pullidx = 0;
const int pullidx = pull ? 1 : 0;
int val;
if (pull)
pullidx = data_out ? 2 : 1;
static const char * const pulls[] = {
"none ",
"pull enabled",
};
seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
gpio,

6
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View File

@ -1601,7 +1601,7 @@ static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev,
kfree(map);
}
static struct pinctrl_ops npcm7xx_pinctrl_ops = {
static const struct pinctrl_ops npcm7xx_pinctrl_ops = {
.get_groups_count = npcm7xx_get_groups_count,
.get_group_name = npcm7xx_get_group_name,
.get_group_pins = npcm7xx_get_group_pins,
@ -1701,7 +1701,7 @@ static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
return 0;
}
static struct pinmux_ops npcm7xx_pinmux_ops = {
static const struct pinmux_ops npcm7xx_pinmux_ops = {
.get_functions_count = npcm7xx_get_functions_count,
.get_function_name = npcm7xx_get_function_name,
.get_function_groups = npcm7xx_get_function_groups,
@ -1842,7 +1842,7 @@ static int npcm7xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
return 0;
}
static struct pinconf_ops npcm7xx_pinconf_ops = {
static const struct pinconf_ops npcm7xx_pinconf_ops = {
.is_generic = true,
.pin_config_get = npcm7xx_config_get,
.pin_config_set = npcm7xx_config_set,

69
drivers/pinctrl/pinctrl-amd.h
View File

@ -123,13 +123,31 @@ static const struct pinctrl_pin_desc kerncz_pins[] = {
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "GPIO_34"),
PINCTRL_PIN(35, "GPIO_35"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(43, "GPIO_42"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GPIO_42"),
PINCTRL_PIN(43, "GPIO_43"),
PINCTRL_PIN(44, "GPIO_44"),
PINCTRL_PIN(45, "GPIO_45"),
PINCTRL_PIN(46, "GPIO_46"),
PINCTRL_PIN(47, "GPIO_47"),
PINCTRL_PIN(48, "GPIO_48"),
@ -150,14 +168,23 @@ static const struct pinctrl_pin_desc kerncz_pins[] = {
PINCTRL_PIN(64, "GPIO_64"),
PINCTRL_PIN(65, "GPIO_65"),
PINCTRL_PIN(66, "GPIO_66"),
PINCTRL_PIN(67, "GPIO_67"),
PINCTRL_PIN(68, "GPIO_68"),
PINCTRL_PIN(69, "GPIO_69"),
PINCTRL_PIN(70, "GPIO_70"),
PINCTRL_PIN(71, "GPIO_71"),
PINCTRL_PIN(72, "GPIO_72"),
PINCTRL_PIN(73, "GPIO_73"),
PINCTRL_PIN(74, "GPIO_74"),
PINCTRL_PIN(75, "GPIO_75"),
PINCTRL_PIN(76, "GPIO_76"),
PINCTRL_PIN(77, "GPIO_77"),
PINCTRL_PIN(78, "GPIO_78"),
PINCTRL_PIN(79, "GPIO_79"),
PINCTRL_PIN(80, "GPIO_80"),
PINCTRL_PIN(81, "GPIO_81"),
PINCTRL_PIN(82, "GPIO_82"),
PINCTRL_PIN(83, "GPIO_83"),
PINCTRL_PIN(84, "GPIO_84"),
PINCTRL_PIN(85, "GPIO_85"),
PINCTRL_PIN(86, "GPIO_86"),
@ -168,6 +195,7 @@ static const struct pinctrl_pin_desc kerncz_pins[] = {
PINCTRL_PIN(91, "GPIO_91"),
PINCTRL_PIN(92, "GPIO_92"),
PINCTRL_PIN(93, "GPIO_93"),
PINCTRL_PIN(94, "GPIO_94"),
PINCTRL_PIN(95, "GPIO_95"),
PINCTRL_PIN(96, "GPIO_96"),
PINCTRL_PIN(97, "GPIO_97"),
@ -176,6 +204,16 @@ static const struct pinctrl_pin_desc kerncz_pins[] = {
PINCTRL_PIN(100, "GPIO_100"),
PINCTRL_PIN(101, "GPIO_101"),
PINCTRL_PIN(102, "GPIO_102"),
PINCTRL_PIN(103, "GPIO_103"),
PINCTRL_PIN(104, "GPIO_104"),
PINCTRL_PIN(105, "GPIO_105"),
PINCTRL_PIN(106, "GPIO_106"),
PINCTRL_PIN(107, "GPIO_107"),
PINCTRL_PIN(108, "GPIO_108"),
PINCTRL_PIN(109, "GPIO_109"),
PINCTRL_PIN(110, "GPIO_110"),
PINCTRL_PIN(111, "GPIO_111"),
PINCTRL_PIN(112, "GPIO_112"),
PINCTRL_PIN(113, "GPIO_113"),
PINCTRL_PIN(114, "GPIO_114"),
PINCTRL_PIN(115, "GPIO_115"),
@ -186,12 +224,18 @@ static const struct pinctrl_pin_desc kerncz_pins[] = {
PINCTRL_PIN(120, "GPIO_120"),
PINCTRL_PIN(121, "GPIO_121"),
PINCTRL_PIN(122, "GPIO_122"),
PINCTRL_PIN(123, "GPIO_123"),
PINCTRL_PIN(124, "GPIO_124"),
PINCTRL_PIN(125, "GPIO_125"),
PINCTRL_PIN(126, "GPIO_126"),
PINCTRL_PIN(127, "GPIO_127"),
PINCTRL_PIN(128, "GPIO_128"),
PINCTRL_PIN(129, "GPIO_129"),
PINCTRL_PIN(130, "GPIO_130"),
PINCTRL_PIN(131, "GPIO_131"),
PINCTRL_PIN(132, "GPIO_132"),
PINCTRL_PIN(133, "GPIO_133"),
PINCTRL_PIN(134, "GPIO_134"),
PINCTRL_PIN(135, "GPIO_135"),
PINCTRL_PIN(136, "GPIO_136"),
PINCTRL_PIN(137, "GPIO_137"),
@ -206,6 +250,23 @@ static const struct pinctrl_pin_desc kerncz_pins[] = {
PINCTRL_PIN(146, "GPIO_146"),
PINCTRL_PIN(147, "GPIO_147"),
PINCTRL_PIN(148, "GPIO_148"),
PINCTRL_PIN(149, "GPIO_149"),
PINCTRL_PIN(150, "GPIO_150"),
PINCTRL_PIN(151, "GPIO_151"),
PINCTRL_PIN(152, "GPIO_152"),
PINCTRL_PIN(153, "GPIO_153"),
PINCTRL_PIN(154, "GPIO_154"),
PINCTRL_PIN(155, "GPIO_155"),
PINCTRL_PIN(156, "GPIO_156"),
PINCTRL_PIN(157, "GPIO_157"),
PINCTRL_PIN(158, "GPIO_158"),
PINCTRL_PIN(159, "GPIO_159"),
PINCTRL_PIN(160, "GPIO_160"),
PINCTRL_PIN(161, "GPIO_161"),
PINCTRL_PIN(162, "GPIO_162"),
PINCTRL_PIN(163, "GPIO_163"),
PINCTRL_PIN(164, "GPIO_164"),
PINCTRL_PIN(165, "GPIO_165"),
PINCTRL_PIN(166, "GPIO_166"),
PINCTRL_PIN(167, "GPIO_167"),
PINCTRL_PIN(168, "GPIO_168"),
@ -218,6 +279,12 @@ static const struct pinctrl_pin_desc kerncz_pins[] = {
PINCTRL_PIN(175, "GPIO_175"),
PINCTRL_PIN(176, "GPIO_176"),
PINCTRL_PIN(177, "GPIO_177"),
PINCTRL_PIN(178, "GPIO_178"),
PINCTRL_PIN(179, "GPIO_179"),
PINCTRL_PIN(180, "GPIO_180"),
PINCTRL_PIN(181, "GPIO_181"),
PINCTRL_PIN(182, "GPIO_182"),
PINCTRL_PIN(183, "GPIO_183"),
};
static const unsigned i2c0_pins[] = {145, 146};

7
drivers/pinctrl/pinctrl-at91-pio4.c
View File

@ -983,10 +983,17 @@ static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
.nbanks = 4,
};
static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
.nbanks = 5,
};
static const struct of_device_id atmel_pctrl_of_match[] = {
{
.compatible = "atmel,sama5d2-pinctrl",
.data = &atmel_sama5d2_pioctrl_data,
}, {
.compatible = "microchip,sama7g5-pinctrl",
.data = &microchip_sama7g5_pioctrl_data,
}, {
/* sentinel */
}

349
drivers/pinctrl/pinctrl-ingenic.c
View File

@ -633,6 +633,46 @@ static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
static int jz4770_ssi0_dt_d_pins[] = { 0x55, };
static int jz4770_ssi0_dt_e_pins[] = { 0x71, };
static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
static int jz4770_ssi0_dr_d_pins[] = { 0x54, };
static int jz4770_ssi0_dr_e_pins[] = { 0x6e, };
static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
static int jz4770_ssi0_clk_d_pins[] = { 0x58, };
static int jz4770_ssi0_clk_e_pins[] = { 0x6f, };
static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
static int jz4770_ssi0_gpc_d_pins[] = { 0x56, };
static int jz4770_ssi0_gpc_e_pins[] = { 0x73, };
static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
static int jz4770_ssi0_ce0_d_pins[] = { 0x59, };
static int jz4770_ssi0_ce0_e_pins[] = { 0x70, };
static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
static int jz4770_ssi0_ce1_d_pins[] = { 0x57, };
static int jz4770_ssi0_ce1_e_pins[] = { 0x72, };
static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
static int jz4770_ssi1_dt_d_pins[] = { 0x55, };
static int jz4770_ssi1_dt_e_pins[] = { 0x71, };
static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
static int jz4770_ssi1_dr_d_pins[] = { 0x54, };
static int jz4770_ssi1_dr_e_pins[] = { 0x6e, };
static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
static int jz4770_ssi1_clk_d_pins[] = { 0x58, };
static int jz4770_ssi1_clk_e_pins[] = { 0x6f, };
static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
static int jz4770_ssi1_gpc_d_pins[] = { 0x56, };
static int jz4770_ssi1_gpc_e_pins[] = { 0x73, };
static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
static int jz4770_ssi1_ce0_d_pins[] = { 0x59, };
static int jz4770_ssi1_ce0_e_pins[] = { 0x70, };
static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
static int jz4770_ssi1_ce1_d_pins[] = { 0x57, };
static int jz4770_ssi1_ce1_e_pins[] = { 0x72, };
static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
@ -703,6 +743,46 @@ static int jz4770_uart2_data_funcs[] = { 0, 0, };
static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
static int jz4770_uart3_data_funcs[] = { 0, 1, };
static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
static int jz4770_ssi0_dt_a_funcs[] = { 2, };
static int jz4770_ssi0_dt_b_funcs[] = { 1, };
static int jz4770_ssi0_dt_d_funcs[] = { 1, };
static int jz4770_ssi0_dt_e_funcs[] = { 0, };
static int jz4770_ssi0_dr_a_funcs[] = { 1, };
static int jz4770_ssi0_dr_b_funcs[] = { 1, };
static int jz4770_ssi0_dr_d_funcs[] = { 1, };
static int jz4770_ssi0_dr_e_funcs[] = { 0, };
static int jz4770_ssi0_clk_a_funcs[] = { 2, };
static int jz4770_ssi0_clk_b_funcs[] = { 1, };
static int jz4770_ssi0_clk_d_funcs[] = { 1, };
static int jz4770_ssi0_clk_e_funcs[] = { 0, };
static int jz4770_ssi0_gpc_b_funcs[] = { 1, };
static int jz4770_ssi0_gpc_d_funcs[] = { 1, };
static int jz4770_ssi0_gpc_e_funcs[] = { 0, };
static int jz4770_ssi0_ce0_a_funcs[] = { 2, };
static int jz4770_ssi0_ce0_b_funcs[] = { 1, };
static int jz4770_ssi0_ce0_d_funcs[] = { 1, };
static int jz4770_ssi0_ce0_e_funcs[] = { 0, };
static int jz4770_ssi0_ce1_b_funcs[] = { 1, };
static int jz4770_ssi0_ce1_d_funcs[] = { 1, };
static int jz4770_ssi0_ce1_e_funcs[] = { 0, };
static int jz4770_ssi1_dt_b_funcs[] = { 2, };
static int jz4770_ssi1_dt_d_funcs[] = { 2, };
static int jz4770_ssi1_dt_e_funcs[] = { 1, };
static int jz4770_ssi1_dr_b_funcs[] = { 2, };
static int jz4770_ssi1_dr_d_funcs[] = { 2, };
static int jz4770_ssi1_dr_e_funcs[] = { 1, };
static int jz4770_ssi1_clk_b_funcs[] = { 2, };
static int jz4770_ssi1_clk_d_funcs[] = { 2, };
static int jz4770_ssi1_clk_e_funcs[] = { 1, };
static int jz4770_ssi1_gpc_b_funcs[] = { 2, };
static int jz4770_ssi1_gpc_d_funcs[] = { 2, };
static int jz4770_ssi1_gpc_e_funcs[] = { 1, };
static int jz4770_ssi1_ce0_b_funcs[] = { 2, };
static int jz4770_ssi1_ce0_d_funcs[] = { 2, };
static int jz4770_ssi1_ce0_e_funcs[] = { 1, };
static int jz4770_ssi1_ce1_b_funcs[] = { 2, };
static int jz4770_ssi1_ce1_d_funcs[] = { 2, };
static int jz4770_ssi1_ce1_e_funcs[] = { 1, };
static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
@ -763,6 +843,46 @@ static const struct group_desc jz4770_groups[] = {
INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a),
INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b),
INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d),
INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e),
INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a),
INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b),
INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d),
INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e),
INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a),
INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b),
INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d),
INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e),
INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b),
INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d),
INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e),
INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a),
INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b),
INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d),
INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b),
INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d),
INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e),
INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b),
INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d),
INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e),
INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b),
INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d),
INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e),
INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b),
INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d),
INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e),
INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b),
INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d),
INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e),
INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b),
INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d),
INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b),
INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d),
INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e),
INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
@ -815,6 +935,22 @@ static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
static const char *jz4770_ssi0_groups[] = {
"ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
"ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
"ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
"ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
};
static const char *jz4770_ssi1_groups[] = {
"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
};
static const char *jz4770_mmc0_groups[] = {
"mmc0-1bit-a", "mmc0-4bit-a",
"mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
@ -858,6 +994,8 @@ static const struct function_desc jz4770_functions[] = {
{ "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
{ "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
{ "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), },
{ "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), },
{ "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
{ "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
{ "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
@ -897,22 +1035,106 @@ static const struct ingenic_chip_info jz4770_chip_info = {
.pull_downs = jz4770_pull_downs,
};
static const u32 jz4780_pull_ups[6] = {
0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,
};
static const u32 jz4780_pull_downs[6] = {
0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
};
static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };
static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };
static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };
static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };
static int jz4780_ssi0_dt_d_pins[] = { 0x59, };
static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };
static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };
static int jz4780_ssi0_dr_b_pins[] = { 0x34, };
static int jz4780_ssi0_dr_d_pins[] = { 0x54, };
static int jz4780_ssi0_clk_a_pins[] = { 0x12, };
static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };
static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };
static int jz4780_ssi0_clk_d_pins[] = { 0x58, };
static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };
static int jz4780_ssi0_gpc_d_pins[] = { 0x56, };
static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };
static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };
static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };
static int jz4780_ssi0_ce0_d_pins[] = { 0x57, };
static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };
static int jz4780_ssi0_ce1_d_pins[] = { 0x55, };
static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };
static int jz4780_ssi1_dt_d_pins[] = { 0x59, };
static int jz4780_ssi1_dr_b_pins[] = { 0x34, };
static int jz4780_ssi1_dr_d_pins[] = { 0x54, };
static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };
static int jz4780_ssi1_clk_d_pins[] = { 0x58, };
static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };
static int jz4780_ssi1_gpc_d_pins[] = { 0x56, };
static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };
static int jz4780_ssi1_ce0_d_pins[] = { 0x57, };
static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };
static int jz4780_ssi1_ce1_d_pins[] = { 0x55, };
static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
static int jz4780_i2s_data_tx_pins[] = { 0x87, };
static int jz4780_i2s_data_rx_pins[] = { 0x86, };
static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };
static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
static int jz4780_i2s_sysclk_pins[] = { 0x85, };
static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
static int jz4780_uart2_data_funcs[] = { 1, 1, };
static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
static int jz4780_uart4_data_funcs[] = { 2, 2, };
static int jz4780_ssi0_dt_a_19_funcs[] = { 2, };
static int jz4780_ssi0_dt_a_21_funcs[] = { 2, };
static int jz4780_ssi0_dt_a_28_funcs[] = { 2, };
static int jz4780_ssi0_dt_b_funcs[] = { 1, };
static int jz4780_ssi0_dt_d_funcs[] = { 1, };
static int jz4780_ssi0_dr_a_20_funcs[] = { 2, };
static int jz4780_ssi0_dr_a_27_funcs[] = { 2, };
static int jz4780_ssi0_dr_b_funcs[] = { 1, };
static int jz4780_ssi0_dr_d_funcs[] = { 1, };
static int jz4780_ssi0_clk_a_funcs[] = { 2, };
static int jz4780_ssi0_clk_b_5_funcs[] = { 1, };
static int jz4780_ssi0_clk_b_28_funcs[] = { 1, };
static int jz4780_ssi0_clk_d_funcs[] = { 1, };
static int jz4780_ssi0_gpc_b_funcs[] = { 1, };
static int jz4780_ssi0_gpc_d_funcs[] = { 1, };
static int jz4780_ssi0_ce0_a_23_funcs[] = { 2, };
static int jz4780_ssi0_ce0_a_25_funcs[] = { 2, };
static int jz4780_ssi0_ce0_b_funcs[] = { 1, };
static int jz4780_ssi0_ce0_d_funcs[] = { 1, };
static int jz4780_ssi0_ce1_b_funcs[] = { 1, };
static int jz4780_ssi0_ce1_d_funcs[] = { 1, };
static int jz4780_ssi1_dt_b_funcs[] = { 2, };
static int jz4780_ssi1_dt_d_funcs[] = { 2, };
static int jz4780_ssi1_dr_b_funcs[] = { 2, };
static int jz4780_ssi1_dr_d_funcs[] = { 2, };
static int jz4780_ssi1_clk_b_funcs[] = { 2, };
static int jz4780_ssi1_clk_d_funcs[] = { 2, };
static int jz4780_ssi1_gpc_b_funcs[] = { 2, };
static int jz4780_ssi1_gpc_d_funcs[] = { 2, };
static int jz4780_ssi1_ce0_b_funcs[] = { 2, };
static int jz4780_ssi1_ce0_d_funcs[] = { 2, };
static int jz4780_ssi1_ce1_b_funcs[] = { 2, };
static int jz4780_ssi1_ce1_d_funcs[] = { 2, };
static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
static int jz4780_i2c3_funcs[] = { 1, 1, };
static int jz4780_i2c4_e_funcs[] = { 1, 1, };
static int jz4780_i2c4_f_funcs[] = { 1, 1, };
static int jz4780_i2s_data_tx_funcs[] = { 0, };
static int jz4780_i2s_data_rx_funcs[] = { 0, };
static int jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
static int jz4780_i2s_clk_rx_funcs[] = { 1, 1, };
static int jz4780_i2s_sysclk_funcs[] = { 2, };
static int jz4780_hdmi_ddc_funcs[] = { 0, 0, };
static const struct group_desc jz4780_groups[] = {
@ -925,6 +1147,51 @@ static const struct group_desc jz4780_groups[] = {
INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19),
INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21),
INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28),
INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b),
INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d),
INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e),
INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20),
INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27),
INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b),
INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d),
INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e),
INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a),
INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5),
INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28),
INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d),
INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e),
INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b),
INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d),
INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e),
INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23),
INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25),
INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b),
INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d),
INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b),
INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d),
INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e),
INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b),
INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d),
INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e),
INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b),
INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d),
INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e),
INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b),
INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d),
INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e),
INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b),
INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d),
INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e),
INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b),
INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d),
INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b),
INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d),
INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e),
INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
@ -956,6 +1223,11 @@ static const struct group_desc jz4780_groups[] = {
INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx),
INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx),
INGENIC_PIN_GROUP("i2s-clk-txrx", jz4780_i2s_clk_txrx),
INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx),
INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk),
INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc),
INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
@ -972,6 +1244,22 @@ static const struct group_desc jz4780_groups[] = {
static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
static const char *jz4780_uart4_groups[] = { "uart4-data", };
static const char *jz4780_ssi0_groups[] = {
"ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
"ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
"ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
"ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
"ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
"ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
};
static const char *jz4780_ssi1_groups[] = {
"ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
"ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
"ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
"ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
"ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
"ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
};
static const char *jz4780_mmc0_groups[] = {
"mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
"mmc0-1bit-e", "mmc0-4bit-e",
@ -988,6 +1276,9 @@ static const char *jz4780_nemc_groups[] = {
};
static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
static const char *jz4780_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
};
static const char *jz4780_cim_groups[] = { "cim-data", };
static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
@ -997,6 +1288,8 @@ static const struct function_desc jz4780_functions[] = {
{ "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
{ "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
{ "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
{ "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), },
{ "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), },
{ "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
{ "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
{ "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
@ -1012,6 +1305,7 @@ static const struct function_desc jz4780_functions[] = {
{ "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
{ "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
{ "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
{ "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), },
{ "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
{ "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
{ "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
@ -1034,8 +1328,8 @@ static const struct ingenic_chip_info jz4780_chip_info = {
.num_groups = ARRAY_SIZE(jz4780_groups),
.functions = jz4780_functions,
.num_functions = ARRAY_SIZE(jz4780_functions),
.pull_ups = jz4770_pull_ups,
.pull_downs = jz4770_pull_downs,
.pull_ups = jz4780_pull_ups,
.pull_downs = jz4780_pull_downs,
};
static const u32 x1000_pull_ups[4] = {
@ -1093,6 +1387,10 @@ static int x1000_i2c0_pins[] = { 0x38, 0x37, };
static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
static int x1000_i2c2_pins[] = { 0x61, 0x60, };
static int x1000_i2s_data_tx_pins[] = { 0x24, };
static int x1000_i2s_data_rx_pins[] = { 0x23, };
static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
static int x1000_i2s_sysclk_pins[] = { 0x20, };
static int x1000_cim_pins[] = {
0x08, 0x09, 0x0a, 0x0b,
0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
@ -1155,6 +1453,10 @@ static int x1000_i2c0_funcs[] = { 0, 0, };
static int x1000_i2c1_a_funcs[] = { 2, 2, };
static int x1000_i2c1_c_funcs[] = { 0, 0, };
static int x1000_i2c2_funcs[] = { 1, 1, };
static int x1000_i2s_data_tx_funcs[] = { 1, };
static int x1000_i2s_data_rx_funcs[] = { 1, };
static int x1000_i2s_clk_txrx_funcs[] = { 1, 1, };
static int x1000_i2s_sysclk_funcs[] = { 1, };
static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
static int x1000_lcd_8bit_funcs[] = {
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
@ -1208,6 +1510,10 @@ static const struct group_desc x1000_groups[] = {
INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2),
INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx),
INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx),
INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx),
INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk),
INGENIC_PIN_GROUP("cim-data", x1000_cim),
INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit),
INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit),
@ -1249,6 +1555,9 @@ static const char *x1000_cs2_groups[] = { "emc-cs2", };
static const char *x1000_i2c0_groups[] = { "i2c0-data", };
static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
static const char *x1000_i2c2_groups[] = { "i2c2-data", };
static const char *x1000_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
};
static const char *x1000_cim_groups[] = { "cim-data", };
static const char *x1000_lcd_groups[] = {
"lcd-8bit", "lcd-16bit", "lcd-no-pins",
@ -1274,6 +1583,7 @@ static const struct function_desc x1000_functions[] = {
{ "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
{ "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
{ "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
{ "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), },
{ "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
{ "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
{ "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
@ -1309,6 +1619,10 @@ static int x1500_i2c0_pins[] = { 0x38, 0x37, };
static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
static int x1500_i2c2_pins[] = { 0x61, 0x60, };
static int x1500_i2s_data_tx_pins[] = { 0x24, };
static int x1500_i2s_data_rx_pins[] = { 0x23, };
static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
static int x1500_i2s_sysclk_pins[] = { 0x20, };
static int x1500_cim_pins[] = {
0x08, 0x09, 0x0a, 0x0b,
0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
@ -1332,6 +1646,10 @@ static int x1500_i2c0_funcs[] = { 0, 0, };
static int x1500_i2c1_a_funcs[] = { 2, 2, };
static int x1500_i2c1_c_funcs[] = { 0, 0, };
static int x1500_i2c2_funcs[] = { 1, 1, };
static int x1500_i2s_data_tx_funcs[] = { 1, };
static int x1500_i2s_data_rx_funcs[] = { 1, };
static int x1500_i2s_clk_txrx_funcs[] = { 1, 1, };
static int x1500_i2s_sysclk_funcs[] = { 1, };
static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
static int x1500_pwm_pwm0_funcs[] = { 0, };
static int x1500_pwm_pwm1_funcs[] = { 1, };
@ -1354,6 +1672,10 @@ static const struct group_desc x1500_groups[] = {
INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),
INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),
INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2),
INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx),
INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx),
INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx),
INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk),
INGENIC_PIN_GROUP("cim-data", x1500_cim),
{ "lcd-no-pins", },
INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0),
@ -1372,6 +1694,9 @@ static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
static const char *x1500_i2c0_groups[] = { "i2c0-data", };
static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
static const char *x1500_i2c2_groups[] = { "i2c2-data", };
static const char *x1500_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
};
static const char *x1500_cim_groups[] = { "cim-data", };
static const char *x1500_lcd_groups[] = { "lcd-no-pins", };
static const char *x1500_pwm0_groups[] = { "pwm0", };
@ -1389,6 +1714,7 @@ static const struct function_desc x1500_functions[] = {
{ "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
{ "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
{ "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
{ "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), },
{ "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
{ "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), },
{ "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
@ -1447,6 +1773,11 @@ static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
static int x1830_i2s_data_tx_pins[] = { 0x53, };
static int x1830_i2s_data_rx_pins[] = { 0x54, };
static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
static int x1830_i2s_sysclk_pins[] = { 0x57, };
static int x1830_lcd_rgb_18bit_pins[] = {
0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f,
@ -1509,6 +1840,11 @@ static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, };
static int x1830_i2c0_funcs[] = { 1, 1, };
static int x1830_i2c1_funcs[] = { 0, 0, };
static int x1830_i2c2_funcs[] = { 1, 1, };
static int x1830_i2s_data_tx_funcs[] = { 0, };
static int x1830_i2s_data_rx_funcs[] = { 0, };
static int x1830_i2s_clk_txrx_funcs[] = { 0, 0, };
static int x1830_i2s_clk_rx_funcs[] = { 0, 0, };
static int x1830_i2s_sysclk_funcs[] = { 0, };
static int x1830_lcd_rgb_18bit_funcs[] = {
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
@ -1567,6 +1903,11 @@ static const struct group_desc x1830_groups[] = {
INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0),
INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1),
INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2),
INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx),
INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx),
INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx),
INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx),
INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk),
INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit),
INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit),
INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit),
@ -1609,6 +1950,9 @@ static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
static const char *x1830_i2c0_groups[] = { "i2c0-data", };
static const char *x1830_i2c1_groups[] = { "i2c1-data", };
static const char *x1830_i2c2_groups[] = { "i2c2-data", };
static const char *x1830_i2s_groups[] = {
"i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
};
static const char *x1830_lcd_groups[] = {
"lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins",
};
@ -1633,6 +1977,7 @@ static const struct function_desc x1830_functions[] = {
{ "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
{ "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
{ "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
{ "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), },
{ "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
{ "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
{ "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },

49
drivers/pinctrl/pinctrl-mcp23s08.c
View File

@ -87,7 +87,7 @@ const struct regmap_config mcp23x08_regmap = {
};
EXPORT_SYMBOL_GPL(mcp23x08_regmap);
static const struct reg_default mcp23x16_defaults[] = {
static const struct reg_default mcp23x17_defaults[] = {
{.reg = MCP_IODIR << 1, .def = 0xffff},
{.reg = MCP_IPOL << 1, .def = 0x0000},
{.reg = MCP_GPINTEN << 1, .def = 0x0000},
@ -98,23 +98,23 @@ static const struct reg_default mcp23x16_defaults[] = {
{.reg = MCP_OLAT << 1, .def = 0x0000},
};
static const struct regmap_range mcp23x16_volatile_range = {
static const struct regmap_range mcp23x17_volatile_range = {
.range_min = MCP_INTF << 1,
.range_max = MCP_GPIO << 1,
};
static const struct regmap_access_table mcp23x16_volatile_table = {
.yes_ranges = &mcp23x16_volatile_range,
static const struct regmap_access_table mcp23x17_volatile_table = {
.yes_ranges = &mcp23x17_volatile_range,
.n_yes_ranges = 1,
};
static const struct regmap_range mcp23x16_precious_range = {
.range_min = MCP_GPIO << 1,
static const struct regmap_range mcp23x17_precious_range = {
.range_min = MCP_INTCAP << 1,
.range_max = MCP_GPIO << 1,
};
static const struct regmap_access_table mcp23x16_precious_table = {
.yes_ranges = &mcp23x16_precious_range,
static const struct regmap_access_table mcp23x17_precious_table = {
.yes_ranges = &mcp23x17_precious_range,
.n_yes_ranges = 1,
};
@ -124,10 +124,10 @@ const struct regmap_config mcp23x17_regmap = {
.reg_stride = 2,
.max_register = MCP_OLAT << 1,
.volatile_table = &mcp23x16_volatile_table,
.precious_table = &mcp23x16_precious_table,
.reg_defaults = mcp23x16_defaults,
.num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults),
.volatile_table = &mcp23x17_volatile_table,
.precious_table = &mcp23x17_precious_table,
.reg_defaults = mcp23x17_defaults,
.num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
.cache_type = REGCACHE_FLAT,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
};
@ -564,7 +564,7 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
ret = mcp_read(mcp, MCP_IOCON, &status);
if (ret < 0)
goto fail;
return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
mcp->irq_controller =
device_property_read_bool(dev, "interrupt-controller");
@ -598,7 +598,7 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
ret = mcp_write(mcp, MCP_IOCON, status);
if (ret < 0)
goto fail;
return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
}
if (mcp->irq && mcp->irq_controller) {
@ -616,7 +616,7 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
if (ret < 0)
goto fail;
return dev_err_probe(dev, ret, "can't add GPIO chip\n");
mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
@ -628,18 +628,17 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
mcp->pinctrl_desc.owner = THIS_MODULE;
mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
if (IS_ERR(mcp->pctldev)) {
ret = PTR_ERR(mcp->pctldev);
goto fail;
if (IS_ERR(mcp->pctldev))
return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
if (mcp->irq) {
ret = mcp23s08_irq_setup(mcp);
if (ret)
return dev_err_probe(dev, ret, "can't setup IRQ\n");
}
if (mcp->irq)
ret = mcp23s08_irq_setup(mcp);
fail:
if (ret < 0)
dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret);
return ret;
return 0;
}
EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
MODULE_LICENSE("GPL");

8
drivers/pinctrl/pinctrl-ocelot.c
View File

@ -1120,7 +1120,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
{
struct gpio_chip *gc;
struct gpio_irq_chip *girq;
int ret, irq;
int irq;
info->gpio_chip = ocelot_gpiolib_chip;
@ -1147,11 +1147,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
girq->handler = handle_edge_irq;
}
ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
if (ret)
return ret;
return 0;
return devm_gpiochip_add_data(&pdev->dev, gc, info);
}
static const struct of_device_id ocelot_pinctrl_of_match[] = {

4
drivers/pinctrl/pinctrl-single.c
View File

@ -1014,7 +1014,7 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
if (res)
return res;
if (pinctrl_spec.args_count < 2) {
if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
dev_err(pcs->dev, "invalid args_count for spec: %i\n",
pinctrl_spec.args_count);
break;
@ -1033,7 +1033,7 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
}
dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
pinctrl_spec.np, offset, pinctrl_spec.args[1]);
pinctrl_spec.np, offset, vals[found].val);
pin = pcs_get_pin_by_offset(pcs, offset);
if (pin < 0) {

17
drivers/pinctrl/pinctrl-sx150x.c
View File

@ -1154,12 +1154,6 @@ static int sx150x_probe(struct i2c_client *client,
return ret;
}
ret = pinctrl_enable(pctl->pctldev);
if (ret) {
dev_err(dev, "Failed to enable pinctrl device\n");
return ret;
}
/* Register GPIO controller */
pctl->gpio.base = -1;
pctl->gpio.ngpio = pctl->data->npins;
@ -1238,6 +1232,17 @@ static int sx150x_probe(struct i2c_client *client,
if (ret)
return ret;
/*
* Pin control functions need to be enabled AFTER registering the
* GPIO chip because sx150x_pinconf_set() calls
* sx150x_gpio_direction_output().
*/
ret = pinctrl_enable(pctl->pctldev);
if (ret) {
dev_err(dev, "Failed to enable pinctrl device\n");
return ret;
}
ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
0, 0, pctl->data->npins);
if (ret)

9
drivers/pinctrl/qcom/Kconfig
View File

@ -62,6 +62,15 @@ config PINCTRL_IPQ6018
Qualcomm Technologies Inc. IPQ6018 platform. Select this for
IPQ6018.
config PINCTRL_MSM8226
tristate "Qualcomm 8226 pin controller driver"
depends on GPIOLIB && OF
select PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc MSM8226 platform.
config PINCTRL_MSM8660
tristate "Qualcomm 8660 pin controller driver"
depends on GPIOLIB && OF

1
drivers/pinctrl/qcom/Makefile
View File

@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o

630
drivers/pinctrl/qcom/pinctrl-msm8226.c Normal file
View File

@ -0,0 +1,630 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
static const struct pinctrl_pin_desc msm8226_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
PINCTRL_PIN(2, "GPIO_2"),
PINCTRL_PIN(3, "GPIO_3"),
PINCTRL_PIN(4, "GPIO_4"),
PINCTRL_PIN(5, "GPIO_5"),
PINCTRL_PIN(6, "GPIO_6"),
PINCTRL_PIN(7, "GPIO_7"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "GPIO_34"),
PINCTRL_PIN(35, "GPIO_35"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GPIO_42"),
PINCTRL_PIN(43, "GPIO_43"),
PINCTRL_PIN(44, "GPIO_44"),
PINCTRL_PIN(45, "GPIO_45"),
PINCTRL_PIN(46, "GPIO_46"),
PINCTRL_PIN(47, "GPIO_47"),
PINCTRL_PIN(48, "GPIO_48"),
PINCTRL_PIN(49, "GPIO_49"),
PINCTRL_PIN(50, "GPIO_50"),
PINCTRL_PIN(51, "GPIO_51"),
PINCTRL_PIN(52, "GPIO_52"),
PINCTRL_PIN(53, "GPIO_53"),
PINCTRL_PIN(54, "GPIO_54"),
PINCTRL_PIN(55, "GPIO_55"),
PINCTRL_PIN(56, "GPIO_56"),
PINCTRL_PIN(57, "GPIO_57"),
PINCTRL_PIN(58, "GPIO_58"),
PINCTRL_PIN(59, "GPIO_59"),
PINCTRL_PIN(60, "GPIO_60"),
PINCTRL_PIN(61, "GPIO_61"),
PINCTRL_PIN(62, "GPIO_62"),
PINCTRL_PIN(63, "GPIO_63"),
PINCTRL_PIN(64, "GPIO_64"),
PINCTRL_PIN(65, "GPIO_65"),
PINCTRL_PIN(66, "GPIO_66"),
PINCTRL_PIN(67, "GPIO_67"),
PINCTRL_PIN(68, "GPIO_68"),
PINCTRL_PIN(69, "GPIO_69"),
PINCTRL_PIN(70, "GPIO_70"),
PINCTRL_PIN(71, "GPIO_71"),
PINCTRL_PIN(72, "GPIO_72"),
PINCTRL_PIN(73, "GPIO_73"),
PINCTRL_PIN(74, "GPIO_74"),
PINCTRL_PIN(75, "GPIO_75"),
PINCTRL_PIN(76, "GPIO_76"),
PINCTRL_PIN(77, "GPIO_77"),
PINCTRL_PIN(78, "GPIO_78"),
PINCTRL_PIN(79, "GPIO_79"),
PINCTRL_PIN(80, "GPIO_80"),
PINCTRL_PIN(81, "GPIO_81"),
PINCTRL_PIN(82, "GPIO_82"),
PINCTRL_PIN(83, "GPIO_83"),
PINCTRL_PIN(84, "GPIO_84"),
PINCTRL_PIN(85, "GPIO_85"),
PINCTRL_PIN(86, "GPIO_86"),
PINCTRL_PIN(87, "GPIO_87"),
PINCTRL_PIN(88, "GPIO_88"),
PINCTRL_PIN(89, "GPIO_89"),
PINCTRL_PIN(90, "GPIO_90"),
PINCTRL_PIN(91, "GPIO_91"),
PINCTRL_PIN(92, "GPIO_92"),
PINCTRL_PIN(93, "GPIO_93"),
PINCTRL_PIN(94, "GPIO_94"),
PINCTRL_PIN(95, "GPIO_95"),
PINCTRL_PIN(96, "GPIO_96"),
PINCTRL_PIN(97, "GPIO_97"),
PINCTRL_PIN(98, "GPIO_98"),
PINCTRL_PIN(99, "GPIO_99"),
PINCTRL_PIN(100, "GPIO_100"),
PINCTRL_PIN(101, "GPIO_101"),
PINCTRL_PIN(102, "GPIO_102"),
PINCTRL_PIN(103, "GPIO_103"),
PINCTRL_PIN(104, "GPIO_104"),
PINCTRL_PIN(105, "GPIO_105"),
PINCTRL_PIN(106, "GPIO_106"),
PINCTRL_PIN(107, "GPIO_107"),
PINCTRL_PIN(108, "GPIO_108"),
PINCTRL_PIN(109, "GPIO_109"),
PINCTRL_PIN(110, "GPIO_110"),
PINCTRL_PIN(111, "GPIO_111"),
PINCTRL_PIN(112, "GPIO_112"),
PINCTRL_PIN(113, "GPIO_113"),
PINCTRL_PIN(114, "GPIO_114"),
PINCTRL_PIN(115, "GPIO_115"),
PINCTRL_PIN(116, "GPIO_116"),
PINCTRL_PIN(117, "SDC1_CLK"),
PINCTRL_PIN(118, "SDC1_CMD"),
PINCTRL_PIN(119, "SDC1_DATA"),
PINCTRL_PIN(120, "SDC2_CLK"),
PINCTRL_PIN(121, "SDC2_CMD"),
PINCTRL_PIN(122, "SDC2_DATA"),
};
#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
DECLARE_MSM_GPIO_PINS(0);
DECLARE_MSM_GPIO_PINS(1);
DECLARE_MSM_GPIO_PINS(2);
DECLARE_MSM_GPIO_PINS(3);
DECLARE_MSM_GPIO_PINS(4);
DECLARE_MSM_GPIO_PINS(5);
DECLARE_MSM_GPIO_PINS(6);
DECLARE_MSM_GPIO_PINS(7);
DECLARE_MSM_GPIO_PINS(8);
DECLARE_MSM_GPIO_PINS(9);
DECLARE_MSM_GPIO_PINS(10);
DECLARE_MSM_GPIO_PINS(11);
DECLARE_MSM_GPIO_PINS(12);
DECLARE_MSM_GPIO_PINS(13);
DECLARE_MSM_GPIO_PINS(14);
DECLARE_MSM_GPIO_PINS(15);
DECLARE_MSM_GPIO_PINS(16);
DECLARE_MSM_GPIO_PINS(17);
DECLARE_MSM_GPIO_PINS(18);
DECLARE_MSM_GPIO_PINS(19);
DECLARE_MSM_GPIO_PINS(20);
DECLARE_MSM_GPIO_PINS(21);
DECLARE_MSM_GPIO_PINS(22);
DECLARE_MSM_GPIO_PINS(23);
DECLARE_MSM_GPIO_PINS(24);
DECLARE_MSM_GPIO_PINS(25);
DECLARE_MSM_GPIO_PINS(26);
DECLARE_MSM_GPIO_PINS(27);
DECLARE_MSM_GPIO_PINS(28);
DECLARE_MSM_GPIO_PINS(29);
DECLARE_MSM_GPIO_PINS(30);
DECLARE_MSM_GPIO_PINS(31);
DECLARE_MSM_GPIO_PINS(32);
DECLARE_MSM_GPIO_PINS(33);
DECLARE_MSM_GPIO_PINS(34);
DECLARE_MSM_GPIO_PINS(35);
DECLARE_MSM_GPIO_PINS(36);
DECLARE_MSM_GPIO_PINS(37);
DECLARE_MSM_GPIO_PINS(38);
DECLARE_MSM_GPIO_PINS(39);
DECLARE_MSM_GPIO_PINS(40);
DECLARE_MSM_GPIO_PINS(41);
DECLARE_MSM_GPIO_PINS(42);
DECLARE_MSM_GPIO_PINS(43);
DECLARE_MSM_GPIO_PINS(44);
DECLARE_MSM_GPIO_PINS(45);
DECLARE_MSM_GPIO_PINS(46);
DECLARE_MSM_GPIO_PINS(47);
DECLARE_MSM_GPIO_PINS(48);
DECLARE_MSM_GPIO_PINS(49);
DECLARE_MSM_GPIO_PINS(50);
DECLARE_MSM_GPIO_PINS(51);
DECLARE_MSM_GPIO_PINS(52);
DECLARE_MSM_GPIO_PINS(53);
DECLARE_MSM_GPIO_PINS(54);
DECLARE_MSM_GPIO_PINS(55);
DECLARE_MSM_GPIO_PINS(56);
DECLARE_MSM_GPIO_PINS(57);
DECLARE_MSM_GPIO_PINS(58);
DECLARE_MSM_GPIO_PINS(59);
DECLARE_MSM_GPIO_PINS(60);
DECLARE_MSM_GPIO_PINS(61);
DECLARE_MSM_GPIO_PINS(62);
DECLARE_MSM_GPIO_PINS(63);
DECLARE_MSM_GPIO_PINS(64);
DECLARE_MSM_GPIO_PINS(65);
DECLARE_MSM_GPIO_PINS(66);
DECLARE_MSM_GPIO_PINS(67);
DECLARE_MSM_GPIO_PINS(68);
DECLARE_MSM_GPIO_PINS(69);
DECLARE_MSM_GPIO_PINS(70);
DECLARE_MSM_GPIO_PINS(71);
DECLARE_MSM_GPIO_PINS(72);
DECLARE_MSM_GPIO_PINS(73);
DECLARE_MSM_GPIO_PINS(74);
DECLARE_MSM_GPIO_PINS(75);
DECLARE_MSM_GPIO_PINS(76);
DECLARE_MSM_GPIO_PINS(77);
DECLARE_MSM_GPIO_PINS(78);
DECLARE_MSM_GPIO_PINS(79);
DECLARE_MSM_GPIO_PINS(80);
DECLARE_MSM_GPIO_PINS(81);
DECLARE_MSM_GPIO_PINS(82);
DECLARE_MSM_GPIO_PINS(83);
DECLARE_MSM_GPIO_PINS(84);
DECLARE_MSM_GPIO_PINS(85);
DECLARE_MSM_GPIO_PINS(86);
DECLARE_MSM_GPIO_PINS(87);
DECLARE_MSM_GPIO_PINS(88);
DECLARE_MSM_GPIO_PINS(89);
DECLARE_MSM_GPIO_PINS(90);
DECLARE_MSM_GPIO_PINS(91);
DECLARE_MSM_GPIO_PINS(92);
DECLARE_MSM_GPIO_PINS(93);
DECLARE_MSM_GPIO_PINS(94);
DECLARE_MSM_GPIO_PINS(95);
DECLARE_MSM_GPIO_PINS(96);
DECLARE_MSM_GPIO_PINS(97);
DECLARE_MSM_GPIO_PINS(98);
DECLARE_MSM_GPIO_PINS(99);
DECLARE_MSM_GPIO_PINS(100);
DECLARE_MSM_GPIO_PINS(101);
DECLARE_MSM_GPIO_PINS(102);
DECLARE_MSM_GPIO_PINS(103);
DECLARE_MSM_GPIO_PINS(104);
DECLARE_MSM_GPIO_PINS(105);
DECLARE_MSM_GPIO_PINS(106);
DECLARE_MSM_GPIO_PINS(107);
DECLARE_MSM_GPIO_PINS(108);
DECLARE_MSM_GPIO_PINS(109);
DECLARE_MSM_GPIO_PINS(110);
DECLARE_MSM_GPIO_PINS(111);
DECLARE_MSM_GPIO_PINS(112);
DECLARE_MSM_GPIO_PINS(113);
DECLARE_MSM_GPIO_PINS(114);
DECLARE_MSM_GPIO_PINS(115);
DECLARE_MSM_GPIO_PINS(116);
static const unsigned int sdc1_clk_pins[] = { 117 };
static const unsigned int sdc1_cmd_pins[] = { 118 };
static const unsigned int sdc1_data_pins[] = { 119 };
static const unsigned int sdc2_clk_pins[] = { 120 };
static const unsigned int sdc2_cmd_pins[] = { 121 };
static const unsigned int sdc2_data_pins[] = { 122 };
#define FUNCTION(fname) \
[MSM_MUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){ \
MSM_MUX_gpio, \
MSM_MUX_##f1, \
MSM_MUX_##f2, \
MSM_MUX_##f3, \
MSM_MUX_##f4, \
MSM_MUX_##f5, \
MSM_MUX_##f6, \
MSM_MUX_##f7 \
}, \
.nfuncs = 8, \
.ctl_reg = 0x1000 + 0x10 * id, \
.io_reg = 0x1004 + 0x10 * id, \
.intr_cfg_reg = 0x1008 + 0x10 * id, \
.intr_status_reg = 0x100c + 0x10 * id, \
.intr_target_reg = 0x1008 + 0x10 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
.intr_target_kpss_val = 4, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 2, \
}
#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
{ \
.name = #pg_name, \
.pins = pg_name##_pins, \
.npins = ARRAY_SIZE(pg_name##_pins), \
.ctl_reg = ctl, \
.io_reg = 0, \
.intr_cfg_reg = 0, \
.intr_status_reg = 0, \
.intr_target_reg = 0, \
.mux_bit = -1, \
.pull_bit = pull, \
.drv_bit = drv, \
.oe_bit = -1, \
.in_bit = -1, \
.out_bit = -1, \
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
.intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \
.intr_detection_width = -1, \
}
/*
* TODO: Add the rest of the possible functions and fill out
* the pingroup table below.
*/
enum msm8226_functions {
MSM_MUX_gpio,
MSM_MUX_cci_i2c0,
MSM_MUX_blsp_i2c1,
MSM_MUX_blsp_i2c2,
MSM_MUX_blsp_i2c3,
MSM_MUX_blsp_i2c5,
MSM_MUX_blsp_spi1,
MSM_MUX_blsp_spi2,
MSM_MUX_blsp_spi3,
MSM_MUX_blsp_spi5,
MSM_MUX_blsp_uart1,
MSM_MUX_blsp_uart2,
MSM_MUX_blsp_uart3,
MSM_MUX_blsp_uart5,
MSM_MUX_blsp_uim1,
MSM_MUX_blsp_uim2,
MSM_MUX_blsp_uim3,
MSM_MUX_blsp_uim5,
MSM_MUX_cam_mclk0,
MSM_MUX_cam_mclk1,
MSM_MUX_wlan,
MSM_MUX_NA,
};
static const char * const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
};
static const char * const blsp_uart1_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3"
};
static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" };
static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" };
static const char * const blsp_spi1_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3"
};
static const char * const blsp_uart2_groups[] = {
"gpio4", "gpio5", "gpio6", "gpio7"
};
static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" };
static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
static const char * const blsp_spi2_groups[] = {
"gpio4", "gpio5", "gpio6", "gpio7"
};
static const char * const blsp_uart3_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11"
};
static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" };
static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" };
static const char * const blsp_spi3_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11"
};
static const char * const blsp_uart5_groups[] = {
"gpio16", "gpio17", "gpio18", "gpio19"
};
static const char * const blsp_uim5_groups[] = { "gpio16", "gpio17" };
static const char * const blsp_i2c5_groups[] = { "gpio18", "gpio19" };
static const char * const blsp_spi5_groups[] = {
"gpio16", "gpio17", "gpio18", "gpio19"
};
static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" };
static const char * const cam_mclk0_groups[] = { "gpio26" };
static const char * const cam_mclk1_groups[] = { "gpio27" };
static const char * const wlan_groups[] = {
"gpio40", "gpio41", "gpio42", "gpio43", "gpio44"
};
static const struct msm_function msm8226_functions[] = {
FUNCTION(gpio),
FUNCTION(cci_i2c0),
FUNCTION(blsp_uim1),
FUNCTION(blsp_uim2),
FUNCTION(blsp_uim3),
FUNCTION(blsp_uim5),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_i2c2),
FUNCTION(blsp_i2c3),
FUNCTION(blsp_i2c5),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi2),
FUNCTION(blsp_spi3),
FUNCTION(blsp_spi5),
FUNCTION(blsp_uart1),
FUNCTION(blsp_uart2),
FUNCTION(blsp_uart3),
FUNCTION(blsp_uart5),
FUNCTION(cam_mclk0),
FUNCTION(cam_mclk1),
FUNCTION(wlan),
};
static const struct msm_pingroup msm8226_groups[] = {
PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA),
PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA),
PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
PINGROUP(12, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(13, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(14, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(15, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(16, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
PINGROUP(17, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
PINGROUP(20, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(21, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(22, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(23, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(24, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(25, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(26, cam_mclk0, NA, NA, NA, NA, NA, NA),
PINGROUP(27, cam_mclk1, NA, NA, NA, NA, NA, NA),
PINGROUP(28, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(29, cci_i2c0, NA, NA, NA, NA, NA, NA),
PINGROUP(30, cci_i2c0, NA, NA, NA, NA, NA, NA),
PINGROUP(31, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(32, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(33, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(34, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(35, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(36, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(37, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(38, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(39, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(40, wlan, NA, NA, NA, NA, NA, NA),
PINGROUP(41, wlan, NA, NA, NA, NA, NA, NA),
PINGROUP(42, wlan, NA, NA, NA, NA, NA, NA),
PINGROUP(43, wlan, NA, NA, NA, NA, NA, NA),
PINGROUP(44, wlan, NA, NA, NA, NA, NA, NA),
PINGROUP(45, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(46, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(47, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(48, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(49, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(50, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(51, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(52, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(53, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(54, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(55, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(56, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(57, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(58, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(59, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(60, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(61, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(62, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(63, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(64, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(65, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(66, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(67, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(68, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(69, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(70, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(71, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(72, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(73, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(74, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(75, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(76, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(77, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(78, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(79, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(80, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(81, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(82, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(83, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(84, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(85, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(86, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(87, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(88, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(89, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(90, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(91, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(92, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(93, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(94, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(95, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(96, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(97, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(98, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(99, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(100, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(101, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(102, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(103, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(104, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(105, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(106, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(107, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(108, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(109, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(110, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(111, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(112, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(113, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(114, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(115, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(116, NA, NA, NA, NA, NA, NA, NA),
SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
};
#define NUM_GPIO_PINGROUPS 117
static const struct msm_pinctrl_soc_data msm8226_pinctrl = {
.pins = msm8226_pins,
.npins = ARRAY_SIZE(msm8226_pins),
.functions = msm8226_functions,
.nfunctions = ARRAY_SIZE(msm8226_functions),
.groups = msm8226_groups,
.ngroups = ARRAY_SIZE(msm8226_groups),
.ngpios = NUM_GPIO_PINGROUPS,
};
static int msm8226_pinctrl_probe(struct platform_device *pdev)
{
return msm_pinctrl_probe(pdev, &msm8226_pinctrl);
}
static const struct of_device_id msm8226_pinctrl_of_match[] = {
{ .compatible = "qcom,msm8226-pinctrl", },
{ },
};
static struct platform_driver msm8226_pinctrl_driver = {
.driver = {
.name = "msm8226-pinctrl",
.of_match_table = msm8226_pinctrl_of_match,
},
.probe = msm8226_pinctrl_probe,
.remove = msm_pinctrl_remove,
};
static int __init msm8226_pinctrl_init(void)
{
return platform_driver_register(&msm8226_pinctrl_driver);
}
arch_initcall(msm8226_pinctrl_init);
static void __exit msm8226_pinctrl_exit(void)
{
platform_driver_unregister(&msm8226_pinctrl_driver);
}
module_exit(msm8226_pinctrl_exit);
MODULE_AUTHOR("Bartosz Dudziak <bartosz.dudziak@snejp.pl>");
MODULE_DESCRIPTION("Qualcomm MSM8226 pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match);

290
drivers/pinctrl/sh-pfc/Kconfig → drivers/pinctrl/renesas/Kconfig
View File

@ -3,12 +3,11 @@
# Renesas SH and SH Mobile PINCTRL drivers
#
config PINCTRL_SH_PFC
menu "Renesas pinctrl drivers"
config PINCTRL_RENESAS
bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH)
default y if ARCH_RENESAS || SUPERH
select PINMUX
select PINCONF
select GENERIC_PINCONF
select PINCTRL_PFC_EMEV2 if ARCH_EMEV2
select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4
select PINCTRL_PFC_R8A7740 if ARCH_R8A7740
@ -53,153 +52,220 @@ config PINCTRL_SH_PFC
help
This enables pin control drivers for Renesas SuperH and ARM platforms
config PINCTRL_SH_PFC_GPIO
select GPIOLIB
config PINCTRL_SH_PFC
bool
select GENERIC_PINCONF
select PINMUX
select PINCONF
help
This enables common pin control functionality for EMMA Mobile, R-Car,
R-Mobile, RZ/G, SH, and SH-Mobile platforms.
config PINCTRL_SH_PFC_GPIO
bool
select GPIOLIB
select PINCTRL_SH_PFC
help
This enables pin control and GPIO drivers for SH/SH Mobile platforms
config PINCTRL_SH_FUNC_GPIO
select PINCTRL_SH_PFC_GPIO
bool
select PINCTRL_SH_PFC_GPIO
help
This enables legacy function GPIOs for SH platforms
config PINCTRL_PFC_EMEV2
bool "Emma Mobile AV2 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A73A4
bool "R-Mobile APE6 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7740
bool "R-Mobile A1 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7742
bool "RZ/G1H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7743
bool "RZ/G1M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7744
bool "RZ/G1N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7745
bool "RZ/G1E pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77470
bool "RZ/G1C pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774A1
bool "RZ/G2M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774B1
bool "RZ/G2N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774C0
bool "RZ/G2E pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774E1
bool "RZ/G2H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7778
bool "R-Car M1A pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7779
bool "R-Car H1 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7790
bool "R-Car H2 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7791
bool "R-Car M2-W pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7792
bool "R-Car V2H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7793
bool "R-Car M2-N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A7794
bool "R-Car E2 pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77950
bool "R-Car H3 ES1.x pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77951
bool "R-Car H3 ES2.0+ pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77960
bool "R-Car M3-W pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77961
bool "R-Car M3-W+ pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77965
bool "R-Car M3-N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77970
bool "R-Car V3M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77980
bool "R-Car V3H pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A77990
bool "R-Car E3 pin control support" if COMPILE_TEST
bool "pin control support for Emma Mobile EV2" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77995
bool "R-Car D3 pin control support" if COMPILE_TEST
bool "pin control support for R-Car D3" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7794
bool "pin control support for R-Car E2" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77990
bool "pin control support for R-Car E3" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7779
bool "pin control support for R-Car H1" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7790
bool "pin control support for R-Car H2" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77950
bool "pin control support for R-Car H3 ES1.x" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77951
bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7778
bool "pin control support for R-Car M1A" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7793
bool "pin control support for R-Car M2-N" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7791
bool "pin control support for R-Car M2-W" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77965
bool "pin control support for R-Car M3-N" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77960
bool "pin control support for R-Car M3-W" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77961
bool "pin control support for R-Car M3-W+" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7792
bool "pin control support for R-Car V2H" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77980
bool "pin control support for R-Car V3H" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77970
bool "pin control support for R-Car V3M" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7740
bool "pin control support for R-Mobile A1" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A73A4
bool "pin control support for R-Mobile APE6" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
config PINCTRL_RZA1
bool "pin control support for RZ/A1"
depends on OF
depends on ARCH_R7S72100 || COMPILE_TEST
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
help
This selects pinctrl driver for Renesas RZ/A1 platforms.
config PINCTRL_RZA2
bool "pin control support for RZ/A2"
depends on OF
depends on ARCH_R7S9210 || COMPILE_TEST
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GPIOLIB
help
This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.
config PINCTRL_PFC_R8A77470
bool "pin control support for RZ/G1C" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7745
bool "pin control support for RZ/G1E" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7742
bool "pin control support for RZ/G1H" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7743
bool "pin control support for RZ/G1M" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7744
bool "pin control support for RZ/G1N" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A774C0
bool "pin control support for RZ/G2E" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A774E1
bool "pin control support for RZ/G2H" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A774A1
bool "pin control support for RZ/G2M" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A774B1
bool "pin control support for RZ/G2N" if COMPILE_TEST
select PINCTRL_SH_PFC
config PINCTRL_RZN1
bool "pin control support for RZ/N1"
depends on OF
depends on ARCH_RZN1 || COMPILE_TEST
select GENERIC_PINCONF
help
This selects pinctrl driver for Renesas RZ/N1 devices.
config PINCTRL_PFC_SH7203
bool "SH7203 pin control support" if COMPILE_TEST
bool "pin control support for SH7203" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7264
bool "SH7264 pin control support" if COMPILE_TEST
bool "pin control support for SH7264" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7269
bool "SH7269 pin control support" if COMPILE_TEST
bool "pin control support for SH7269" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH73A0
bool "SH-Mobile AG5 pin control support" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
select REGULATOR
config PINCTRL_PFC_SH7720
bool "SH7720 pin control support" if COMPILE_TEST
bool "pin control support for SH7720" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7722
bool "SH7722 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7723
bool "SH-Mobile R2 pin control support" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7724
bool "SH-Mobile R2R pin control support" if COMPILE_TEST
bool "pin control support for SH7722" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7734
bool "SH7734 pin control support" if COMPILE_TEST
bool "pin control support for SH7734" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7757
bool "SH7757 pin control support" if COMPILE_TEST
bool "pin control support for SH7757" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7785
bool "SH7785 pin control support" if COMPILE_TEST
bool "pin control support for SH7785" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7786
bool "SH7786 pin control support" if COMPILE_TEST
bool "pin control support for SH7786" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH73A0
bool "pin control support for SH-Mobile AG5" if COMPILE_TEST
select PINCTRL_SH_PFC_GPIO
select REGULATOR
config PINCTRL_PFC_SH7723
bool "pin control support for SH-Mobile R2" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SH7724
bool "pin control support for SH-Mobile R2R" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
config PINCTRL_PFC_SHX3
bool "SH-X3 pin control support" if COMPILE_TEST
bool "pin control support for SH-X3" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
endmenu

8
drivers/pinctrl/sh-pfc/Makefile → drivers/pinctrl/renesas/Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o
obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o
obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o
obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
obj-$(CONFIG_PINCTRL_PFC_R8A7742) += pfc-r8a7790.o
@ -43,6 +43,10 @@ obj-$(CONFIG_PINCTRL_PFC_SH7785) += pfc-sh7785.o
obj-$(CONFIG_PINCTRL_PFC_SH7786) += pfc-sh7786.o
obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
ifeq ($(CONFIG_COMPILE_TEST),y)
CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a
CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a

0
drivers/pinctrl/sh-pfc/core.c → drivers/pinctrl/renesas/core.c
View File

0
drivers/pinctrl/sh-pfc/core.h → drivers/pinctrl/renesas/core.h
View File

0
drivers/pinctrl/sh-pfc/gpio.c → drivers/pinctrl/renesas/gpio.c
View File

0
drivers/pinctrl/sh-pfc/pfc-emev2.c → drivers/pinctrl/renesas/pfc-emev2.c
View File

0
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c → drivers/pinctrl/renesas/pfc-r8a73a4.c
View File

0
drivers/pinctrl/sh-pfc/pfc-r8a7740.c → drivers/pinctrl/renesas/pfc-r8a7740.c
View File

0
drivers/pinctrl/sh-pfc/pfc-r8a77470.c → drivers/pinctrl/renesas/pfc-r8a77470.c
View File

0
drivers/pinctrl/sh-pfc/pfc-r8a7778.c → drivers/pinctrl/renesas/pfc-r8a7778.c
View File

0
drivers/pinctrl/sh-pfc/pfc-r8a7779.c → drivers/pinctrl/renesas/pfc-r8a7779.c
View File

121
drivers/pinctrl/sh-pfc/pfc-r8a7790.c → drivers/pinctrl/renesas/pfc-r8a7790.c
View File

@ -1871,6 +1871,86 @@ static const unsigned int avb_gmii_mux[] = {
AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
AVB_COL_MARK,
};
/* - CAN0 ----------------------------------------------------------------- */
static const unsigned int can0_data_pins[] = {
/* CAN0 RX */
RCAR_GP_PIN(1, 17),
/* CAN0 TX */
RCAR_GP_PIN(1, 19),
};
static const unsigned int can0_data_mux[] = {
CAN0_RX_MARK,
CAN0_TX_MARK,
};
static const unsigned int can0_data_b_pins[] = {
/* CAN0 RXB */
RCAR_GP_PIN(4, 5),
/* CAN0 TXB */
RCAR_GP_PIN(4, 4),
};
static const unsigned int can0_data_b_mux[] = {
CAN0_RX_B_MARK,
CAN0_TX_B_MARK,
};
static const unsigned int can0_data_c_pins[] = {
/* CAN0 RXC */
RCAR_GP_PIN(4, 26),
/* CAN0 TXC */
RCAR_GP_PIN(4, 23),
};
static const unsigned int can0_data_c_mux[] = {
CAN0_RX_C_MARK,
CAN0_TX_C_MARK,
};
static const unsigned int can0_data_d_pins[] = {
/* CAN0 RXD */
RCAR_GP_PIN(4, 26),
/* CAN0 TXD */
RCAR_GP_PIN(4, 18),
};
static const unsigned int can0_data_d_mux[] = {
CAN0_RX_D_MARK,
CAN0_TX_D_MARK,
};
/* - CAN1 ----------------------------------------------------------------- */
static const unsigned int can1_data_pins[] = {
/* CAN1 RX */
RCAR_GP_PIN(1, 22),
/* CAN1 TX */
RCAR_GP_PIN(1, 18),
};
static const unsigned int can1_data_mux[] = {
CAN1_RX_MARK,
CAN1_TX_MARK,
};
static const unsigned int can1_data_b_pins[] = {
/* CAN1 RXB */
RCAR_GP_PIN(4, 7),
/* CAN1 TXB */
RCAR_GP_PIN(4, 6),
};
static const unsigned int can1_data_b_mux[] = {
CAN1_RX_B_MARK,
CAN1_TX_B_MARK,
};
/* - CAN Clock -------------------------------------------------------------- */
static const unsigned int can_clk_pins[] = {
/* CLK */
RCAR_GP_PIN(1, 21),
};
static const unsigned int can_clk_mux[] = {
CAN_CLK_MARK,
};
static const unsigned int can_clk_b_pins[] = {
/* CLK */
RCAR_GP_PIN(4, 3),
};
static const unsigned int can_clk_b_mux[] = {
CAN_CLK_B_MARK,
};
/* - DU RGB ----------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
/* R[7:2], G[7:2], B[7:2] */
@ -3611,6 +3691,13 @@ static const unsigned int usb1_pins[] = {
static const unsigned int usb1_mux[] = {
USB1_PWEN_MARK, USB1_OVC_MARK,
};
static const unsigned int usb1_pwen_pins[] = {
/* PWEN */
RCAR_GP_PIN(5, 20),
};
static const unsigned int usb1_pwen_mux[] = {
USB1_PWEN_MARK,
};
/* - USB2 ------------------------------------------------------------------- */
static const unsigned int usb2_pins[] = {
/* PWEN, OVC */
@ -3939,7 +4026,7 @@ static const unsigned int vin3_clk_mux[] = {
};
static const struct {
struct sh_pfc_pin_group common[289];
struct sh_pfc_pin_group common[298];
struct sh_pfc_pin_group automotive[1];
} pinmux_groups = {
.common = {
@ -3956,6 +4043,14 @@ static const struct {
SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_gmii),
SH_PFC_PIN_GROUP(can0_data),
SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(can0_data_c),
SH_PFC_PIN_GROUP(can0_data_d),
SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can1_data_b),
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(can_clk_b),
SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(du_clk_out_0),
@ -4193,6 +4288,7 @@ static const struct {
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb0_ovc_vbus),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb1_pwen),
SH_PFC_PIN_GROUP(usb2),
VIN_DATA_PIN_GROUP(vin0_data, 24),
VIN_DATA_PIN_GROUP(vin0_data, 20),
@ -4257,6 +4353,23 @@ static const char * const avb_groups[] = {
"avb_gmii",
};
static const char * const can0_groups[] = {
"can0_data",
"can0_data_b",
"can0_data_c",
"can0_data_d",
};
static const char * const can1_groups[] = {
"can1_data",
"can1_data_b",
};
static const char * const can_clk_groups[] = {
"can_clk",
"can_clk_b",
};
static const char * const du_groups[] = {
"du_rgb666",
"du_rgb888",
@ -4640,6 +4753,7 @@ static const char * const usb0_groups[] = {
static const char * const usb1_groups[] = {
"usb1",
"usb1_pwen",
};
static const char * const usb2_groups[] = {
@ -4697,13 +4811,16 @@ static const char * const vin3_groups[] = {
};
static const struct {
struct sh_pfc_function common[55];
struct sh_pfc_function common[58];
struct sh_pfc_function automotive[1];
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(du0),
SH_PFC_FUNCTION(du1),
SH_PFC_FUNCTION(du2),

0
drivers/pinctrl/sh-pfc/pfc-r8a7791.c → drivers/pinctrl/renesas/pfc-r8a7791.c
View File

0
drivers/pinctrl/sh-pfc/pfc-r8a7792.c → drivers/pinctrl/renesas/pfc-r8a7792.c
View File

0
drivers/pinctrl/sh-pfc/pfc-r8a7794.c → drivers/pinctrl/renesas/pfc-r8a7794.c
View File

0
drivers/pinctrl/sh-pfc/pfc-r8a77950.c → drivers/pinctrl/renesas/pfc-r8a77950.c
View File

0
drivers/pinctrl/sh-pfc/pfc-r8a77951.c → drivers/pinctrl/renesas/pfc-r8a77951.c
View File

2
drivers/pinctrl/sh-pfc/pfc-r8a7796.c → drivers/pinctrl/renesas/pfc-r8a7796.c
View File

@ -4,7 +4,7 @@
*
* Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
*
* R-Car Gen3 processor support - PFC hardware block.
*

2
drivers/pinctrl/sh-pfc/pfc-r8a77965.c → drivers/pinctrl/renesas/pfc-r8a77965.c
View File

@ -5,7 +5,7 @@
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
* Copyright (C) 2016-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
*
* R-Car Gen3 processor support - PFC hardware block.
*

2
drivers/pinctrl/sh-pfc/pfc-r8a77970.c → drivers/pinctrl/renesas/pfc-r8a77970.c
View File

@ -5,7 +5,7 @@
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
*
* R-Car Gen3 processor support - PFC hardware block.
*

2
drivers/pinctrl/sh-pfc/pfc-r8a77980.c → drivers/pinctrl/renesas/pfc-r8a77980.c
View File

@ -5,7 +5,7 @@
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
*
* R-Car Gen3 processor support - PFC hardware block.
*

2
drivers/pinctrl/sh-pfc/pfc-r8a77990.c → drivers/pinctrl/renesas/pfc-r8a77990.c
View File

@ -4,7 +4,7 @@
*
* Copyright (C) 2018-2019 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
*
* R8A7796 processor support - PFC hardware block.
*

2
drivers/pinctrl/sh-pfc/pfc-r8a77995.c → drivers/pinctrl/renesas/pfc-r8a77995.c
View File

@ -4,7 +4,7 @@
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
*
* R-Car Gen3 processor support - PFC hardware block.
*

0
drivers/pinctrl/sh-pfc/pfc-sh7203.c → drivers/pinctrl/renesas/pfc-sh7203.c
View File

0
drivers/pinctrl/sh-pfc/pfc-sh7264.c → drivers/pinctrl/renesas/pfc-sh7264.c
View File

0
drivers/pinctrl/sh-pfc/pfc-sh7269.c → drivers/pinctrl/renesas/pfc-sh7269.c
View File

0
drivers/pinctrl/sh-pfc/pfc-sh73a0.c → drivers/pinctrl/renesas/pfc-sh73a0.c
View File

0
drivers/pinctrl/sh-pfc/pfc-sh7720.c → drivers/pinctrl/renesas/pfc-sh7720.c
View File

0
drivers/pinctrl/sh-pfc/pfc-sh7722.c → drivers/pinctrl/renesas/pfc-sh7722.c
View File

0
drivers/pinctrl/sh-pfc/pfc-sh7723.c → drivers/pinctrl/renesas/pfc-sh7723.c
View File

0
drivers/pinctrl/sh-pfc/pfc-sh7724.c → drivers/pinctrl/renesas/pfc-sh7724.c
View File

0
drivers/pinctrl/sh-pfc/pfc-sh7734.c → drivers/pinctrl/renesas/pfc-sh7734.c
View File

0
drivers/pinctrl/sh-pfc/pfc-sh7757.c → drivers/pinctrl/renesas/pfc-sh7757.c
View File

0
drivers/pinctrl/sh-pfc/pfc-sh7785.c → drivers/pinctrl/renesas/pfc-sh7785.c
View File

Some files were not shown because too many files have changed in this diff Show More