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serial: imx: add DMA support for imx6q
We only enable the DMA support when the following are meet:
[1] The uart port supports the hardware flow control(CTS/RTS).
(Some uart port does not support the CTS/RTS.)
[2] The application enables the CTS/RTS.
[3] The Soc is imx6q.
For the sdma's firmware limit, we do not support the DMA except
the imx6q platform.
[4] The uart is not used as a console.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Huang Shijie
Greg Kroah-Hartman
parent
09bd00f6e9
commit
b4cdc8f61b
@ -48,9 +48,11 @@
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <asm/irq.h>
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#include <linux/platform_data/serial-imx.h>
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#include <linux/platform_data/dma-imx.h>
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/* Register definitions */
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#define URXD0 0x0 /* Receiver Register */
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@ -82,6 +84,7 @@
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#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
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#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
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#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
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#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
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#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
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#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
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#define UCR1_IREN (1<<7) /* Infrared interface enable */
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@ -90,6 +93,7 @@
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#define UCR1_SNDBRK (1<<4) /* Send break */
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#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
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#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
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#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
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#define UCR1_DOZE (1<<1) /* Doze */
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#define UCR1_UARTEN (1<<0) /* UART enabled */
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#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
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@ -125,6 +129,7 @@
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
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#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
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#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
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#define UCR4_IRSC (1<<5) /* IR special case */
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#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
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#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
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@ -209,6 +214,19 @@ struct imx_port {
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struct clk *clk_ipg;
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struct clk *clk_per;
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const struct imx_uart_data *devdata;
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/* DMA fields */
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unsigned int dma_is_inited:1;
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unsigned int dma_is_enabled:1;
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unsigned int dma_is_rxing:1;
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unsigned int dma_is_txing:1;
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struct dma_chan *dma_chan_rx, *dma_chan_tx;
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struct scatterlist rx_sgl, tx_sgl[2];
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void *rx_buf;
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unsigned int rx_bytes, tx_bytes;
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struct work_struct tsk_dma_rx, tsk_dma_tx;
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unsigned int dma_tx_nents;
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wait_queue_head_t dma_wait;
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};
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struct imx_port_ucrs {
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@ -399,6 +417,13 @@ static void imx_stop_tx(struct uart_port *port)
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return;
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}
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/*
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* We are maybe in the SMP context, so if the DMA TX thread is running
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* on other cpu, we have to wait for it to finish.
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*/
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if (sport->dma_is_enabled && sport->dma_is_txing)
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return;
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temp = readl(sport->port.membase + UCR1);
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writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
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}
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@ -411,6 +436,13 @@ static void imx_stop_rx(struct uart_port *port)
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struct imx_port *sport = (struct imx_port *)port;
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unsigned long temp;
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/*
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* We are maybe in the SMP context, so if the DMA TX thread is running
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* on other cpu, we have to wait for it to finish.
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*/
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if (sport->dma_is_enabled && sport->dma_is_rxing)
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return;
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temp = readl(sport->port.membase + UCR2);
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writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
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}
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@ -446,6 +478,95 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
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imx_stop_tx(&sport->port);
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}
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static void dma_tx_callback(void *data)
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{
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struct imx_port *sport = data;
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struct scatterlist *sgl = &sport->tx_sgl[0];
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struct circ_buf *xmit = &sport->port.state->xmit;
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unsigned long flags;
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dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
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sport->dma_is_txing = 0;
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/* update the stat */
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spin_lock_irqsave(&sport->port.lock, flags);
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xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
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sport->port.icount.tx += sport->tx_bytes;
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spin_unlock_irqrestore(&sport->port.lock, flags);
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dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&sport->port);
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if (waitqueue_active(&sport->dma_wait)) {
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wake_up(&sport->dma_wait);
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dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
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return;
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}
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schedule_work(&sport->tsk_dma_tx);
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}
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static void dma_tx_work(struct work_struct *w)
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{
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struct imx_port *sport = container_of(w, struct imx_port, tsk_dma_tx);
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struct circ_buf *xmit = &sport->port.state->xmit;
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struct scatterlist *sgl = sport->tx_sgl;
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struct dma_async_tx_descriptor *desc;
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struct dma_chan *chan = sport->dma_chan_tx;
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struct device *dev = sport->port.dev;
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enum dma_status status;
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unsigned long flags;
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int ret;
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status = chan->device->device_tx_status(chan, (dma_cookie_t)0, NULL);
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if (DMA_IN_PROGRESS == status)
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return;
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spin_lock_irqsave(&sport->port.lock, flags);
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sport->tx_bytes = uart_circ_chars_pending(xmit);
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if (sport->tx_bytes == 0) {
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spin_unlock_irqrestore(&sport->port.lock, flags);
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return;
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}
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if (xmit->tail > xmit->head) {
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sport->dma_tx_nents = 2;
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sg_init_table(sgl, 2);
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sg_set_buf(sgl, xmit->buf + xmit->tail,
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UART_XMIT_SIZE - xmit->tail);
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sg_set_buf(sgl + 1, xmit->buf, xmit->head);
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} else {
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sport->dma_tx_nents = 1;
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sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
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}
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spin_unlock_irqrestore(&sport->port.lock, flags);
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ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
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if (ret == 0) {
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dev_err(dev, "DMA mapping error for TX.\n");
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return;
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}
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desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
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if (!desc) {
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dev_err(dev, "We cannot prepare for the TX slave dma!\n");
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return;
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}
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desc->callback = dma_tx_callback;
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desc->callback_param = sport;
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dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
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uart_circ_chars_pending(xmit));
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/* fire it */
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sport->dma_is_txing = 1;
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dmaengine_submit(desc);
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dma_async_issue_pending(chan);
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return;
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}
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/*
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* interrupts disabled on entry
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*/
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@ -472,8 +593,10 @@ static void imx_start_tx(struct uart_port *port)
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temp |= UCR4_OREN;
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writel(temp, sport->port.membase + UCR4);
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temp = readl(sport->port.membase + UCR1);
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writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
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if (!sport->dma_is_enabled) {
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temp = readl(sport->port.membase + UCR1);
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writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
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}
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if (USE_IRDA(sport)) {
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temp = readl(sport->port.membase + UCR1);
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@ -485,6 +608,15 @@ static void imx_start_tx(struct uart_port *port)
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writel(temp, sport->port.membase + UCR4);
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}
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if (sport->dma_is_enabled) {
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/*
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* We may in the interrupt context, so arise a work_struct to
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* do the real job.
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*/
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schedule_work(&sport->tsk_dma_tx);
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return;
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}
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if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
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imx_transmit_buffer(sport);
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}
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@ -600,6 +732,28 @@ out:
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return IRQ_HANDLED;
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}
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/*
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* If the RXFIFO is filled with some data, and then we
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* arise a DMA operation to receive them.
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*/
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static void imx_dma_rxint(struct imx_port *sport)
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{
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unsigned long temp;
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temp = readl(sport->port.membase + USR2);
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if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
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sport->dma_is_rxing = 1;
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/* disable the `Recerver Ready Interrrupt` */
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temp = readl(sport->port.membase + UCR1);
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temp &= ~(UCR1_RRDYEN);
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writel(temp, sport->port.membase + UCR1);
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/* tell the DMA to receive the data. */
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schedule_work(&sport->tsk_dma_rx);
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}
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}
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static irqreturn_t imx_int(int irq, void *dev_id)
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{
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struct imx_port *sport = dev_id;
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@ -608,8 +762,12 @@ static irqreturn_t imx_int(int irq, void *dev_id)
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sts = readl(sport->port.membase + USR1);
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if (sts & USR1_RRDY)
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imx_rxint(irq, dev_id);
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if (sts & USR1_RRDY) {
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if (sport->dma_is_enabled)
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imx_dma_rxint(sport);
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else
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imx_rxint(irq, dev_id);
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}
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if (sts & USR1_TRDY &&
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readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
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@ -666,7 +824,8 @@ static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
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temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
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if (mctrl & TIOCM_RTS)
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temp |= UCR2_CTS;
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if (!sport->dma_is_enabled)
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temp |= UCR2_CTS;
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writel(temp, sport->port.membase + UCR2);
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}
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@ -705,6 +864,226 @@ static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
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return 0;
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}
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#define RX_BUF_SIZE (PAGE_SIZE)
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static int start_rx_dma(struct imx_port *sport);
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static void dma_rx_work(struct work_struct *w)
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{
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struct imx_port *sport = container_of(w, struct imx_port, tsk_dma_rx);
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struct tty_port *port = &sport->port.state->port;
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if (sport->rx_bytes) {
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tty_insert_flip_string(port, sport->rx_buf, sport->rx_bytes);
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tty_flip_buffer_push(port);
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sport->rx_bytes = 0;
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}
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if (sport->dma_is_rxing)
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start_rx_dma(sport);
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}
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static void imx_rx_dma_done(struct imx_port *sport)
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{
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unsigned long temp;
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/* Enable this interrupt when the RXFIFO is empty. */
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temp = readl(sport->port.membase + UCR1);
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temp |= UCR1_RRDYEN;
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writel(temp, sport->port.membase + UCR1);
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sport->dma_is_rxing = 0;
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/* Is the shutdown waiting for us? */
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if (waitqueue_active(&sport->dma_wait))
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wake_up(&sport->dma_wait);
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}
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/*
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* There are three kinds of RX DMA interrupts(such as in the MX6Q):
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* [1] the RX DMA buffer is full.
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* [2] the Aging timer expires(wait for 8 bytes long)
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* [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
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*
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* The [2] is trigger when a character was been sitting in the FIFO
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* meanwhile [3] can wait for 32 bytes long when the RX line is
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* on IDLE state and RxFIFO is empty.
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*/
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static void dma_rx_callback(void *data)
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{
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struct imx_port *sport = data;
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struct dma_chan *chan = sport->dma_chan_rx;
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struct scatterlist *sgl = &sport->rx_sgl;
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struct dma_tx_state state;
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enum dma_status status;
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unsigned int count;
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/* unmap it first */
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dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
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status = chan->device->device_tx_status(chan, (dma_cookie_t)0, &state);
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count = RX_BUF_SIZE - state.residue;
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dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
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if (count) {
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sport->rx_bytes = count;
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schedule_work(&sport->tsk_dma_rx);
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} else
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imx_rx_dma_done(sport);
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}
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static int start_rx_dma(struct imx_port *sport)
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{
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struct scatterlist *sgl = &sport->rx_sgl;
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struct dma_chan *chan = sport->dma_chan_rx;
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struct device *dev = sport->port.dev;
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struct dma_async_tx_descriptor *desc;
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int ret;
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sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
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ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
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if (ret == 0) {
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dev_err(dev, "DMA mapping error for RX.\n");
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return -EINVAL;
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}
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desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT);
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if (!desc) {
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dev_err(dev, "We cannot prepare for the RX slave dma!\n");
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return -EINVAL;
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}
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desc->callback = dma_rx_callback;
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desc->callback_param = sport;
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dev_dbg(dev, "RX: prepare for the DMA.\n");
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dmaengine_submit(desc);
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dma_async_issue_pending(chan);
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return 0;
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}
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static void imx_uart_dma_exit(struct imx_port *sport)
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{
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if (sport->dma_chan_rx) {
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dma_release_channel(sport->dma_chan_rx);
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sport->dma_chan_rx = NULL;
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kfree(sport->rx_buf);
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sport->rx_buf = NULL;
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}
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if (sport->dma_chan_tx) {
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dma_release_channel(sport->dma_chan_tx);
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sport->dma_chan_tx = NULL;
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}
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sport->dma_is_inited = 0;
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}
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static int imx_uart_dma_init(struct imx_port *sport)
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{
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struct dma_slave_config slave_config;
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struct device *dev = sport->port.dev;
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int ret;
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/* Prepare for RX : */
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sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
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if (!sport->dma_chan_rx) {
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dev_dbg(dev, "cannot get the DMA channel.\n");
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ret = -EINVAL;
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goto err;
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}
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slave_config.direction = DMA_DEV_TO_MEM;
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slave_config.src_addr = sport->port.mapbase + URXD0;
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slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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slave_config.src_maxburst = RXTL;
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ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
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if (ret) {
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dev_err(dev, "error in RX dma configuration.\n");
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goto err;
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}
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sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
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if (!sport->rx_buf) {
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dev_err(dev, "cannot alloc DMA buffer.\n");
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ret = -ENOMEM;
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goto err;
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}
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sport->rx_bytes = 0;
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/* Prepare for TX : */
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sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
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if (!sport->dma_chan_tx) {
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dev_err(dev, "cannot get the TX DMA channel!\n");
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ret = -EINVAL;
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goto err;
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}
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slave_config.direction = DMA_MEM_TO_DEV;
|
||||
slave_config.dst_addr = sport->port.mapbase + URTX0;
|
||||
slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
||||
slave_config.dst_maxburst = TXTL;
|
||||
ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
|
||||
if (ret) {
|
||||
dev_err(dev, "error in TX dma configuration.");
|
||||
goto err;
|
||||
}
|
||||
|
||||
sport->dma_is_inited = 1;
|
||||
|
||||
return 0;
|
||||
err:
|
||||
imx_uart_dma_exit(sport);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void imx_enable_dma(struct imx_port *sport)
|
||||
{
|
||||
unsigned long temp;
|
||||
struct tty_port *port = &sport->port.state->port;
|
||||
|
||||
port->low_latency = 1;
|
||||
INIT_WORK(&sport->tsk_dma_tx, dma_tx_work);
|
||||
INIT_WORK(&sport->tsk_dma_rx, dma_rx_work);
|
||||
init_waitqueue_head(&sport->dma_wait);
|
||||
|
||||
/* set UCR1 */
|
||||
temp = readl(sport->port.membase + UCR1);
|
||||
temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
|
||||
/* wait for 32 idle frames for IDDMA interrupt */
|
||||
UCR1_ICD_REG(3);
|
||||
writel(temp, sport->port.membase + UCR1);
|
||||
|
||||
/* set UCR4 */
|
||||
temp = readl(sport->port.membase + UCR4);
|
||||
temp |= UCR4_IDDMAEN;
|
||||
writel(temp, sport->port.membase + UCR4);
|
||||
|
||||
sport->dma_is_enabled = 1;
|
||||
}
|
||||
|
||||
static void imx_disable_dma(struct imx_port *sport)
|
||||
{
|
||||
unsigned long temp;
|
||||
struct tty_port *port = &sport->port.state->port;
|
||||
|
||||
/* clear UCR1 */
|
||||
temp = readl(sport->port.membase + UCR1);
|
||||
temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
|
||||
writel(temp, sport->port.membase + UCR1);
|
||||
|
||||
/* clear UCR2 */
|
||||
temp = readl(sport->port.membase + UCR2);
|
||||
temp &= ~(UCR2_CTSC | UCR2_CTS);
|
||||
writel(temp, sport->port.membase + UCR2);
|
||||
|
||||
/* clear UCR4 */
|
||||
temp = readl(sport->port.membase + UCR4);
|
||||
temp &= ~UCR4_IDDMAEN;
|
||||
writel(temp, sport->port.membase + UCR4);
|
||||
|
||||
sport->dma_is_enabled = 0;
|
||||
port->low_latency = 0;
|
||||
}
|
||||
|
||||
/* half the RX buffer size */
|
||||
#define CTSTL 16
|
||||
|
||||
@ -869,6 +1248,15 @@ static void imx_shutdown(struct uart_port *port)
|
||||
unsigned long temp;
|
||||
unsigned long flags;
|
||||
|
||||
if (sport->dma_is_enabled) {
|
||||
/* We have to wait for the DMA to finish. */
|
||||
wait_event(sport->dma_wait,
|
||||
!sport->dma_is_rxing && !sport->dma_is_txing);
|
||||
imx_stop_rx(port);
|
||||
imx_disable_dma(sport);
|
||||
imx_uart_dma_exit(sport);
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&sport->port.lock, flags);
|
||||
temp = readl(sport->port.membase + UCR2);
|
||||
temp &= ~(UCR2_TXEN);
|
||||
@ -955,6 +1343,11 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
|
||||
if (sport->have_rtscts) {
|
||||
ucr2 &= ~UCR2_IRTS;
|
||||
ucr2 |= UCR2_CTSC;
|
||||
|
||||
/* Can we enable the DMA support? */
|
||||
if (is_imx6q_uart(sport) && !uart_console(port)
|
||||
&& !sport->dma_is_inited)
|
||||
imx_uart_dma_init(sport);
|
||||
} else {
|
||||
termios->c_cflag &= ~CRTSCTS;
|
||||
}
|
||||
@ -1073,6 +1466,8 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
|
||||
if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
|
||||
imx_enable_ms(&sport->port);
|
||||
|
||||
if (sport->dma_is_inited && !sport->dma_is_enabled)
|
||||
imx_enable_dma(sport);
|
||||
spin_unlock_irqrestore(&sport->port.lock, flags);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user