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drm/sti: remove stih415-416 platform support
stih415 and stih416 platform are obsolete and no more supported. Only stih407 and stih410 platform are maintained. Signed-off-by: Vincent Abriou <vincent.abriou@st.com> Acked-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org>
This commit is contained in:
Vincent Abriou
parent
38fdb8d95f
commit
b4bba92dfb
@ -1,6 +1,6 @@
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config DRM_STI
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tristate "DRM Support for STMicroelectronics SoC stiH41x Series"
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depends on DRM && (SOC_STIH415 || SOC_STIH416 || ARCH_MULTIPLATFORM)
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tristate "DRM Support for STMicroelectronics SoC stiH4xx Series"
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depends on DRM && (ARCH_STI || ARCH_MULTIPLATFORM)
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select RESET_CONTROLLER
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select DRM_KMS_HELPER
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select DRM_GEM_CMA_HELPER
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@ -9,4 +9,4 @@ config DRM_STI
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select FW_LOADER
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select SND_SOC_HDMI_CODEC if SND_SOC
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help
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Choose this option to enable DRM on STM stiH41x chipset
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Choose this option to enable DRM on STM stiH4xx chipset
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@ -9,7 +9,6 @@ sti-drm-y := \
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sti_crtc.o \
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sti_plane.o \
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sti_hdmi.o \
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sti_hdmi_tx3g0c55phy.o \
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sti_hdmi_tx3g4c28phy.o \
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sti_dvo.o \
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sti_awg_utils.o \
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@ -39,22 +39,6 @@ static const struct sti_compositor_data stih407_compositor_data = {
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},
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};
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/*
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* stiH416 compositor properties
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* Note:
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* on stih416 MIXER_AUX has a different base address from MIXER_MAIN
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* Moreover, GDPx is different for Main and Aux Mixer. So this subdev map does
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* not fit for stiH416 if we want to enable the MIXER_AUX.
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*/
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static const struct sti_compositor_data stih416_compositor_data = {
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.nb_subdev = 3,
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.subdev_desc = {
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{STI_GPD_SUBDEV, (int)STI_GDP_0, 0x100},
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{STI_GPD_SUBDEV, (int)STI_GDP_1, 0x200},
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{STI_MIXER_MAIN_SUBDEV, STI_MIXER_MAIN, 0xC00}
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},
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};
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int sti_compositor_debugfs_init(struct sti_compositor *compo,
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struct drm_minor *minor)
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{
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@ -179,9 +163,6 @@ static const struct component_ops sti_compositor_ops = {
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static const struct of_device_id compositor_of_match[] = {
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{
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.compatible = "st,stih416-compositor",
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.data = &stih416_compositor_data,
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}, {
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.compatible = "st,stih407-compositor",
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.data = &stih407_compositor_data,
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}, {
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@ -62,14 +62,8 @@
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#define SCALE_CTRL_CR_DFLT 0x00DB0249
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/* Video DACs control */
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#define VIDEO_DACS_CONTROL_MASK 0x0FFF
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#define VIDEO_DACS_CONTROL_SYSCFG2535 0x085C /* for stih416 */
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#define DAC_CFG_HD_OFF_SHIFT 5
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#define DAC_CFG_HD_OFF_MASK (0x7 << DAC_CFG_HD_OFF_SHIFT)
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#define VIDEO_DACS_CONTROL_SYSCFG5072 0x0120 /* for stih407 */
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#define DAC_CFG_HD_HZUVW_OFF_MASK BIT(1)
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/* Upsampler values for the alternative 2X Filter */
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#define SAMPLER_COEF_NB 8
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#define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000
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@ -300,28 +294,14 @@ static bool hda_get_mode_idx(struct drm_display_mode mode, int *idx)
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*/
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static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable)
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{
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u32 mask;
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if (hda->video_dacs_ctrl) {
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u32 val;
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switch ((u32)hda->video_dacs_ctrl & VIDEO_DACS_CONTROL_MASK) {
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case VIDEO_DACS_CONTROL_SYSCFG2535:
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mask = DAC_CFG_HD_OFF_MASK;
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break;
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case VIDEO_DACS_CONTROL_SYSCFG5072:
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mask = DAC_CFG_HD_HZUVW_OFF_MASK;
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break;
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default:
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DRM_INFO("Video DACS control register not supported\n");
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return;
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}
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val = readl(hda->video_dacs_ctrl);
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if (enable)
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val &= ~mask;
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val &= ~DAC_CFG_HD_HZUVW_OFF_MASK;
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else
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val |= mask;
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val |= DAC_CFG_HD_HZUVW_OFF_MASK;
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writel(val, hda->video_dacs_ctrl);
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}
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@ -352,24 +332,11 @@ static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg)
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static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg)
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{
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u32 val = readl(reg);
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u32 mask;
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switch ((u32)reg & VIDEO_DACS_CONTROL_MASK) {
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case VIDEO_DACS_CONTROL_SYSCFG2535:
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mask = DAC_CFG_HD_OFF_MASK;
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break;
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case VIDEO_DACS_CONTROL_SYSCFG5072:
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mask = DAC_CFG_HD_HZUVW_OFF_MASK;
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break;
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default:
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DRM_DEBUG_DRIVER("Warning: DACS ctrl register not supported\n");
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return;
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}
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seq_puts(s, "\n");
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seq_printf(s, "\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val);
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seq_puts(s, "\tHD DACs ");
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seq_puts(s, val & mask ? "disabled" : "enabled");
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seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled");
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}
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static int hda_dbg_show(struct seq_file *s, void *data)
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@ -22,7 +22,6 @@
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#include "sti_hdmi.h"
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#include "sti_hdmi_tx3g4c28phy.h"
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#include "sti_hdmi_tx3g0c55phy.h"
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#include "sti_vtg.h"
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#define HDMI_CFG 0x0000
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@ -1374,9 +1373,6 @@ static const struct component_ops sti_hdmi_ops = {
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static const struct of_device_id hdmi_of_match[] = {
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{
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.compatible = "st,stih416-hdmi",
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.data = &tx3g0c55phy_ops,
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}, {
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.compatible = "st,stih407-hdmi",
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.data = &tx3g4c28phy_ops,
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}, {
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@ -1423,22 +1419,6 @@ static int sti_hdmi_probe(struct platform_device *pdev)
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goto release_adapter;
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}
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if (of_device_is_compatible(np, "st,stih416-hdmi")) {
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"syscfg");
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if (!res) {
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DRM_ERROR("Invalid syscfg resource\n");
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ret = -ENOMEM;
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goto release_adapter;
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}
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hdmi->syscfg = devm_ioremap_nocache(dev, res->start,
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resource_size(res));
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if (!hdmi->syscfg) {
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ret = -ENOMEM;
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goto release_adapter;
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}
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}
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hdmi->phy_ops = (struct hdmi_phy_ops *)
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of_match_node(hdmi_of_match, np)->data;
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@ -1,336 +0,0 @@
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/*
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* Copyright (C) STMicroelectronics SA 2014
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* Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include "sti_hdmi_tx3g0c55phy.h"
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#define HDMI_SRZ_PLL_CFG 0x0504
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#define HDMI_SRZ_TAP_1 0x0508
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#define HDMI_SRZ_TAP_2 0x050C
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#define HDMI_SRZ_TAP_3 0x0510
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#define HDMI_SRZ_CTRL 0x0514
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#define HDMI_SRZ_PLL_CFG_POWER_DOWN BIT(0)
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#define HDMI_SRZ_PLL_CFG_VCOR_SHIFT 1
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#define HDMI_SRZ_PLL_CFG_VCOR_425MHZ 0
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#define HDMI_SRZ_PLL_CFG_VCOR_850MHZ 1
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#define HDMI_SRZ_PLL_CFG_VCOR_1700MHZ 2
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#define HDMI_SRZ_PLL_CFG_VCOR_3000MHZ 3
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#define HDMI_SRZ_PLL_CFG_VCOR_MASK 3
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#define HDMI_SRZ_PLL_CFG_VCOR(x) (x << HDMI_SRZ_PLL_CFG_VCOR_SHIFT)
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#define HDMI_SRZ_PLL_CFG_NDIV_SHIFT 8
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#define HDMI_SRZ_PLL_CFG_NDIV_MASK (0x1F << HDMI_SRZ_PLL_CFG_NDIV_SHIFT)
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#define HDMI_SRZ_PLL_CFG_MODE_SHIFT 16
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#define HDMI_SRZ_PLL_CFG_MODE_13_5_MHZ 0x1
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#define HDMI_SRZ_PLL_CFG_MODE_25_2_MHZ 0x4
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#define HDMI_SRZ_PLL_CFG_MODE_27_MHZ 0x5
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#define HDMI_SRZ_PLL_CFG_MODE_33_75_MHZ 0x6
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#define HDMI_SRZ_PLL_CFG_MODE_40_5_MHZ 0x7
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#define HDMI_SRZ_PLL_CFG_MODE_54_MHZ 0x8
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#define HDMI_SRZ_PLL_CFG_MODE_67_5_MHZ 0x9
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#define HDMI_SRZ_PLL_CFG_MODE_74_25_MHZ 0xA
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#define HDMI_SRZ_PLL_CFG_MODE_81_MHZ 0xB
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#define HDMI_SRZ_PLL_CFG_MODE_82_5_MHZ 0xC
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#define HDMI_SRZ_PLL_CFG_MODE_108_MHZ 0xD
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#define HDMI_SRZ_PLL_CFG_MODE_148_5_MHZ 0xE
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#define HDMI_SRZ_PLL_CFG_MODE_165_MHZ 0xF
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#define HDMI_SRZ_PLL_CFG_MODE_MASK 0xF
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#define HDMI_SRZ_PLL_CFG_MODE(x) (x << HDMI_SRZ_PLL_CFG_MODE_SHIFT)
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#define HDMI_SRZ_CTRL_POWER_DOWN (1 << 0)
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#define HDMI_SRZ_CTRL_EXTERNAL_DATA_EN (1 << 1)
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/* sysconf registers */
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#define HDMI_REJECTION_PLL_CONFIGURATION 0x0858 /* SYSTEM_CONFIG2534 */
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#define HDMI_REJECTION_PLL_STATUS 0x0948 /* SYSTEM_CONFIG2594 */
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#define REJECTION_PLL_HDMI_ENABLE_SHIFT 0
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#define REJECTION_PLL_HDMI_ENABLE_MASK (0x1 << REJECTION_PLL_HDMI_ENABLE_SHIFT)
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#define REJECTION_PLL_HDMI_PDIV_SHIFT 24
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#define REJECTION_PLL_HDMI_PDIV_MASK (0x7 << REJECTION_PLL_HDMI_PDIV_SHIFT)
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#define REJECTION_PLL_HDMI_NDIV_SHIFT 16
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#define REJECTION_PLL_HDMI_NDIV_MASK (0xFF << REJECTION_PLL_HDMI_NDIV_SHIFT)
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#define REJECTION_PLL_HDMI_MDIV_SHIFT 8
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#define REJECTION_PLL_HDMI_MDIV_MASK (0xFF << REJECTION_PLL_HDMI_MDIV_SHIFT)
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#define REJECTION_PLL_HDMI_REJ_PLL_LOCK BIT(0)
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#define HDMI_TIMEOUT_PLL_LOCK 50 /*milliseconds */
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/**
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* pll mode structure
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*
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* A pointer to an array of these structures is passed to a TMDS (HDMI) output
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* via the control interface to provide board and SoC specific
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* configurations of the HDMI PHY. Each entry in the array specifies a hardware
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* specific configuration for a given TMDS clock frequency range. The array
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* should be terminated with an entry that has all fields set to zero.
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*
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* @min: Lower bound of TMDS clock frequency this entry applies to
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* @max: Upper bound of TMDS clock frequency this entry applies to
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* @mode: SoC specific register configuration
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*/
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struct pllmode {
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u32 min;
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u32 max;
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u32 mode;
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};
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#define NB_PLL_MODE 7
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static struct pllmode pllmodes[NB_PLL_MODE] = {
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{13500000, 13513500, HDMI_SRZ_PLL_CFG_MODE_13_5_MHZ},
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{25174800, 25200000, HDMI_SRZ_PLL_CFG_MODE_25_2_MHZ},
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{27000000, 27027000, HDMI_SRZ_PLL_CFG_MODE_27_MHZ},
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{54000000, 54054000, HDMI_SRZ_PLL_CFG_MODE_54_MHZ},
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{72000000, 74250000, HDMI_SRZ_PLL_CFG_MODE_74_25_MHZ},
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{108000000, 108108000, HDMI_SRZ_PLL_CFG_MODE_108_MHZ},
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{148351648, 297000000, HDMI_SRZ_PLL_CFG_MODE_148_5_MHZ}
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};
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#define NB_HDMI_PHY_CONFIG 5
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static struct hdmi_phy_config hdmiphy_config[NB_HDMI_PHY_CONFIG] = {
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{0, 40000000, {0x00101010, 0x00101010, 0x00101010, 0x02} },
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{40000000, 140000000, {0x00111111, 0x00111111, 0x00111111, 0x02} },
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{140000000, 160000000, {0x00131313, 0x00101010, 0x00101010, 0x02} },
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{160000000, 250000000, {0x00131313, 0x00111111, 0x00111111, 0x03FE} },
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{250000000, 300000000, {0x00151515, 0x00101010, 0x00101010, 0x03FE} },
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};
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#define PLL_CHANGE_DELAY 1 /* ms */
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/**
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* Disable the pll rejection
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*
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* @hdmi: pointer on the hdmi internal structure
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*
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* return true if the pll has been disabled
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*/
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static bool disable_pll_rejection(struct sti_hdmi *hdmi)
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{
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u32 val;
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DRM_DEBUG_DRIVER("\n");
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val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
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val &= ~REJECTION_PLL_HDMI_ENABLE_MASK;
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writel(val, hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
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msleep(PLL_CHANGE_DELAY);
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val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_STATUS);
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return !(val & REJECTION_PLL_HDMI_REJ_PLL_LOCK);
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}
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/**
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* Enable the old BCH/rejection PLL is now reused to provide the CLKPXPLL
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* clock input to the new PHY PLL that generates the serializer clock
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* (TMDS*10) and the TMDS clock which is now fed back into the HDMI
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* formatter instead of the TMDS clock line from ClockGenB.
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*
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* @hdmi: pointer on the hdmi internal structure
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*
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* return true if pll has been correctly set
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*/
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static bool enable_pll_rejection(struct sti_hdmi *hdmi)
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{
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unsigned int inputclock;
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u32 mdiv, ndiv, pdiv, val;
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DRM_DEBUG_DRIVER("\n");
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if (!disable_pll_rejection(hdmi))
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return false;
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inputclock = hdmi->mode.clock * 1000;
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DRM_DEBUG_DRIVER("hdmi rejection pll input clock = %dHz\n", inputclock);
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/* Power up the HDMI rejection PLL
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* Note: On this SoC (stiH416) we are forced to have the input clock
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* be equal to the HDMI pixel clock.
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*
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* The values here have been suggested by validation however they are
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* still provisional and subject to change.
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*
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* PLLout = (Fin*Mdiv) / ((2 * Ndiv) / 2^Pdiv)
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*/
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if (inputclock < 50000000) {
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/*
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* For slower clocks we need to multiply more to keep the
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* internal VCO frequency within the physical specification
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* of the PLL.
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*/
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pdiv = 4;
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ndiv = 240;
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mdiv = 30;
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} else {
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pdiv = 2;
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ndiv = 60;
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mdiv = 30;
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}
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val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
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val &= ~(REJECTION_PLL_HDMI_PDIV_MASK |
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REJECTION_PLL_HDMI_NDIV_MASK |
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REJECTION_PLL_HDMI_MDIV_MASK |
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REJECTION_PLL_HDMI_ENABLE_MASK);
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val |= (pdiv << REJECTION_PLL_HDMI_PDIV_SHIFT) |
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(ndiv << REJECTION_PLL_HDMI_NDIV_SHIFT) |
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(mdiv << REJECTION_PLL_HDMI_MDIV_SHIFT) |
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(0x1 << REJECTION_PLL_HDMI_ENABLE_SHIFT);
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writel(val, hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
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msleep(PLL_CHANGE_DELAY);
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val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_STATUS);
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return (val & REJECTION_PLL_HDMI_REJ_PLL_LOCK);
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}
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/**
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* Start hdmi phy macro cell tx3g0c55
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*
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* @hdmi: pointer on the hdmi internal structure
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*
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* Return false if an error occur
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*/
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static bool sti_hdmi_tx3g0c55phy_start(struct sti_hdmi *hdmi)
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{
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u32 ckpxpll = hdmi->mode.clock * 1000;
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u32 val, tmdsck, freqvco, pllctrl = 0;
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unsigned int i;
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if (!enable_pll_rejection(hdmi))
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return false;
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DRM_DEBUG_DRIVER("ckpxpll = %dHz\n", ckpxpll);
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/* Assuming no pixel repetition and 24bits color */
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tmdsck = ckpxpll;
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pllctrl = 2 << HDMI_SRZ_PLL_CFG_NDIV_SHIFT;
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/*
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* Setup the PLL mode parameter based on the ckpxpll. If we haven't got
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* a clock frequency supported by one of the specific PLL modes then we
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* will end up using the generic mode (0) which only supports a 10x
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* multiplier, hence only 24bit color.
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*/
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for (i = 0; i < NB_PLL_MODE; i++) {
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if (ckpxpll >= pllmodes[i].min && ckpxpll <= pllmodes[i].max)
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pllctrl |= HDMI_SRZ_PLL_CFG_MODE(pllmodes[i].mode);
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}
|
||||
|
||||
freqvco = tmdsck * 10;
|
||||
if (freqvco <= 425000000UL)
|
||||
pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_425MHZ);
|
||||
else if (freqvco <= 850000000UL)
|
||||
pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_850MHZ);
|
||||
else if (freqvco <= 1700000000UL)
|
||||
pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_1700MHZ);
|
||||
else if (freqvco <= 2970000000UL)
|
||||
pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_3000MHZ);
|
||||
else {
|
||||
DRM_ERROR("PHY serializer clock out of range\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Configure and power up the PHY PLL
|
||||
*/
|
||||
hdmi->event_received = false;
|
||||
DRM_DEBUG_DRIVER("pllctrl = 0x%x\n", pllctrl);
|
||||
hdmi_write(hdmi, pllctrl, HDMI_SRZ_PLL_CFG);
|
||||
|
||||
/* wait PLL interrupt */
|
||||
wait_event_interruptible_timeout(hdmi->wait_event,
|
||||
hdmi->event_received == true,
|
||||
msecs_to_jiffies
|
||||
(HDMI_TIMEOUT_PLL_LOCK));
|
||||
|
||||
if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) == 0) {
|
||||
DRM_ERROR("hdmi phy pll not locked\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
DRM_DEBUG_DRIVER("got PHY PLL Lock\n");
|
||||
|
||||
/*
|
||||
* To configure the source termination and pre-emphasis appropriately
|
||||
* for different high speed TMDS clock frequencies a phy configuration
|
||||
* table must be provided, tailored to the SoC and board combination.
|
||||
*/
|
||||
for (i = 0; i < NB_HDMI_PHY_CONFIG; i++) {
|
||||
if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) &&
|
||||
(hdmiphy_config[i].max_tmds_freq >= tmdsck)) {
|
||||
val = hdmiphy_config[i].config[0];
|
||||
hdmi_write(hdmi, val, HDMI_SRZ_TAP_1);
|
||||
val = hdmiphy_config[i].config[1];
|
||||
hdmi_write(hdmi, val, HDMI_SRZ_TAP_2);
|
||||
val = hdmiphy_config[i].config[2];
|
||||
hdmi_write(hdmi, val, HDMI_SRZ_TAP_3);
|
||||
val = hdmiphy_config[i].config[3];
|
||||
val |= HDMI_SRZ_CTRL_EXTERNAL_DATA_EN;
|
||||
val &= ~HDMI_SRZ_CTRL_POWER_DOWN;
|
||||
hdmi_write(hdmi, val, HDMI_SRZ_CTRL);
|
||||
|
||||
DRM_DEBUG_DRIVER("serializer cfg 0x%x 0x%x 0x%x 0x%x\n",
|
||||
hdmiphy_config[i].config[0],
|
||||
hdmiphy_config[i].config[1],
|
||||
hdmiphy_config[i].config[2],
|
||||
hdmiphy_config[i].config[3]);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Default, power up the serializer with no pre-emphasis or source
|
||||
* termination.
|
||||
*/
|
||||
hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_1);
|
||||
hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_2);
|
||||
hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_3);
|
||||
hdmi_write(hdmi, HDMI_SRZ_CTRL_EXTERNAL_DATA_EN, HDMI_SRZ_CTRL);
|
||||
|
||||
return true;
|
||||
|
||||
err:
|
||||
disable_pll_rejection(hdmi);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* Stop hdmi phy macro cell tx3g0c55
|
||||
*
|
||||
* @hdmi: pointer on the hdmi internal structure
|
||||
*/
|
||||
static void sti_hdmi_tx3g0c55phy_stop(struct sti_hdmi *hdmi)
|
||||
{
|
||||
DRM_DEBUG_DRIVER("\n");
|
||||
|
||||
hdmi->event_received = false;
|
||||
|
||||
hdmi_write(hdmi, HDMI_SRZ_CTRL_POWER_DOWN, HDMI_SRZ_CTRL);
|
||||
hdmi_write(hdmi, HDMI_SRZ_PLL_CFG_POWER_DOWN, HDMI_SRZ_PLL_CFG);
|
||||
|
||||
/* wait PLL interrupt */
|
||||
wait_event_interruptible_timeout(hdmi->wait_event,
|
||||
hdmi->event_received == true,
|
||||
msecs_to_jiffies
|
||||
(HDMI_TIMEOUT_PLL_LOCK));
|
||||
|
||||
if (hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK)
|
||||
DRM_ERROR("hdmi phy pll not well disabled\n");
|
||||
|
||||
disable_pll_rejection(hdmi);
|
||||
}
|
||||
|
||||
struct hdmi_phy_ops tx3g0c55phy_ops = {
|
||||
.start = sti_hdmi_tx3g0c55phy_start,
|
||||
.stop = sti_hdmi_tx3g0c55phy_stop,
|
||||
};
|
||||
@ -1,14 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics SA 2014
|
||||
* Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
|
||||
* License terms: GNU General Public License (GPL), version 2
|
||||
*/
|
||||
|
||||
#ifndef _STI_HDMI_TX3G0C55PHY_H_
|
||||
#define _STI_HDMI_TX3G0C55PHY_H_
|
||||
|
||||
#include "sti_hdmi.h"
|
||||
|
||||
extern struct hdmi_phy_ops tx3g0c55phy_ops;
|
||||
|
||||
#endif
|
||||
@ -16,12 +16,6 @@ static unsigned int bkg_color = 0x000000;
|
||||
MODULE_PARM_DESC(bkgcolor, "Value of the background color 0xRRGGBB");
|
||||
module_param_named(bkgcolor, bkg_color, int, 0644);
|
||||
|
||||
/* Identity: G=Y , B=Cb , R=Cr */
|
||||
static const u32 mixerColorSpaceMatIdentity[] = {
|
||||
0x10000000, 0x00000000, 0x10000000, 0x00001000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000
|
||||
};
|
||||
|
||||
/* regs offset */
|
||||
#define GAM_MIXER_CTL 0x00
|
||||
#define GAM_MIXER_BKC 0x04
|
||||
@ -358,22 +352,12 @@ int sti_mixer_set_plane_status(struct sti_mixer *mixer,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sti_mixer_set_matrix(struct sti_mixer *mixer)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
|
||||
sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
|
||||
mixerColorSpaceMatIdentity[i]);
|
||||
}
|
||||
|
||||
struct sti_mixer *sti_mixer_create(struct device *dev,
|
||||
struct drm_device *drm_dev,
|
||||
int id,
|
||||
void __iomem *baseaddr)
|
||||
{
|
||||
struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
|
||||
struct device_node *np = dev->of_node;
|
||||
|
||||
dev_dbg(dev, "%s\n", __func__);
|
||||
if (!mixer) {
|
||||
@ -384,9 +368,6 @@ struct sti_mixer *sti_mixer_create(struct device *dev,
|
||||
mixer->dev = dev;
|
||||
mixer->id = id;
|
||||
|
||||
if (of_device_is_compatible(np, "st,stih416-compositor"))
|
||||
sti_mixer_set_matrix(mixer);
|
||||
|
||||
DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
|
||||
sti_mixer_to_str(mixer), mixer->regs);
|
||||
|
||||
|
||||
@ -210,13 +210,11 @@ static void tvout_vip_set_rnd(struct sti_tvout *tvout, int reg, u32 rnd)
|
||||
* @tvout: tvout structure
|
||||
* @reg: register to set
|
||||
* @main_path: main or auxiliary path
|
||||
* @sel_input_logic_inverted: need to invert the logic
|
||||
* @sel_input: selected_input (main/aux + conv)
|
||||
*/
|
||||
static void tvout_vip_set_sel_input(struct sti_tvout *tvout,
|
||||
int reg,
|
||||
bool main_path,
|
||||
bool sel_input_logic_inverted,
|
||||
enum sti_tvout_video_out_type video_out)
|
||||
{
|
||||
u32 sel_input;
|
||||
@ -237,8 +235,7 @@ static void tvout_vip_set_sel_input(struct sti_tvout *tvout,
|
||||
}
|
||||
|
||||
/* on stih407 chip the sel_input bypass mode logic is inverted */
|
||||
if (sel_input_logic_inverted)
|
||||
sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK;
|
||||
sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK;
|
||||
|
||||
val &= ~TVO_VIP_SEL_INPUT_MASK;
|
||||
val |= sel_input;
|
||||
@ -296,8 +293,6 @@ static void tvout_preformatter_set_matrix(struct sti_tvout *tvout,
|
||||
*/
|
||||
static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path)
|
||||
{
|
||||
struct device_node *node = tvout->dev->of_node;
|
||||
bool sel_input_logic_inverted = false;
|
||||
u32 tvo_in_vid_format;
|
||||
int val, tmp;
|
||||
|
||||
@ -335,16 +330,11 @@ static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path)
|
||||
/* Set round mode (rounded to 8-bit per component) */
|
||||
tvout_vip_set_rnd(tvout, TVO_VIP_DVO, TVO_VIP_RND_8BIT_ROUNDED);
|
||||
|
||||
if (of_device_is_compatible(node, "st,stih407-tvout")) {
|
||||
/* Set input video format */
|
||||
tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format,
|
||||
TVO_IN_FMT_SIGNED);
|
||||
sel_input_logic_inverted = true;
|
||||
}
|
||||
/* Set input video format */
|
||||
tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
|
||||
|
||||
/* Input selection */
|
||||
tvout_vip_set_sel_input(tvout, TVO_VIP_DVO, main_path,
|
||||
sel_input_logic_inverted,
|
||||
STI_TVOUT_VIDEO_OUT_RGB);
|
||||
}
|
||||
|
||||
@ -357,8 +347,6 @@ static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path)
|
||||
*/
|
||||
static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
|
||||
{
|
||||
struct device_node *node = tvout->dev->of_node;
|
||||
bool sel_input_logic_inverted = false;
|
||||
u32 tvo_in_vid_format;
|
||||
|
||||
dev_dbg(tvout->dev, "%s\n", __func__);
|
||||
@ -391,16 +379,12 @@ static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
|
||||
/* set round mode (rounded to 8-bit per component) */
|
||||
tvout_vip_set_rnd(tvout, TVO_VIP_HDMI, TVO_VIP_RND_8BIT_ROUNDED);
|
||||
|
||||
if (of_device_is_compatible(node, "st,stih407-tvout")) {
|
||||
/* set input video format */
|
||||
tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format,
|
||||
TVO_IN_FMT_SIGNED);
|
||||
sel_input_logic_inverted = true;
|
||||
}
|
||||
/* set input video format */
|
||||
tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
|
||||
|
||||
/* input selection */
|
||||
tvout_vip_set_sel_input(tvout, TVO_VIP_HDMI, main_path,
|
||||
sel_input_logic_inverted, STI_TVOUT_VIDEO_OUT_RGB);
|
||||
STI_TVOUT_VIDEO_OUT_RGB);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -412,8 +396,6 @@ static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
|
||||
*/
|
||||
static void tvout_hda_start(struct sti_tvout *tvout, bool main_path)
|
||||
{
|
||||
struct device_node *node = tvout->dev->of_node;
|
||||
bool sel_input_logic_inverted = false;
|
||||
u32 tvo_in_vid_format;
|
||||
int val;
|
||||
|
||||
@ -449,16 +431,11 @@ static void tvout_hda_start(struct sti_tvout *tvout, bool main_path)
|
||||
/* set round mode (rounded to 10-bit per component) */
|
||||
tvout_vip_set_rnd(tvout, TVO_VIP_HDF, TVO_VIP_RND_10BIT_ROUNDED);
|
||||
|
||||
if (of_device_is_compatible(node, "st,stih407-tvout")) {
|
||||
/* set input video format */
|
||||
tvout_vip_set_in_vid_fmt(tvout,
|
||||
tvo_in_vid_format, TVO_IN_FMT_SIGNED);
|
||||
sel_input_logic_inverted = true;
|
||||
}
|
||||
/* Set input video format */
|
||||
tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
|
||||
|
||||
/* Input selection */
|
||||
tvout_vip_set_sel_input(tvout, TVO_VIP_HDF, main_path,
|
||||
sel_input_logic_inverted,
|
||||
STI_TVOUT_VIDEO_OUT_YUV);
|
||||
|
||||
/* power up HD DAC */
|
||||
@ -906,7 +883,6 @@ static int sti_tvout_remove(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
static const struct of_device_id tvout_of_match[] = {
|
||||
{ .compatible = "st,stih416-tvout", },
|
||||
{ .compatible = "st,stih407-tvout", },
|
||||
{ /* end node */ }
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user