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Microblaze patches for 3.15-rc1
- Use asm-generic/io.h and fix intc/timer code - Clean platform handling - Enable some syscalls -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iEYEABECAAYFAlNHiDIACgkQykllyylKDCHbLgCggWXqrfHFULZqlTUfAV2krfsx q44AoJ5sI0rBHEtXnL8Clo5+4vpftv0G =CRLR -----END PGP SIGNATURE----- Merge tag 'microblaze-3.15-rc1' of git://git.monstr.eu/linux-2.6-microblaze Pull Microblaze updates from Michal Simek: - use asm-generic/io.h and fix intc/timer code - clean platform handling - enable some syscalls * tag 'microblaze-3.15-rc1' of git://git.monstr.eu/linux-2.6-microblaze: microblaze: Use asm-generic/io.h microblaze: Remove platform folder microblaze: Remove generic platform microblaze: Sort Kconfig options microblaze: Move DTS file to common location at boot/dts folder microblaze: Fix compilation failure because of release_thread microblaze: Fix sparse warning because of missing cpu.h header microblaze: Make timer driver endian aware microblaze: Make intc driver endian aware microblaze: Wire-up new system calls sched_setattr/getattr microblaze: Wire-up preadv/pwritev in syscall table microblaze: Enable pselect6 syscall microblaze: Drop architecture-specific declaration of early_printk microblaze: Rename global function heartbeat()
This commit is contained in:
Linus Torvalds
commit
b42e6dc66b
@ -1,38 +1,38 @@
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config MICROBLAZE
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def_bool y
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select ARCH_MIGHT_HAVE_PC_PARPORT
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select HAVE_MEMBLOCK
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select HAVE_MEMBLOCK_NODE_MAP
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select HAVE_FUNCTION_TRACER
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select HAVE_FUNCTION_TRACE_MCOUNT_TEST
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select HAVE_FUNCTION_GRAPH_TRACER
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select HAVE_DYNAMIC_FTRACE
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select HAVE_FTRACE_MCOUNT_RECORD
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select HAVE_OPROFILE
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select HAVE_ARCH_KGDB
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select HAVE_DMA_ATTRS
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select HAVE_DMA_API_DEBUG
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select TRACING_SUPPORT
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select OF
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select OF_EARLY_FLATTREE
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select ARCH_WANT_IPC_PARSE_VERSION
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select HAVE_DEBUG_KMEMLEAK
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select IRQ_DOMAIN
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select VIRT_TO_BUS
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select BUILDTIME_EXTABLE_SORT
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select CLKSRC_OF
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select CLONE_BACKWARDS3
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select COMMON_CLK
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select GENERIC_ATOMIC64
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select GENERIC_CLOCKEVENTS
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select GENERIC_CPU_DEVICES
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select GENERIC_IDLE_POLL_SETUP
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select GENERIC_IRQ_PROBE
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select GENERIC_IRQ_SHOW
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select GENERIC_PCI_IOMAP
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select GENERIC_CPU_DEVICES
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select GENERIC_ATOMIC64
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select GENERIC_CLOCKEVENTS
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select COMMON_CLK
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select GENERIC_SCHED_CLOCK
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select GENERIC_IDLE_POLL_SETUP
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select HAVE_ARCH_KGDB
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select HAVE_DEBUG_KMEMLEAK
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select HAVE_DMA_API_DEBUG
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select HAVE_DMA_ATTRS
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select HAVE_DYNAMIC_FTRACE
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select HAVE_FTRACE_MCOUNT_RECORD
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select HAVE_FUNCTION_GRAPH_TRACER
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select HAVE_FUNCTION_TRACE_MCOUNT_TEST
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select HAVE_FUNCTION_TRACER
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select HAVE_MEMBLOCK
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select HAVE_MEMBLOCK_NODE_MAP
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select HAVE_OPROFILE
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select IRQ_DOMAIN
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select MODULES_USE_ELF_RELA
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select CLONE_BACKWARDS3
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select CLKSRC_OF
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select BUILDTIME_EXTABLE_SORT
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select OF
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select OF_EARLY_FLATTREE
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select TRACING_SUPPORT
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select VIRT_TO_BUS
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config SWAP
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def_bool n
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@ -74,7 +74,7 @@ source "init/Kconfig"
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source "kernel/Kconfig.freezer"
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source "arch/microblaze/platform/Kconfig.platform"
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source "arch/microblaze/Kconfig.platform"
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menu "Processor type and features"
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@ -5,18 +5,6 @@
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#
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menu "Platform options"
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choice
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prompt "Platform"
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default PLATFORM_MICROBLAZE_AUTO
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help
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Choose which hardware board/platform you are targeting.
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config PLATFORM_GENERIC
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bool "Generic"
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help
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Choose this option for the Generic platform.
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endchoice
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config OPT_LIB_FUNCTION
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bool "Optimalized lib function"
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@ -37,8 +25,45 @@ config OPT_LIB_ASM
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Allows turn on optimalized library function (memcpy and memmove).
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Function are written in asm code.
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if PLATFORM_GENERIC=y
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source "arch/microblaze/platform/generic/Kconfig.auto"
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endif
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# Definitions for MICROBLAZE0
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comment "Definitions for MICROBLAZE0"
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config KERNEL_BASE_ADDR
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hex "Physical address where Linux Kernel is"
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default "0x90000000"
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help
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BASE Address for kernel
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config XILINX_MICROBLAZE0_FAMILY
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string "Targeted FPGA family"
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default "virtex5"
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config XILINX_MICROBLAZE0_USE_MSR_INSTR
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int "USE_MSR_INSTR range (0:1)"
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default 0
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config XILINX_MICROBLAZE0_USE_PCMP_INSTR
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int "USE_PCMP_INSTR range (0:1)"
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default 0
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config XILINX_MICROBLAZE0_USE_BARREL
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int "USE_BARREL range (0:1)"
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default 0
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config XILINX_MICROBLAZE0_USE_DIV
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int "USE_DIV range (0:1)"
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default 0
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config XILINX_MICROBLAZE0_USE_HW_MUL
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int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
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default 0
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config XILINX_MICROBLAZE0_USE_FPU
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int "USE_FPU values (0=NONE, 1=BASIC, 2=EXTENDED)"
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default 0
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config XILINX_MICROBLAZE0_HW_VER
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string "Core version number"
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default 7.10.d
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endmenu
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@ -48,7 +48,6 @@ head-y := arch/microblaze/kernel/head.o
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libs-y += arch/microblaze/lib/
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core-y += arch/microblaze/kernel/
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core-y += arch/microblaze/mm/
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core-y += arch/microblaze/platform/
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core-$(CONFIG_PCI) += arch/microblaze/pci/
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drivers-$(CONFIG_OPROFILE) += arch/microblaze/oprofile/
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@ -1 +0,0 @@
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../../platform/generic/system.dts
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366
arch/microblaze/boot/dts/system.dts
Normal file
366
arch/microblaze/boot/dts/system.dts
Normal file
@ -0,0 +1,366 @@
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/*
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* Device Tree Generator version: 1.1
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*
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* (C) Copyright 2007-2008 Xilinx, Inc.
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* (C) Copyright 2007-2009 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* CAUTION: This file is automatically generated by libgen.
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* Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
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*
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* XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,microblaze";
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hard-reset-gpios = <&LEDs_8Bit 2 1>;
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model = "testing";
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DDR2_SDRAM: memory@90000000 {
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device_type = "memory";
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reg = < 0x90000000 0x10000000 >;
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} ;
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aliases {
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ethernet0 = &Hard_Ethernet_MAC;
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serial0 = &RS232_Uart_1;
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} ;
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chosen {
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bootargs = "console=ttyUL0,115200 highres=on";
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linux,stdout-path = "/plb@0/serial@84000000";
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} ;
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cpus {
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#address-cells = <1>;
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#cpus = <0x1>;
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#size-cells = <0>;
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microblaze_0: cpu@0 {
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clock-frequency = <125000000>;
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compatible = "xlnx,microblaze-7.10.d";
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d-cache-baseaddr = <0x90000000>;
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d-cache-highaddr = <0x9fffffff>;
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d-cache-line-size = <0x10>;
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d-cache-size = <0x2000>;
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device_type = "cpu";
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i-cache-baseaddr = <0x90000000>;
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i-cache-highaddr = <0x9fffffff>;
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i-cache-line-size = <0x10>;
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i-cache-size = <0x2000>;
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model = "microblaze,7.10.d";
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reg = <0>;
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timebase-frequency = <125000000>;
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xlnx,addr-tag-bits = <0xf>;
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xlnx,allow-dcache-wr = <0x1>;
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xlnx,allow-icache-wr = <0x1>;
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xlnx,area-optimized = <0x0>;
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xlnx,cache-byte-size = <0x2000>;
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xlnx,d-lmb = <0x1>;
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xlnx,d-opb = <0x0>;
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xlnx,d-plb = <0x1>;
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xlnx,data-size = <0x20>;
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xlnx,dcache-addr-tag = <0xf>;
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xlnx,dcache-always-used = <0x1>;
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xlnx,dcache-byte-size = <0x2000>;
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xlnx,dcache-line-len = <0x4>;
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xlnx,dcache-use-fsl = <0x1>;
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xlnx,debug-enabled = <0x1>;
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xlnx,div-zero-exception = <0x1>;
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xlnx,dopb-bus-exception = <0x0>;
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xlnx,dynamic-bus-sizing = <0x1>;
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xlnx,edge-is-positive = <0x1>;
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xlnx,family = "virtex5";
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xlnx,endianness = <0x1>;
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xlnx,fpu-exception = <0x1>;
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xlnx,fsl-data-size = <0x20>;
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xlnx,fsl-exception = <0x0>;
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xlnx,fsl-links = <0x0>;
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xlnx,i-lmb = <0x1>;
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xlnx,i-opb = <0x0>;
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xlnx,i-plb = <0x1>;
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xlnx,icache-always-used = <0x1>;
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xlnx,icache-line-len = <0x4>;
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xlnx,icache-use-fsl = <0x1>;
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xlnx,ill-opcode-exception = <0x1>;
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xlnx,instance = "microblaze_0";
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xlnx,interconnect = <0x1>;
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xlnx,interrupt-is-edge = <0x0>;
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xlnx,iopb-bus-exception = <0x0>;
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xlnx,mmu-dtlb-size = <0x4>;
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xlnx,mmu-itlb-size = <0x2>;
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xlnx,mmu-tlb-access = <0x3>;
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xlnx,mmu-zones = <0x10>;
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xlnx,number-of-pc-brk = <0x1>;
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xlnx,number-of-rd-addr-brk = <0x0>;
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xlnx,number-of-wr-addr-brk = <0x0>;
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xlnx,opcode-0x0-illegal = <0x1>;
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xlnx,pvr = <0x2>;
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xlnx,pvr-user1 = <0x0>;
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xlnx,pvr-user2 = <0x0>;
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xlnx,reset-msr = <0x0>;
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xlnx,sco = <0x0>;
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xlnx,unaligned-exceptions = <0x1>;
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xlnx,use-barrel = <0x1>;
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xlnx,use-dcache = <0x1>;
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xlnx,use-div = <0x1>;
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xlnx,use-ext-brk = <0x1>;
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xlnx,use-ext-nm-brk = <0x1>;
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xlnx,use-extended-fsl-instr = <0x0>;
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xlnx,use-fpu = <0x2>;
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xlnx,use-hw-mul = <0x2>;
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xlnx,use-icache = <0x1>;
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xlnx,use-interrupt = <0x1>;
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xlnx,use-mmu = <0x3>;
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xlnx,use-msr-instr = <0x1>;
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xlnx,use-pcmp-instr = <0x1>;
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} ;
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} ;
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mb_plb: plb@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
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ranges ;
|
||||
FLASH: flash@a0000000 {
|
||||
bank-width = <2>;
|
||||
compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
|
||||
reg = < 0xa0000000 0x2000000 >;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,include-datawidth-matching-0 = <0x1>;
|
||||
xlnx,include-datawidth-matching-1 = <0x0>;
|
||||
xlnx,include-datawidth-matching-2 = <0x0>;
|
||||
xlnx,include-datawidth-matching-3 = <0x0>;
|
||||
xlnx,include-negedge-ioregs = <0x0>;
|
||||
xlnx,include-plb-ipif = <0x1>;
|
||||
xlnx,include-wrbuf = <0x1>;
|
||||
xlnx,max-mem-width = <0x10>;
|
||||
xlnx,mch-native-dwidth = <0x20>;
|
||||
xlnx,mch-plb-clk-period-ps = <0x1f40>;
|
||||
xlnx,mch-splb-awidth = <0x20>;
|
||||
xlnx,mch0-accessbuf-depth = <0x10>;
|
||||
xlnx,mch0-protocol = <0x0>;
|
||||
xlnx,mch0-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch1-accessbuf-depth = <0x10>;
|
||||
xlnx,mch1-protocol = <0x0>;
|
||||
xlnx,mch1-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch2-accessbuf-depth = <0x10>;
|
||||
xlnx,mch2-protocol = <0x0>;
|
||||
xlnx,mch2-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch3-accessbuf-depth = <0x10>;
|
||||
xlnx,mch3-protocol = <0x0>;
|
||||
xlnx,mch3-rddatabuf-depth = <0x10>;
|
||||
xlnx,mem0-width = <0x10>;
|
||||
xlnx,mem1-width = <0x20>;
|
||||
xlnx,mem2-width = <0x20>;
|
||||
xlnx,mem3-width = <0x20>;
|
||||
xlnx,num-banks-mem = <0x1>;
|
||||
xlnx,num-channels = <0x0>;
|
||||
xlnx,priority-mode = <0x0>;
|
||||
xlnx,synch-mem-0 = <0x0>;
|
||||
xlnx,synch-mem-1 = <0x0>;
|
||||
xlnx,synch-mem-2 = <0x0>;
|
||||
xlnx,synch-mem-3 = <0x0>;
|
||||
xlnx,synch-pipedelay-0 = <0x2>;
|
||||
xlnx,synch-pipedelay-1 = <0x2>;
|
||||
xlnx,synch-pipedelay-2 = <0x2>;
|
||||
xlnx,synch-pipedelay-3 = <0x2>;
|
||||
xlnx,tavdv-ps-mem-0 = <0x1adb0>;
|
||||
xlnx,tavdv-ps-mem-1 = <0x3a98>;
|
||||
xlnx,tavdv-ps-mem-2 = <0x3a98>;
|
||||
xlnx,tavdv-ps-mem-3 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-0 = <0x1adb0>;
|
||||
xlnx,tcedv-ps-mem-1 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-2 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-3 = <0x3a98>;
|
||||
xlnx,thzce-ps-mem-0 = <0x88b8>;
|
||||
xlnx,thzce-ps-mem-1 = <0x1b58>;
|
||||
xlnx,thzce-ps-mem-2 = <0x1b58>;
|
||||
xlnx,thzce-ps-mem-3 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-0 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-1 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-2 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-3 = <0x1b58>;
|
||||
xlnx,tlzwe-ps-mem-0 = <0x88b8>;
|
||||
xlnx,tlzwe-ps-mem-1 = <0x0>;
|
||||
xlnx,tlzwe-ps-mem-2 = <0x0>;
|
||||
xlnx,tlzwe-ps-mem-3 = <0x0>;
|
||||
xlnx,twc-ps-mem-0 = <0x2af8>;
|
||||
xlnx,twc-ps-mem-1 = <0x3a98>;
|
||||
xlnx,twc-ps-mem-2 = <0x3a98>;
|
||||
xlnx,twc-ps-mem-3 = <0x3a98>;
|
||||
xlnx,twp-ps-mem-0 = <0x11170>;
|
||||
xlnx,twp-ps-mem-1 = <0x2ee0>;
|
||||
xlnx,twp-ps-mem-2 = <0x2ee0>;
|
||||
xlnx,twp-ps-mem-3 = <0x2ee0>;
|
||||
xlnx,xcl0-linesize = <0x4>;
|
||||
xlnx,xcl0-writexfer = <0x1>;
|
||||
xlnx,xcl1-linesize = <0x4>;
|
||||
xlnx,xcl1-writexfer = <0x1>;
|
||||
xlnx,xcl2-linesize = <0x4>;
|
||||
xlnx,xcl2-writexfer = <0x1>;
|
||||
xlnx,xcl3-linesize = <0x4>;
|
||||
xlnx,xcl3-writexfer = <0x1>;
|
||||
} ;
|
||||
Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,compound";
|
||||
ranges ;
|
||||
ethernet@81c00000 {
|
||||
compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 5 2 >;
|
||||
llink-connected = <&PIM3>;
|
||||
local-mac-address = [ 00 0a 35 00 00 00 ];
|
||||
reg = < 0x81c00000 0x40 >;
|
||||
xlnx,bus2core-clk-ratio = <0x1>;
|
||||
xlnx,phy-type = <0x1>;
|
||||
xlnx,phyaddr = <0x1>;
|
||||
xlnx,rxcsum = <0x0>;
|
||||
xlnx,rxfifo = <0x1000>;
|
||||
xlnx,temac-type = <0x0>;
|
||||
xlnx,txcsum = <0x0>;
|
||||
xlnx,txfifo = <0x1000>;
|
||||
} ;
|
||||
} ;
|
||||
IIC_EEPROM: i2c@81600000 {
|
||||
compatible = "xlnx,xps-iic-2.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 6 2 >;
|
||||
reg = < 0x81600000 0x10000 >;
|
||||
xlnx,clk-freq = <0x7735940>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gpo-width = <0x1>;
|
||||
xlnx,iic-freq = <0x186a0>;
|
||||
xlnx,scl-inertial-delay = <0x0>;
|
||||
xlnx,sda-inertial-delay = <0x0>;
|
||||
xlnx,ten-bit-adr = <0x0>;
|
||||
} ;
|
||||
LEDs_8Bit: gpio@81400000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 7 2 >;
|
||||
reg = < 0x81400000 0x10000 >;
|
||||
xlnx,all-inputs = <0x0>;
|
||||
xlnx,all-inputs-2 = <0x0>;
|
||||
xlnx,dout-default = <0x0>;
|
||||
xlnx,dout-default-2 = <0x0>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gpio-width = <0x8>;
|
||||
xlnx,interrupt-present = <0x1>;
|
||||
xlnx,is-bidir = <0x1>;
|
||||
xlnx,is-bidir-2 = <0x1>;
|
||||
xlnx,is-dual = <0x0>;
|
||||
xlnx,tri-default = <0xffffffff>;
|
||||
xlnx,tri-default-2 = <0xffffffff>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
} ;
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
heartbeat {
|
||||
label = "Heartbeat";
|
||||
gpios = <&LEDs_8Bit 4 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
yellow {
|
||||
label = "Yellow";
|
||||
gpios = <&LEDs_8Bit 5 1>;
|
||||
};
|
||||
|
||||
red {
|
||||
label = "Red";
|
||||
gpios = <&LEDs_8Bit 6 1>;
|
||||
};
|
||||
|
||||
green {
|
||||
label = "Green";
|
||||
gpios = <&LEDs_8Bit 7 1>;
|
||||
};
|
||||
} ;
|
||||
RS232_Uart_1: serial@84000000 {
|
||||
clock-frequency = <125000000>;
|
||||
compatible = "xlnx,xps-uartlite-1.00.a";
|
||||
current-speed = <115200>;
|
||||
device_type = "serial";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 8 0 >;
|
||||
port-number = <0>;
|
||||
reg = < 0x84000000 0x10000 >;
|
||||
xlnx,baudrate = <0x1c200>;
|
||||
xlnx,data-bits = <0x8>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,odd-parity = <0x0>;
|
||||
xlnx,use-parity = <0x0>;
|
||||
} ;
|
||||
SysACE_CompactFlash: sysace@83600000 {
|
||||
compatible = "xlnx,xps-sysace-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 4 2 >;
|
||||
reg = < 0x83600000 0x10000 >;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,mem-width = <0x10>;
|
||||
} ;
|
||||
debug_module: debug@84400000 {
|
||||
compatible = "xlnx,mdm-1.00.d";
|
||||
reg = < 0x84400000 0x10000 >;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,interconnect = <0x1>;
|
||||
xlnx,jtag-chain = <0x2>;
|
||||
xlnx,mb-dbg-ports = <0x1>;
|
||||
xlnx,uart-width = <0x8>;
|
||||
xlnx,use-uart = <0x1>;
|
||||
xlnx,write-fsl-ports = <0x0>;
|
||||
} ;
|
||||
mpmc@90000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,mpmc-4.02.a";
|
||||
ranges ;
|
||||
PIM3: sdma@84600180 {
|
||||
compatible = "xlnx,ll-dma-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 2 2 1 2 >;
|
||||
reg = < 0x84600180 0x80 >;
|
||||
} ;
|
||||
} ;
|
||||
xps_intc_0: interrupt-controller@81800000 {
|
||||
#interrupt-cells = <0x2>;
|
||||
compatible = "xlnx,xps-intc-1.00.a";
|
||||
interrupt-controller ;
|
||||
reg = < 0x81800000 0x10000 >;
|
||||
xlnx,kind-of-intr = <0x100>;
|
||||
xlnx,num-intr-inputs = <0x9>;
|
||||
} ;
|
||||
xps_timer_1: timer@83c00000 {
|
||||
compatible = "xlnx,xps-timer-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 3 2 >;
|
||||
reg = < 0x83c00000 0x10000 >;
|
||||
xlnx,count-width = <0x20>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gen0-assert = <0x1>;
|
||||
xlnx,gen1-assert = <0x1>;
|
||||
xlnx,one-timer-only = <0x0>;
|
||||
xlnx,trig0-assert = <0x1>;
|
||||
xlnx,trig1-assert = <0x1>;
|
||||
} ;
|
||||
} ;
|
||||
} ;
|
||||
@ -15,7 +15,6 @@
|
||||
#include <asm/page.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/mm.h> /* Get struct page {...} */
|
||||
#include <asm-generic/iomap.h>
|
||||
|
||||
#ifndef CONFIG_PCI
|
||||
#define _IO_BASE 0
|
||||
@ -25,211 +24,32 @@
|
||||
#define _IO_BASE isa_io_base
|
||||
#define _ISA_MEM_BASE isa_mem_base
|
||||
#define PCI_DRAM_OFFSET pci_dram_offset
|
||||
#endif
|
||||
struct pci_dev;
|
||||
extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
|
||||
#define pci_iounmap pci_iounmap
|
||||
|
||||
extern unsigned long isa_io_base;
|
||||
extern unsigned long pci_io_base;
|
||||
extern unsigned long pci_dram_offset;
|
||||
|
||||
extern resource_size_t isa_mem_base;
|
||||
#endif
|
||||
|
||||
#define PCI_IOBASE ((void __iomem *)_IO_BASE)
|
||||
#define IO_SPACE_LIMIT (0xFFFFFFFF)
|
||||
|
||||
/* the following is needed to support PCI with some drivers */
|
||||
|
||||
#define mmiowb()
|
||||
|
||||
static inline unsigned char __raw_readb(const volatile void __iomem *addr)
|
||||
{
|
||||
return *(volatile unsigned char __force *)addr;
|
||||
}
|
||||
static inline unsigned short __raw_readw(const volatile void __iomem *addr)
|
||||
{
|
||||
return *(volatile unsigned short __force *)addr;
|
||||
}
|
||||
static inline unsigned int __raw_readl(const volatile void __iomem *addr)
|
||||
{
|
||||
return *(volatile unsigned int __force *)addr;
|
||||
}
|
||||
static inline unsigned long __raw_readq(const volatile void __iomem *addr)
|
||||
{
|
||||
return *(volatile unsigned long __force *)addr;
|
||||
}
|
||||
static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
|
||||
{
|
||||
*(volatile unsigned char __force *)addr = v;
|
||||
}
|
||||
static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
|
||||
{
|
||||
*(volatile unsigned short __force *)addr = v;
|
||||
}
|
||||
static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
|
||||
{
|
||||
*(volatile unsigned int __force *)addr = v;
|
||||
}
|
||||
static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
|
||||
{
|
||||
*(volatile unsigned long __force *)addr = v;
|
||||
}
|
||||
|
||||
/*
|
||||
* read (readb, readw, readl, readq) and write (writeb, writew,
|
||||
* writel, writeq) accessors are for PCI and thus little endian.
|
||||
* Linux 2.4 for Microblaze had this wrong.
|
||||
*/
|
||||
static inline unsigned char readb(const volatile void __iomem *addr)
|
||||
{
|
||||
return *(volatile unsigned char __force *)addr;
|
||||
}
|
||||
static inline unsigned short readw(const volatile void __iomem *addr)
|
||||
{
|
||||
return le16_to_cpu(*(volatile unsigned short __force *)addr);
|
||||
}
|
||||
static inline unsigned int readl(const volatile void __iomem *addr)
|
||||
{
|
||||
return le32_to_cpu(*(volatile unsigned int __force *)addr);
|
||||
}
|
||||
#define readq readq
|
||||
static inline u64 readq(const volatile void __iomem *addr)
|
||||
{
|
||||
return le64_to_cpu(__raw_readq(addr));
|
||||
}
|
||||
static inline void writeb(unsigned char v, volatile void __iomem *addr)
|
||||
{
|
||||
*(volatile unsigned char __force *)addr = v;
|
||||
}
|
||||
static inline void writew(unsigned short v, volatile void __iomem *addr)
|
||||
{
|
||||
*(volatile unsigned short __force *)addr = cpu_to_le16(v);
|
||||
}
|
||||
static inline void writel(unsigned int v, volatile void __iomem *addr)
|
||||
{
|
||||
*(volatile unsigned int __force *)addr = cpu_to_le32(v);
|
||||
}
|
||||
#define writeq(b, addr) __raw_writeq(cpu_to_le64(b), addr)
|
||||
|
||||
/* ioread and iowrite variants. thease are for now same as __raw_
|
||||
* variants of accessors. we might check for endianess in the feature
|
||||
*/
|
||||
#define ioread8(addr) __raw_readb((u8 *)(addr))
|
||||
#define ioread16(addr) __raw_readw((u16 *)(addr))
|
||||
#define ioread32(addr) __raw_readl((u32 *)(addr))
|
||||
#define iowrite8(v, addr) __raw_writeb((u8)(v), (u8 *)(addr))
|
||||
#define iowrite16(v, addr) __raw_writew((u16)(v), (u16 *)(addr))
|
||||
#define iowrite32(v, addr) __raw_writel((u32)(v), (u32 *)(addr))
|
||||
|
||||
#define ioread16be(addr) __raw_readw((u16 *)(addr))
|
||||
#define ioread32be(addr) __raw_readl((u32 *)(addr))
|
||||
#define iowrite16be(v, addr) __raw_writew((u16)(v), (u16 *)(addr))
|
||||
#define iowrite32be(v, addr) __raw_writel((u32)(v), (u32 *)(addr))
|
||||
|
||||
/* These are the definitions for the x86 IO instructions
|
||||
* inb/inw/inl/outb/outw/outl, the "string" versions
|
||||
* insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions
|
||||
* inb_p/inw_p/...
|
||||
* The macros don't do byte-swapping.
|
||||
*/
|
||||
#define inb(port) readb((u8 *)((unsigned long)(port)))
|
||||
#define outb(val, port) writeb((val), (u8 *)((unsigned long)(port)))
|
||||
#define inw(port) readw((u16 *)((unsigned long)(port)))
|
||||
#define outw(val, port) writew((val), (u16 *)((unsigned long)(port)))
|
||||
#define inl(port) readl((u32 *)((unsigned long)(port)))
|
||||
#define outl(val, port) writel((val), (u32 *)((unsigned long)(port)))
|
||||
|
||||
#define inb_p(port) inb((port))
|
||||
#define outb_p(val, port) outb((val), (port))
|
||||
#define inw_p(port) inw((port))
|
||||
#define outw_p(val, port) outw((val), (port))
|
||||
#define inl_p(port) inl((port))
|
||||
#define outl_p(val, port) outl((val), (port))
|
||||
|
||||
#define memset_io(a, b, c) memset((void *)(a), (b), (c))
|
||||
#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
|
||||
#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
|
||||
#define phys_to_virt(addr) ((void *)__phys_to_virt(addr))
|
||||
#define virt_to_phys(addr) ((unsigned long)__virt_to_phys(addr))
|
||||
#define virt_to_bus(addr) ((unsigned long)__virt_to_phys(addr))
|
||||
|
||||
#define page_to_bus(page) (page_to_phys(page))
|
||||
#define bus_to_virt(addr) (phys_to_virt(addr))
|
||||
|
||||
extern void iounmap(void __iomem *addr);
|
||||
/*extern void *__ioremap(phys_addr_t address, unsigned long size,
|
||||
unsigned long flags);*/
|
||||
|
||||
extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
|
||||
#define ioremap_writethrough(addr, size) ioremap((addr), (size))
|
||||
#define ioremap_nocache(addr, size) ioremap((addr), (size))
|
||||
#define ioremap_fullcache(addr, size) ioremap((addr), (size))
|
||||
|
||||
#else /* CONFIG_MMU */
|
||||
|
||||
/**
|
||||
* virt_to_phys - map virtual addresses to physical
|
||||
* @address: address to remap
|
||||
*
|
||||
* The returned physical address is the physical (CPU) mapping for
|
||||
* the memory address given. It is only valid to use this function on
|
||||
* addresses directly mapped or allocated via kmalloc.
|
||||
*
|
||||
* This function does not give bus mappings for DMA transfers. In
|
||||
* almost all conceivable cases a device driver should not be using
|
||||
* this function
|
||||
*/
|
||||
static inline unsigned long __iomem virt_to_phys(volatile void *address)
|
||||
{
|
||||
return __pa((unsigned long)address);
|
||||
}
|
||||
|
||||
#define virt_to_bus virt_to_phys
|
||||
|
||||
/**
|
||||
* phys_to_virt - map physical address to virtual
|
||||
* @address: address to remap
|
||||
*
|
||||
* The returned virtual address is a current CPU mapping for
|
||||
* the memory address given. It is only valid to use this function on
|
||||
* addresses that have a kernel mapping
|
||||
*
|
||||
* This function does not handle bus mappings for DMA transfers. In
|
||||
* almost all conceivable cases a device driver should not be using
|
||||
* this function
|
||||
*/
|
||||
static inline void *phys_to_virt(unsigned long address)
|
||||
{
|
||||
return (void *)__va(address);
|
||||
}
|
||||
|
||||
#define bus_to_virt(a) phys_to_virt(a)
|
||||
|
||||
static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
|
||||
unsigned long flags)
|
||||
{
|
||||
return (void *)address;
|
||||
}
|
||||
|
||||
#define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
|
||||
#define iounmap(addr) ((void)0)
|
||||
#define ioremap_nocache(physaddr, size) ioremap(physaddr, size)
|
||||
#define ioremap_wc(addr, size) ioremap((addr), (size))
|
||||
|
||||
#endif /* CONFIG_MMU */
|
||||
|
||||
/*
|
||||
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
|
||||
* access
|
||||
*/
|
||||
#define xlate_dev_mem_ptr(p) __va(p)
|
||||
|
||||
/*
|
||||
* Convert a virtual cached pointer to an uncached pointer
|
||||
*/
|
||||
#define xlate_dev_kmem_ptr(p) p
|
||||
|
||||
/*
|
||||
* Big Endian
|
||||
*/
|
||||
/* Big Endian */
|
||||
#define out_be32(a, v) __raw_writel((v), (void __iomem __force *)(a))
|
||||
#define out_be16(a, v) __raw_writew((v), (a))
|
||||
|
||||
@ -239,10 +59,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
|
||||
#define writel_be(v, a) out_be32((__force unsigned *)a, v)
|
||||
#define readl_be(a) in_be32((__force unsigned *)a)
|
||||
|
||||
/*
|
||||
* Little endian
|
||||
*/
|
||||
|
||||
/* Little endian */
|
||||
#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a))
|
||||
#define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a))
|
||||
|
||||
@ -253,100 +70,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
|
||||
#define out_8(a, v) __raw_writeb((v), (a))
|
||||
#define in_8(a) __raw_readb(a)
|
||||
|
||||
#define mmiowb()
|
||||
|
||||
#define ioport_map(port, nr) ((void __iomem *)(port))
|
||||
#define ioport_unmap(addr)
|
||||
|
||||
/* from asm-generic/io.h */
|
||||
#ifndef insb
|
||||
static inline void insb(unsigned long addr, void *buffer, int count)
|
||||
{
|
||||
if (count) {
|
||||
u8 *buf = buffer;
|
||||
do {
|
||||
u8 x = inb(addr);
|
||||
*buf++ = x;
|
||||
} while (--count);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef insw
|
||||
static inline void insw(unsigned long addr, void *buffer, int count)
|
||||
{
|
||||
if (count) {
|
||||
u16 *buf = buffer;
|
||||
do {
|
||||
u16 x = inw(addr);
|
||||
*buf++ = x;
|
||||
} while (--count);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef insl
|
||||
static inline void insl(unsigned long addr, void *buffer, int count)
|
||||
{
|
||||
if (count) {
|
||||
u32 *buf = buffer;
|
||||
do {
|
||||
u32 x = inl(addr);
|
||||
*buf++ = x;
|
||||
} while (--count);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef outsb
|
||||
static inline void outsb(unsigned long addr, const void *buffer, int count)
|
||||
{
|
||||
if (count) {
|
||||
const u8 *buf = buffer;
|
||||
do {
|
||||
outb(*buf++, addr);
|
||||
} while (--count);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef outsw
|
||||
static inline void outsw(unsigned long addr, const void *buffer, int count)
|
||||
{
|
||||
if (count) {
|
||||
const u16 *buf = buffer;
|
||||
do {
|
||||
outw(*buf++, addr);
|
||||
} while (--count);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef outsl
|
||||
static inline void outsl(unsigned long addr, const void *buffer, int count)
|
||||
{
|
||||
if (count) {
|
||||
const u32 *buf = buffer;
|
||||
do {
|
||||
outl(*buf++, addr);
|
||||
} while (--count);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#define ioread8_rep(p, dst, count) \
|
||||
insb((unsigned long) (p), (dst), (count))
|
||||
#define ioread16_rep(p, dst, count) \
|
||||
insw((unsigned long) (p), (dst), (count))
|
||||
#define ioread32_rep(p, dst, count) \
|
||||
insl((unsigned long) (p), (dst), (count))
|
||||
|
||||
#define iowrite8_rep(p, src, count) \
|
||||
outsb((unsigned long) (p), (src), (count))
|
||||
#define iowrite16_rep(p, src, count) \
|
||||
outsw((unsigned long) (p), (src), (count))
|
||||
#define iowrite32_rep(p, src, count) \
|
||||
outsl((unsigned long) (p), (src), (count))
|
||||
#include <asm-generic/io.h>
|
||||
|
||||
#define readb_relaxed readb
|
||||
#define readw_relaxed readw
|
||||
|
||||
@ -122,7 +122,7 @@ struct thread_struct {
|
||||
}
|
||||
|
||||
/* Free all resources held by a thread. */
|
||||
extern inline void release_thread(struct task_struct *dead_task)
|
||||
static inline void release_thread(struct task_struct *dead_task)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
@ -19,14 +19,12 @@ extern char cmd_line[COMMAND_LINE_SIZE];
|
||||
|
||||
extern char *klimit;
|
||||
|
||||
void early_printk(const char *fmt, ...);
|
||||
|
||||
int setup_early_printk(char *opt);
|
||||
void remap_early_printk(void);
|
||||
void disable_early_printk(void);
|
||||
|
||||
void heartbeat(void);
|
||||
void setup_heartbeat(void);
|
||||
void microblaze_heartbeat(void);
|
||||
void microblaze_setup_heartbeat(void);
|
||||
|
||||
# ifdef CONFIG_MMU
|
||||
extern void mmu_reset(void);
|
||||
|
||||
@ -93,7 +93,7 @@
|
||||
#define __NR_settimeofday 79 /* ok */
|
||||
#define __NR_getgroups 80 /* ok */
|
||||
#define __NR_setgroups 81 /* ok */
|
||||
#define __NR_select 82 /* obsolete -> sys_pselect7 */
|
||||
#define __NR_select 82 /* obsolete -> sys_pselect6 */
|
||||
#define __NR_symlink 83 /* symlinkat */
|
||||
#define __NR_oldlstat 84 /* remove */
|
||||
#define __NR_readlink 85 /* obsolete -> sys_readlinkat */
|
||||
@ -320,7 +320,7 @@
|
||||
#define __NR_readlinkat 305 /* ok */
|
||||
#define __NR_fchmodat 306 /* ok */
|
||||
#define __NR_faccessat 307 /* ok */
|
||||
#define __NR_pselect6 308 /* obsolete -> sys_pselect7 */
|
||||
#define __NR_pselect6 308 /* ok */
|
||||
#define __NR_ppoll 309 /* ok */
|
||||
#define __NR_unshare 310 /* ok */
|
||||
#define __NR_set_robust_list 311 /* ok */
|
||||
@ -396,5 +396,7 @@
|
||||
#define __NR_process_vm_writev 378
|
||||
#define __NR_kcmp 379
|
||||
#define __NR_finit_module 380
|
||||
#define __NR_sched_setattr 381
|
||||
#define __NR_sched_getattr 382
|
||||
|
||||
#endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */
|
||||
|
||||
@ -16,7 +16,7 @@ extra-y := head.o vmlinux.lds
|
||||
|
||||
obj-y += dma.o exceptions.o \
|
||||
hw_exception_handler.o intc.o irq.o \
|
||||
process.o prom.o prom_parse.o ptrace.o \
|
||||
platform.o process.o prom.o prom_parse.o ptrace.o \
|
||||
reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
|
||||
|
||||
obj-y += cpu/
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
|
||||
static unsigned int base_addr;
|
||||
|
||||
void heartbeat(void)
|
||||
void microblaze_heartbeat(void)
|
||||
{
|
||||
static unsigned int cnt, period, dist;
|
||||
|
||||
@ -42,7 +42,7 @@ void heartbeat(void)
|
||||
}
|
||||
}
|
||||
|
||||
void setup_heartbeat(void)
|
||||
void microblaze_setup_heartbeat(void)
|
||||
{
|
||||
struct device_node *gpio = NULL;
|
||||
int *prop;
|
||||
|
||||
@ -32,6 +32,29 @@ static void __iomem *intc_baseaddr;
|
||||
#define MER_ME (1<<0)
|
||||
#define MER_HIE (1<<1)
|
||||
|
||||
static unsigned int (*read_fn)(void __iomem *);
|
||||
static void (*write_fn)(u32, void __iomem *);
|
||||
|
||||
static void intc_write32(u32 val, void __iomem *addr)
|
||||
{
|
||||
iowrite32(val, addr);
|
||||
}
|
||||
|
||||
static unsigned int intc_read32(void __iomem *addr)
|
||||
{
|
||||
return ioread32(addr);
|
||||
}
|
||||
|
||||
static void intc_write32_be(u32 val, void __iomem *addr)
|
||||
{
|
||||
iowrite32be(val, addr);
|
||||
}
|
||||
|
||||
static unsigned int intc_read32_be(void __iomem *addr)
|
||||
{
|
||||
return ioread32be(addr);
|
||||
}
|
||||
|
||||
static void intc_enable_or_unmask(struct irq_data *d)
|
||||
{
|
||||
unsigned long mask = 1 << d->hwirq;
|
||||
@ -43,21 +66,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
|
||||
* acks the irq before calling the interrupt handler
|
||||
*/
|
||||
if (irqd_is_level_type(d))
|
||||
out_be32(intc_baseaddr + IAR, mask);
|
||||
write_fn(mask, intc_baseaddr + IAR);
|
||||
|
||||
out_be32(intc_baseaddr + SIE, mask);
|
||||
write_fn(mask, intc_baseaddr + SIE);
|
||||
}
|
||||
|
||||
static void intc_disable_or_mask(struct irq_data *d)
|
||||
{
|
||||
pr_debug("disable: %ld\n", d->hwirq);
|
||||
out_be32(intc_baseaddr + CIE, 1 << d->hwirq);
|
||||
write_fn(1 << d->hwirq, intc_baseaddr + CIE);
|
||||
}
|
||||
|
||||
static void intc_ack(struct irq_data *d)
|
||||
{
|
||||
pr_debug("ack: %ld\n", d->hwirq);
|
||||
out_be32(intc_baseaddr + IAR, 1 << d->hwirq);
|
||||
write_fn(1 << d->hwirq, intc_baseaddr + IAR);
|
||||
}
|
||||
|
||||
static void intc_mask_ack(struct irq_data *d)
|
||||
@ -65,8 +88,8 @@ static void intc_mask_ack(struct irq_data *d)
|
||||
unsigned long mask = 1 << d->hwirq;
|
||||
|
||||
pr_debug("disable_and_ack: %ld\n", d->hwirq);
|
||||
out_be32(intc_baseaddr + CIE, mask);
|
||||
out_be32(intc_baseaddr + IAR, mask);
|
||||
write_fn(mask, intc_baseaddr + CIE);
|
||||
write_fn(mask, intc_baseaddr + IAR);
|
||||
}
|
||||
|
||||
static struct irq_chip intc_dev = {
|
||||
@ -83,7 +106,7 @@ unsigned int get_irq(void)
|
||||
{
|
||||
unsigned int hwirq, irq = -1;
|
||||
|
||||
hwirq = in_be32(intc_baseaddr + IVR);
|
||||
hwirq = read_fn(intc_baseaddr + IVR);
|
||||
if (hwirq != -1U)
|
||||
irq = irq_find_mapping(root_domain, hwirq);
|
||||
|
||||
@ -140,17 +163,25 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
|
||||
pr_info("%s: num_irq=%d, edge=0x%x\n",
|
||||
intc->full_name, nr_irq, intr_mask);
|
||||
|
||||
write_fn = intc_write32;
|
||||
read_fn = intc_read32;
|
||||
|
||||
/*
|
||||
* Disable all external interrupts until they are
|
||||
* explicity requested.
|
||||
*/
|
||||
out_be32(intc_baseaddr + IER, 0);
|
||||
write_fn(0, intc_baseaddr + IER);
|
||||
|
||||
/* Acknowledge any pending interrupts just in case. */
|
||||
out_be32(intc_baseaddr + IAR, 0xffffffff);
|
||||
write_fn(0xffffffff, intc_baseaddr + IAR);
|
||||
|
||||
/* Turn on the Master Enable. */
|
||||
out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);
|
||||
write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
|
||||
if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) {
|
||||
write_fn = intc_write32_be;
|
||||
read_fn = intc_read32_be;
|
||||
write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
|
||||
}
|
||||
|
||||
/* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
|
||||
* lazy and Michal can clean it up to something nicer when he tests
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/pm.h>
|
||||
|
||||
@ -216,7 +216,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
|
||||
/* MS: I need add offset in page */
|
||||
address += ((unsigned long)frame->tramp) & ~PAGE_MASK;
|
||||
/* MS address is virtual */
|
||||
address = virt_to_phys(address);
|
||||
address = __virt_to_phys(address);
|
||||
invalidate_icache_range(address, address + 8);
|
||||
flush_dcache_range(address, address + 8);
|
||||
}
|
||||
|
||||
@ -308,7 +308,7 @@ ENTRY(sys_call_table)
|
||||
.long sys_readlinkat /* 305 */
|
||||
.long sys_fchmodat
|
||||
.long sys_faccessat
|
||||
.long sys_ni_syscall /* pselect6 */
|
||||
.long sys_pselect6
|
||||
.long sys_ppoll
|
||||
.long sys_unshare /* 310 */
|
||||
.long sys_set_robust_list
|
||||
@ -363,8 +363,8 @@ ENTRY(sys_call_table)
|
||||
.long sys_sendmsg /* 360 */
|
||||
.long sys_recvmsg
|
||||
.long sys_accept4
|
||||
.long sys_ni_syscall
|
||||
.long sys_ni_syscall
|
||||
.long sys_preadv
|
||||
.long sys_pwritev
|
||||
.long sys_rt_tgsigqueueinfo /* 365 */
|
||||
.long sys_perf_event_open
|
||||
.long sys_recvmmsg
|
||||
@ -381,3 +381,5 @@ ENTRY(sys_call_table)
|
||||
.long sys_process_vm_writev
|
||||
.long sys_kcmp
|
||||
.long sys_finit_module
|
||||
.long sys_sched_setattr
|
||||
.long sys_sched_getattr
|
||||
|
||||
@ -43,10 +43,33 @@ static unsigned int timer_clock_freq;
|
||||
#define TCSR_PWMA (1<<9)
|
||||
#define TCSR_ENALL (1<<10)
|
||||
|
||||
static unsigned int (*read_fn)(void __iomem *);
|
||||
static void (*write_fn)(u32, void __iomem *);
|
||||
|
||||
static void timer_write32(u32 val, void __iomem *addr)
|
||||
{
|
||||
iowrite32(val, addr);
|
||||
}
|
||||
|
||||
static unsigned int timer_read32(void __iomem *addr)
|
||||
{
|
||||
return ioread32(addr);
|
||||
}
|
||||
|
||||
static void timer_write32_be(u32 val, void __iomem *addr)
|
||||
{
|
||||
iowrite32be(val, addr);
|
||||
}
|
||||
|
||||
static unsigned int timer_read32_be(void __iomem *addr)
|
||||
{
|
||||
return ioread32be(addr);
|
||||
}
|
||||
|
||||
static inline void xilinx_timer0_stop(void)
|
||||
{
|
||||
out_be32(timer_baseaddr + TCSR0,
|
||||
in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT);
|
||||
write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT,
|
||||
timer_baseaddr + TCSR0);
|
||||
}
|
||||
|
||||
static inline void xilinx_timer0_start_periodic(unsigned long load_val)
|
||||
@ -54,10 +77,10 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val)
|
||||
if (!load_val)
|
||||
load_val = 1;
|
||||
/* loading value to timer reg */
|
||||
out_be32(timer_baseaddr + TLR0, load_val);
|
||||
write_fn(load_val, timer_baseaddr + TLR0);
|
||||
|
||||
/* load the initial value */
|
||||
out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
|
||||
write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
|
||||
|
||||
/* see timer data sheet for detail
|
||||
* !ENALL - don't enable 'em all
|
||||
@ -72,8 +95,8 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val)
|
||||
* UDT - set the timer as down counter
|
||||
* !MDT0 - generate mode
|
||||
*/
|
||||
out_be32(timer_baseaddr + TCSR0,
|
||||
TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
|
||||
write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
|
||||
timer_baseaddr + TCSR0);
|
||||
}
|
||||
|
||||
static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
|
||||
@ -81,13 +104,13 @@ static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
|
||||
if (!load_val)
|
||||
load_val = 1;
|
||||
/* loading value to timer reg */
|
||||
out_be32(timer_baseaddr + TLR0, load_val);
|
||||
write_fn(load_val, timer_baseaddr + TLR0);
|
||||
|
||||
/* load the initial value */
|
||||
out_be32(timer_baseaddr + TCSR0, TCSR_LOAD);
|
||||
write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
|
||||
|
||||
out_be32(timer_baseaddr + TCSR0,
|
||||
TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
|
||||
write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
|
||||
timer_baseaddr + TCSR0);
|
||||
}
|
||||
|
||||
static int xilinx_timer_set_next_event(unsigned long delta,
|
||||
@ -133,14 +156,14 @@ static struct clock_event_device clockevent_xilinx_timer = {
|
||||
|
||||
static inline void timer_ack(void)
|
||||
{
|
||||
out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0));
|
||||
write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0);
|
||||
}
|
||||
|
||||
static irqreturn_t timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = &clockevent_xilinx_timer;
|
||||
#ifdef CONFIG_HEART_BEAT
|
||||
heartbeat();
|
||||
microblaze_heartbeat();
|
||||
#endif
|
||||
timer_ack();
|
||||
evt->event_handler(evt);
|
||||
@ -169,7 +192,7 @@ static __init void xilinx_clockevent_init(void)
|
||||
|
||||
static u64 xilinx_clock_read(void)
|
||||
{
|
||||
return in_be32(timer_baseaddr + TCR1);
|
||||
return read_fn(timer_baseaddr + TCR1);
|
||||
}
|
||||
|
||||
static cycle_t xilinx_read(struct clocksource *cs)
|
||||
@ -217,10 +240,10 @@ static int __init xilinx_clocksource_init(void)
|
||||
panic("failed to register clocksource");
|
||||
|
||||
/* stop timer1 */
|
||||
out_be32(timer_baseaddr + TCSR1,
|
||||
in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT);
|
||||
write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT,
|
||||
timer_baseaddr + TCSR1);
|
||||
/* start timer1 - up counting without interrupt */
|
||||
out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);
|
||||
write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1);
|
||||
|
||||
/* register timecounter - for ftrace support */
|
||||
init_xilinx_timecounter();
|
||||
@ -245,6 +268,15 @@ static void __init xilinx_timer_init(struct device_node *timer)
|
||||
BUG();
|
||||
}
|
||||
|
||||
write_fn = timer_write32;
|
||||
read_fn = timer_read32;
|
||||
|
||||
write_fn(TCSR_MDT, timer_baseaddr + TCSR0);
|
||||
if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) {
|
||||
write_fn = timer_write32_be;
|
||||
read_fn = timer_read32_be;
|
||||
}
|
||||
|
||||
irq = irq_of_parse_and_map(timer, 0);
|
||||
|
||||
of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
|
||||
@ -274,7 +306,7 @@ static void __init xilinx_timer_init(struct device_node *timer)
|
||||
|
||||
setup_irq(irq, &timer_irqaction);
|
||||
#ifdef CONFIG_HEART_BEAT
|
||||
setup_heartbeat();
|
||||
microblaze_setup_heartbeat();
|
||||
#endif
|
||||
xilinx_clocksource_init();
|
||||
xilinx_clockevent_init();
|
||||
|
||||
@ -117,7 +117,7 @@ void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle)
|
||||
ret = (void *)va;
|
||||
|
||||
/* This gives us the real physical address of the first page. */
|
||||
*dma_handle = pa = virt_to_bus((void *)vaddr);
|
||||
*dma_handle = pa = __virt_to_phys(vaddr);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
||||
@ -369,7 +369,7 @@ asmlinkage void __init mmu_init(void)
|
||||
if (initrd_start) {
|
||||
unsigned long size;
|
||||
size = initrd_end - initrd_start;
|
||||
memblock_reserve(virt_to_phys(initrd_start), size);
|
||||
memblock_reserve(__virt_to_phys(initrd_start), size);
|
||||
}
|
||||
#endif /* CONFIG_BLK_DEV_INITRD */
|
||||
|
||||
|
||||
@ -69,10 +69,11 @@ static void __iomem *__ioremap(phys_addr_t addr, unsigned long size,
|
||||
*
|
||||
* However, allow remap of rootfs: TBD
|
||||
*/
|
||||
|
||||
if (mem_init_done &&
|
||||
p >= memory_start && p < virt_to_phys(high_memory) &&
|
||||
!(p >= virt_to_phys((unsigned long)&__bss_stop) &&
|
||||
p < virt_to_phys((unsigned long)__bss_stop))) {
|
||||
!(p >= __virt_to_phys((phys_addr_t)__bss_stop) &&
|
||||
p < __virt_to_phys((phys_addr_t)__bss_stop))) {
|
||||
pr_warn("__ioremap(): phys addr "PTE_FMT" is RAM lr %pf\n",
|
||||
(unsigned long)p, __builtin_return_address(0));
|
||||
return NULL;
|
||||
|
||||
@ -1,6 +0,0 @@
|
||||
#
|
||||
# Makefile for arch/microblaze/platform directory
|
||||
#
|
||||
#obj-$(CONFIG_PLATFORM_GENERIC) += generic/
|
||||
|
||||
obj-y += platform.o
|
||||
@ -1,61 +0,0 @@
|
||||
#
|
||||
# (C) Copyright 2007 Michal Simek
|
||||
#
|
||||
# Michal SIMEK <monstr@monstr.eu>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
# Definitions for MICROBLAZE0
|
||||
comment "Definitions for MICROBLAZE0"
|
||||
|
||||
config KERNEL_BASE_ADDR
|
||||
hex "Physical address where Linux Kernel is"
|
||||
default "0x90000000"
|
||||
help
|
||||
BASE Address for kernel
|
||||
|
||||
config XILINX_MICROBLAZE0_FAMILY
|
||||
string "Targeted FPGA family"
|
||||
default "virtex5"
|
||||
|
||||
config XILINX_MICROBLAZE0_USE_MSR_INSTR
|
||||
int "USE_MSR_INSTR range (0:1)"
|
||||
default 0
|
||||
|
||||
config XILINX_MICROBLAZE0_USE_PCMP_INSTR
|
||||
int "USE_PCMP_INSTR range (0:1)"
|
||||
default 0
|
||||
|
||||
config XILINX_MICROBLAZE0_USE_BARREL
|
||||
int "USE_BARREL range (0:1)"
|
||||
default 0
|
||||
|
||||
config XILINX_MICROBLAZE0_USE_DIV
|
||||
int "USE_DIV range (0:1)"
|
||||
default 0
|
||||
|
||||
config XILINX_MICROBLAZE0_USE_HW_MUL
|
||||
int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
|
||||
default 0
|
||||
|
||||
config XILINX_MICROBLAZE0_USE_FPU
|
||||
int "USE_FPU values (0=NONE, 1=BASIC, 2=EXTENDED)"
|
||||
default 0
|
||||
|
||||
config XILINX_MICROBLAZE0_HW_VER
|
||||
string "Core version number"
|
||||
default 7.10.d
|
||||
@ -1,3 +0,0 @@
|
||||
#
|
||||
# Empty Makefile to keep make clean happy
|
||||
#
|
||||
@ -1,366 +0,0 @@
|
||||
/*
|
||||
* Device Tree Generator version: 1.1
|
||||
*
|
||||
* (C) Copyright 2007-2008 Xilinx, Inc.
|
||||
* (C) Copyright 2007-2009 Michal Simek
|
||||
*
|
||||
* Michal SIMEK <monstr@monstr.eu>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* CAUTION: This file is automatically generated by libgen.
|
||||
* Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
|
||||
*
|
||||
* XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,microblaze";
|
||||
hard-reset-gpios = <&LEDs_8Bit 2 1>;
|
||||
model = "testing";
|
||||
DDR2_SDRAM: memory@90000000 {
|
||||
device_type = "memory";
|
||||
reg = < 0x90000000 0x10000000 >;
|
||||
} ;
|
||||
aliases {
|
||||
ethernet0 = &Hard_Ethernet_MAC;
|
||||
serial0 = &RS232_Uart_1;
|
||||
} ;
|
||||
chosen {
|
||||
bootargs = "console=ttyUL0,115200 highres=on";
|
||||
linux,stdout-path = "/plb@0/serial@84000000";
|
||||
} ;
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#cpus = <0x1>;
|
||||
#size-cells = <0>;
|
||||
microblaze_0: cpu@0 {
|
||||
clock-frequency = <125000000>;
|
||||
compatible = "xlnx,microblaze-7.10.d";
|
||||
d-cache-baseaddr = <0x90000000>;
|
||||
d-cache-highaddr = <0x9fffffff>;
|
||||
d-cache-line-size = <0x10>;
|
||||
d-cache-size = <0x2000>;
|
||||
device_type = "cpu";
|
||||
i-cache-baseaddr = <0x90000000>;
|
||||
i-cache-highaddr = <0x9fffffff>;
|
||||
i-cache-line-size = <0x10>;
|
||||
i-cache-size = <0x2000>;
|
||||
model = "microblaze,7.10.d";
|
||||
reg = <0>;
|
||||
timebase-frequency = <125000000>;
|
||||
xlnx,addr-tag-bits = <0xf>;
|
||||
xlnx,allow-dcache-wr = <0x1>;
|
||||
xlnx,allow-icache-wr = <0x1>;
|
||||
xlnx,area-optimized = <0x0>;
|
||||
xlnx,cache-byte-size = <0x2000>;
|
||||
xlnx,d-lmb = <0x1>;
|
||||
xlnx,d-opb = <0x0>;
|
||||
xlnx,d-plb = <0x1>;
|
||||
xlnx,data-size = <0x20>;
|
||||
xlnx,dcache-addr-tag = <0xf>;
|
||||
xlnx,dcache-always-used = <0x1>;
|
||||
xlnx,dcache-byte-size = <0x2000>;
|
||||
xlnx,dcache-line-len = <0x4>;
|
||||
xlnx,dcache-use-fsl = <0x1>;
|
||||
xlnx,debug-enabled = <0x1>;
|
||||
xlnx,div-zero-exception = <0x1>;
|
||||
xlnx,dopb-bus-exception = <0x0>;
|
||||
xlnx,dynamic-bus-sizing = <0x1>;
|
||||
xlnx,edge-is-positive = <0x1>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,endianness = <0x1>;
|
||||
xlnx,fpu-exception = <0x1>;
|
||||
xlnx,fsl-data-size = <0x20>;
|
||||
xlnx,fsl-exception = <0x0>;
|
||||
xlnx,fsl-links = <0x0>;
|
||||
xlnx,i-lmb = <0x1>;
|
||||
xlnx,i-opb = <0x0>;
|
||||
xlnx,i-plb = <0x1>;
|
||||
xlnx,icache-always-used = <0x1>;
|
||||
xlnx,icache-line-len = <0x4>;
|
||||
xlnx,icache-use-fsl = <0x1>;
|
||||
xlnx,ill-opcode-exception = <0x1>;
|
||||
xlnx,instance = "microblaze_0";
|
||||
xlnx,interconnect = <0x1>;
|
||||
xlnx,interrupt-is-edge = <0x0>;
|
||||
xlnx,iopb-bus-exception = <0x0>;
|
||||
xlnx,mmu-dtlb-size = <0x4>;
|
||||
xlnx,mmu-itlb-size = <0x2>;
|
||||
xlnx,mmu-tlb-access = <0x3>;
|
||||
xlnx,mmu-zones = <0x10>;
|
||||
xlnx,number-of-pc-brk = <0x1>;
|
||||
xlnx,number-of-rd-addr-brk = <0x0>;
|
||||
xlnx,number-of-wr-addr-brk = <0x0>;
|
||||
xlnx,opcode-0x0-illegal = <0x1>;
|
||||
xlnx,pvr = <0x2>;
|
||||
xlnx,pvr-user1 = <0x0>;
|
||||
xlnx,pvr-user2 = <0x0>;
|
||||
xlnx,reset-msr = <0x0>;
|
||||
xlnx,sco = <0x0>;
|
||||
xlnx,unaligned-exceptions = <0x1>;
|
||||
xlnx,use-barrel = <0x1>;
|
||||
xlnx,use-dcache = <0x1>;
|
||||
xlnx,use-div = <0x1>;
|
||||
xlnx,use-ext-brk = <0x1>;
|
||||
xlnx,use-ext-nm-brk = <0x1>;
|
||||
xlnx,use-extended-fsl-instr = <0x0>;
|
||||
xlnx,use-fpu = <0x2>;
|
||||
xlnx,use-hw-mul = <0x2>;
|
||||
xlnx,use-icache = <0x1>;
|
||||
xlnx,use-interrupt = <0x1>;
|
||||
xlnx,use-mmu = <0x3>;
|
||||
xlnx,use-msr-instr = <0x1>;
|
||||
xlnx,use-pcmp-instr = <0x1>;
|
||||
} ;
|
||||
} ;
|
||||
mb_plb: plb@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
|
||||
ranges ;
|
||||
FLASH: flash@a0000000 {
|
||||
bank-width = <2>;
|
||||
compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
|
||||
reg = < 0xa0000000 0x2000000 >;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,include-datawidth-matching-0 = <0x1>;
|
||||
xlnx,include-datawidth-matching-1 = <0x0>;
|
||||
xlnx,include-datawidth-matching-2 = <0x0>;
|
||||
xlnx,include-datawidth-matching-3 = <0x0>;
|
||||
xlnx,include-negedge-ioregs = <0x0>;
|
||||
xlnx,include-plb-ipif = <0x1>;
|
||||
xlnx,include-wrbuf = <0x1>;
|
||||
xlnx,max-mem-width = <0x10>;
|
||||
xlnx,mch-native-dwidth = <0x20>;
|
||||
xlnx,mch-plb-clk-period-ps = <0x1f40>;
|
||||
xlnx,mch-splb-awidth = <0x20>;
|
||||
xlnx,mch0-accessbuf-depth = <0x10>;
|
||||
xlnx,mch0-protocol = <0x0>;
|
||||
xlnx,mch0-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch1-accessbuf-depth = <0x10>;
|
||||
xlnx,mch1-protocol = <0x0>;
|
||||
xlnx,mch1-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch2-accessbuf-depth = <0x10>;
|
||||
xlnx,mch2-protocol = <0x0>;
|
||||
xlnx,mch2-rddatabuf-depth = <0x10>;
|
||||
xlnx,mch3-accessbuf-depth = <0x10>;
|
||||
xlnx,mch3-protocol = <0x0>;
|
||||
xlnx,mch3-rddatabuf-depth = <0x10>;
|
||||
xlnx,mem0-width = <0x10>;
|
||||
xlnx,mem1-width = <0x20>;
|
||||
xlnx,mem2-width = <0x20>;
|
||||
xlnx,mem3-width = <0x20>;
|
||||
xlnx,num-banks-mem = <0x1>;
|
||||
xlnx,num-channels = <0x0>;
|
||||
xlnx,priority-mode = <0x0>;
|
||||
xlnx,synch-mem-0 = <0x0>;
|
||||
xlnx,synch-mem-1 = <0x0>;
|
||||
xlnx,synch-mem-2 = <0x0>;
|
||||
xlnx,synch-mem-3 = <0x0>;
|
||||
xlnx,synch-pipedelay-0 = <0x2>;
|
||||
xlnx,synch-pipedelay-1 = <0x2>;
|
||||
xlnx,synch-pipedelay-2 = <0x2>;
|
||||
xlnx,synch-pipedelay-3 = <0x2>;
|
||||
xlnx,tavdv-ps-mem-0 = <0x1adb0>;
|
||||
xlnx,tavdv-ps-mem-1 = <0x3a98>;
|
||||
xlnx,tavdv-ps-mem-2 = <0x3a98>;
|
||||
xlnx,tavdv-ps-mem-3 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-0 = <0x1adb0>;
|
||||
xlnx,tcedv-ps-mem-1 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-2 = <0x3a98>;
|
||||
xlnx,tcedv-ps-mem-3 = <0x3a98>;
|
||||
xlnx,thzce-ps-mem-0 = <0x88b8>;
|
||||
xlnx,thzce-ps-mem-1 = <0x1b58>;
|
||||
xlnx,thzce-ps-mem-2 = <0x1b58>;
|
||||
xlnx,thzce-ps-mem-3 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-0 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-1 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-2 = <0x1b58>;
|
||||
xlnx,thzoe-ps-mem-3 = <0x1b58>;
|
||||
xlnx,tlzwe-ps-mem-0 = <0x88b8>;
|
||||
xlnx,tlzwe-ps-mem-1 = <0x0>;
|
||||
xlnx,tlzwe-ps-mem-2 = <0x0>;
|
||||
xlnx,tlzwe-ps-mem-3 = <0x0>;
|
||||
xlnx,twc-ps-mem-0 = <0x2af8>;
|
||||
xlnx,twc-ps-mem-1 = <0x3a98>;
|
||||
xlnx,twc-ps-mem-2 = <0x3a98>;
|
||||
xlnx,twc-ps-mem-3 = <0x3a98>;
|
||||
xlnx,twp-ps-mem-0 = <0x11170>;
|
||||
xlnx,twp-ps-mem-1 = <0x2ee0>;
|
||||
xlnx,twp-ps-mem-2 = <0x2ee0>;
|
||||
xlnx,twp-ps-mem-3 = <0x2ee0>;
|
||||
xlnx,xcl0-linesize = <0x4>;
|
||||
xlnx,xcl0-writexfer = <0x1>;
|
||||
xlnx,xcl1-linesize = <0x4>;
|
||||
xlnx,xcl1-writexfer = <0x1>;
|
||||
xlnx,xcl2-linesize = <0x4>;
|
||||
xlnx,xcl2-writexfer = <0x1>;
|
||||
xlnx,xcl3-linesize = <0x4>;
|
||||
xlnx,xcl3-writexfer = <0x1>;
|
||||
} ;
|
||||
Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,compound";
|
||||
ranges ;
|
||||
ethernet@81c00000 {
|
||||
compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 5 2 >;
|
||||
llink-connected = <&PIM3>;
|
||||
local-mac-address = [ 00 0a 35 00 00 00 ];
|
||||
reg = < 0x81c00000 0x40 >;
|
||||
xlnx,bus2core-clk-ratio = <0x1>;
|
||||
xlnx,phy-type = <0x1>;
|
||||
xlnx,phyaddr = <0x1>;
|
||||
xlnx,rxcsum = <0x0>;
|
||||
xlnx,rxfifo = <0x1000>;
|
||||
xlnx,temac-type = <0x0>;
|
||||
xlnx,txcsum = <0x0>;
|
||||
xlnx,txfifo = <0x1000>;
|
||||
} ;
|
||||
} ;
|
||||
IIC_EEPROM: i2c@81600000 {
|
||||
compatible = "xlnx,xps-iic-2.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 6 2 >;
|
||||
reg = < 0x81600000 0x10000 >;
|
||||
xlnx,clk-freq = <0x7735940>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gpo-width = <0x1>;
|
||||
xlnx,iic-freq = <0x186a0>;
|
||||
xlnx,scl-inertial-delay = <0x0>;
|
||||
xlnx,sda-inertial-delay = <0x0>;
|
||||
xlnx,ten-bit-adr = <0x0>;
|
||||
} ;
|
||||
LEDs_8Bit: gpio@81400000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 7 2 >;
|
||||
reg = < 0x81400000 0x10000 >;
|
||||
xlnx,all-inputs = <0x0>;
|
||||
xlnx,all-inputs-2 = <0x0>;
|
||||
xlnx,dout-default = <0x0>;
|
||||
xlnx,dout-default-2 = <0x0>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gpio-width = <0x8>;
|
||||
xlnx,interrupt-present = <0x1>;
|
||||
xlnx,is-bidir = <0x1>;
|
||||
xlnx,is-bidir-2 = <0x1>;
|
||||
xlnx,is-dual = <0x0>;
|
||||
xlnx,tri-default = <0xffffffff>;
|
||||
xlnx,tri-default-2 = <0xffffffff>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
} ;
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
heartbeat {
|
||||
label = "Heartbeat";
|
||||
gpios = <&LEDs_8Bit 4 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
yellow {
|
||||
label = "Yellow";
|
||||
gpios = <&LEDs_8Bit 5 1>;
|
||||
};
|
||||
|
||||
red {
|
||||
label = "Red";
|
||||
gpios = <&LEDs_8Bit 6 1>;
|
||||
};
|
||||
|
||||
green {
|
||||
label = "Green";
|
||||
gpios = <&LEDs_8Bit 7 1>;
|
||||
};
|
||||
} ;
|
||||
RS232_Uart_1: serial@84000000 {
|
||||
clock-frequency = <125000000>;
|
||||
compatible = "xlnx,xps-uartlite-1.00.a";
|
||||
current-speed = <115200>;
|
||||
device_type = "serial";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 8 0 >;
|
||||
port-number = <0>;
|
||||
reg = < 0x84000000 0x10000 >;
|
||||
xlnx,baudrate = <0x1c200>;
|
||||
xlnx,data-bits = <0x8>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,odd-parity = <0x0>;
|
||||
xlnx,use-parity = <0x0>;
|
||||
} ;
|
||||
SysACE_CompactFlash: sysace@83600000 {
|
||||
compatible = "xlnx,xps-sysace-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 4 2 >;
|
||||
reg = < 0x83600000 0x10000 >;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,mem-width = <0x10>;
|
||||
} ;
|
||||
debug_module: debug@84400000 {
|
||||
compatible = "xlnx,mdm-1.00.d";
|
||||
reg = < 0x84400000 0x10000 >;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,interconnect = <0x1>;
|
||||
xlnx,jtag-chain = <0x2>;
|
||||
xlnx,mb-dbg-ports = <0x1>;
|
||||
xlnx,uart-width = <0x8>;
|
||||
xlnx,use-uart = <0x1>;
|
||||
xlnx,write-fsl-ports = <0x0>;
|
||||
} ;
|
||||
mpmc@90000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,mpmc-4.02.a";
|
||||
ranges ;
|
||||
PIM3: sdma@84600180 {
|
||||
compatible = "xlnx,ll-dma-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 2 2 1 2 >;
|
||||
reg = < 0x84600180 0x80 >;
|
||||
} ;
|
||||
} ;
|
||||
xps_intc_0: interrupt-controller@81800000 {
|
||||
#interrupt-cells = <0x2>;
|
||||
compatible = "xlnx,xps-intc-1.00.a";
|
||||
interrupt-controller ;
|
||||
reg = < 0x81800000 0x10000 >;
|
||||
xlnx,kind-of-intr = <0x100>;
|
||||
xlnx,num-intr-inputs = <0x9>;
|
||||
} ;
|
||||
xps_timer_1: timer@83c00000 {
|
||||
compatible = "xlnx,xps-timer-1.00.a";
|
||||
interrupt-parent = <&xps_intc_0>;
|
||||
interrupts = < 3 2 >;
|
||||
reg = < 0x83c00000 0x10000 >;
|
||||
xlnx,count-width = <0x20>;
|
||||
xlnx,family = "virtex5";
|
||||
xlnx,gen0-assert = <0x1>;
|
||||
xlnx,gen1-assert = <0x1>;
|
||||
xlnx,one-timer-only = <0x0>;
|
||||
xlnx,trig0-assert = <0x1>;
|
||||
xlnx,trig1-assert = <0x1>;
|
||||
} ;
|
||||
} ;
|
||||
} ;
|
||||
Loading…
Reference in New Issue
Block a user