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RDMA/mlx5: Use mlx5_umr_post_send_wait() to update MR pas
Move mlx5_ib_update_mr_pas logic to umr.c, and use mlx5_umr_post_send_wait() instead of mlx5_ib_post_send_wait(). Link: https://lore.kernel.org/r/ed8f2ee6c64804072155d727149abf7105f92536.1649747695.git.leonro@nvidia.com Signed-off-by: Aharon Landau <aharonl@nvidia.com> Reviewed-by: Michael Guralnik <michaelgur@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Aharon Landau
Jason Gunthorpe
parent
916adb491e
commit
b3d47ebd49
@ -1289,7 +1289,6 @@ int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
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int mlx5_ib_dealloc_mw(struct ib_mw *mw);
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int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
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int page_shift, int flags);
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int mlx5_ib_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags);
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struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
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int access_flags);
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void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
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@ -1082,76 +1082,6 @@ int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
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return err;
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}
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/*
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* Send the DMA list to the HW for a normal MR using UMR.
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* Dmabuf MR is handled in a similar way, except that the MLX5_IB_UPD_XLT_ZAP
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* flag may be used.
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*/
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int mlx5_ib_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags)
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{
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struct mlx5_ib_dev *dev = mr_to_mdev(mr);
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struct device *ddev = &dev->mdev->pdev->dev;
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struct ib_block_iter biter;
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struct mlx5_mtt *cur_mtt;
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struct mlx5_umr_wr wr;
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size_t orig_sg_length;
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struct mlx5_mtt *mtt;
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size_t final_size;
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struct ib_sge sg;
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int err = 0;
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if (WARN_ON(mr->umem->is_odp))
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return -EINVAL;
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mtt = mlx5_ib_create_xlt_wr(mr, &wr, &sg,
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ib_umem_num_dma_blocks(mr->umem,
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1 << mr->page_shift),
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sizeof(*mtt), flags);
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if (!mtt)
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return -ENOMEM;
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orig_sg_length = sg.length;
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cur_mtt = mtt;
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rdma_for_each_block (mr->umem->sgt_append.sgt.sgl, &biter,
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mr->umem->sgt_append.sgt.nents,
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BIT(mr->page_shift)) {
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if (cur_mtt == (void *)mtt + sg.length) {
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dma_sync_single_for_device(ddev, sg.addr, sg.length,
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DMA_TO_DEVICE);
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err = mlx5_ib_post_send_wait(dev, &wr);
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if (err)
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goto err;
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dma_sync_single_for_cpu(ddev, sg.addr, sg.length,
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DMA_TO_DEVICE);
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wr.offset += sg.length;
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cur_mtt = mtt;
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}
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cur_mtt->ptag =
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cpu_to_be64(rdma_block_iter_dma_address(&biter) |
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MLX5_IB_MTT_PRESENT);
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if (mr->umem->is_dmabuf && (flags & MLX5_IB_UPD_XLT_ZAP))
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cur_mtt->ptag = 0;
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cur_mtt++;
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}
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final_size = (void *)cur_mtt - (void *)mtt;
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sg.length = ALIGN(final_size, MLX5_UMR_MTT_ALIGNMENT);
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memset(cur_mtt, 0, sg.length - final_size);
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wr.wr.send_flags |= xlt_wr_final_send_flags(flags);
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wr.xlt_size = sg.length;
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dma_sync_single_for_device(ddev, sg.addr, sg.length, DMA_TO_DEVICE);
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err = mlx5_ib_post_send_wait(dev, &wr);
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err:
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sg.length = orig_sg_length;
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mlx5r_umr_unmap_free_xlt(dev, mtt, &sg);
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return err;
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}
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/*
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* If ibmr is NULL it will be allocated by reg_create.
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* Else, the given ibmr will be used.
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@ -1368,7 +1298,7 @@ static struct ib_mr *create_real_mr(struct ib_pd *pd, struct ib_umem *umem,
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* configured properly but left disabled. It is safe to go ahead
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* and configure it again via UMR while enabling it.
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*/
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err = mlx5_ib_update_mr_pas(mr, MLX5_IB_UPD_XLT_ENABLE);
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err = mlx5r_umr_update_mr_pas(mr, MLX5_IB_UPD_XLT_ENABLE);
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if (err) {
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mlx5_ib_dereg_mr(&mr->ibmr, NULL);
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return ERR_PTR(err);
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@ -1467,7 +1397,7 @@ static void mlx5_ib_dmabuf_invalidate_cb(struct dma_buf_attachment *attach)
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if (!umem_dmabuf->sgt)
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return;
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mlx5_ib_update_mr_pas(mr, MLX5_IB_UPD_XLT_ZAP);
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mlx5r_umr_update_mr_pas(mr, MLX5_IB_UPD_XLT_ZAP);
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ib_umem_dmabuf_unmap_pages(umem_dmabuf);
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}
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@ -1602,7 +1532,7 @@ static int umr_rereg_pas(struct mlx5_ib_mr *mr, struct ib_pd *pd,
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mr->ibmr.length = new_umem->length;
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mr->page_shift = order_base_2(page_size);
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mr->umem = new_umem;
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err = mlx5_ib_update_mr_pas(mr, upd_flags);
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err = mlx5r_umr_update_mr_pas(mr, upd_flags);
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if (err) {
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/*
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* The MR is revoked at this point so there is no issue to free
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@ -715,7 +715,7 @@ static int pagefault_dmabuf_mr(struct mlx5_ib_mr *mr, size_t bcnt,
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ib_umem_dmabuf_unmap_pages(umem_dmabuf);
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err = -EINVAL;
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} else {
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err = mlx5_ib_update_mr_pas(mr, xlt_flags);
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err = mlx5r_umr_update_mr_pas(mr, xlt_flags);
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}
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dma_resv_unlock(umem_dmabuf->attach->dmabuf->resv);
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@ -499,3 +499,162 @@ void *mlx5r_umr_create_xlt(struct mlx5_ib_dev *dev, struct ib_sge *sg,
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return xlt;
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}
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static void
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mlx5r_umr_set_update_xlt_ctrl_seg(struct mlx5_wqe_umr_ctrl_seg *ctrl_seg,
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unsigned int flags, struct ib_sge *sg)
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{
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if (!(flags & MLX5_IB_UPD_XLT_ENABLE))
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/* fail if free */
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ctrl_seg->flags = MLX5_UMR_CHECK_FREE;
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else
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/* fail if not free */
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ctrl_seg->flags = MLX5_UMR_CHECK_NOT_FREE;
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ctrl_seg->xlt_octowords =
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cpu_to_be16(mlx5r_umr_get_xlt_octo(sg->length));
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}
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static void mlx5r_umr_set_update_xlt_mkey_seg(struct mlx5_ib_dev *dev,
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struct mlx5_mkey_seg *mkey_seg,
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struct mlx5_ib_mr *mr,
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unsigned int page_shift)
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{
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mlx5r_umr_set_access_flags(dev, mkey_seg, mr->access_flags);
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MLX5_SET(mkc, mkey_seg, pd, to_mpd(mr->ibmr.pd)->pdn);
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MLX5_SET64(mkc, mkey_seg, start_addr, mr->ibmr.iova);
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MLX5_SET64(mkc, mkey_seg, len, mr->ibmr.length);
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MLX5_SET(mkc, mkey_seg, log_page_size, page_shift);
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MLX5_SET(mkc, mkey_seg, qpn, 0xffffff);
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MLX5_SET(mkc, mkey_seg, mkey_7_0, mlx5_mkey_variant(mr->mmkey.key));
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}
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static void
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mlx5r_umr_set_update_xlt_data_seg(struct mlx5_wqe_data_seg *data_seg,
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struct ib_sge *sg)
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{
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data_seg->byte_count = cpu_to_be32(sg->length);
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data_seg->lkey = cpu_to_be32(sg->lkey);
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data_seg->addr = cpu_to_be64(sg->addr);
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}
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static void mlx5r_umr_update_offset(struct mlx5_wqe_umr_ctrl_seg *ctrl_seg,
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u64 offset)
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{
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u64 octo_offset = mlx5r_umr_get_xlt_octo(offset);
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ctrl_seg->xlt_offset = cpu_to_be16(octo_offset & 0xffff);
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ctrl_seg->xlt_offset_47_16 = cpu_to_be32(octo_offset >> 16);
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ctrl_seg->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
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}
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static void mlx5r_umr_final_update_xlt(struct mlx5_ib_dev *dev,
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struct mlx5r_umr_wqe *wqe,
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struct mlx5_ib_mr *mr, struct ib_sge *sg,
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unsigned int flags)
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{
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bool update_pd_access, update_translation;
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if (flags & MLX5_IB_UPD_XLT_ENABLE)
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wqe->ctrl_seg.mkey_mask |= get_umr_enable_mr_mask();
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update_pd_access = flags & MLX5_IB_UPD_XLT_ENABLE ||
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flags & MLX5_IB_UPD_XLT_PD ||
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flags & MLX5_IB_UPD_XLT_ACCESS;
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if (update_pd_access) {
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wqe->ctrl_seg.mkey_mask |= get_umr_update_access_mask(dev);
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wqe->ctrl_seg.mkey_mask |= get_umr_update_pd_mask();
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}
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update_translation =
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flags & MLX5_IB_UPD_XLT_ENABLE || flags & MLX5_IB_UPD_XLT_ADDR;
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if (update_translation) {
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wqe->ctrl_seg.mkey_mask |= get_umr_update_translation_mask();
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if (!mr->ibmr.length)
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MLX5_SET(mkc, &wqe->mkey_seg, length64, 1);
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}
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wqe->ctrl_seg.xlt_octowords =
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cpu_to_be16(mlx5r_umr_get_xlt_octo(sg->length));
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wqe->data_seg.byte_count = cpu_to_be32(sg->length);
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}
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/*
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* Send the DMA list to the HW for a normal MR using UMR.
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* Dmabuf MR is handled in a similar way, except that the MLX5_IB_UPD_XLT_ZAP
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* flag may be used.
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*/
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int mlx5r_umr_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags)
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{
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struct mlx5_ib_dev *dev = mr_to_mdev(mr);
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struct device *ddev = &dev->mdev->pdev->dev;
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struct mlx5r_umr_wqe wqe = {};
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struct ib_block_iter biter;
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struct mlx5_mtt *cur_mtt;
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size_t orig_sg_length;
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struct mlx5_mtt *mtt;
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size_t final_size;
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struct ib_sge sg;
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u64 offset = 0;
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int err = 0;
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if (WARN_ON(mr->umem->is_odp))
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return -EINVAL;
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mtt = mlx5r_umr_create_xlt(
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dev, &sg, ib_umem_num_dma_blocks(mr->umem, 1 << mr->page_shift),
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sizeof(*mtt), flags);
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if (!mtt)
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return -ENOMEM;
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orig_sg_length = sg.length;
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mlx5r_umr_set_update_xlt_ctrl_seg(&wqe.ctrl_seg, flags, &sg);
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mlx5r_umr_set_update_xlt_mkey_seg(dev, &wqe.mkey_seg, mr,
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mr->page_shift);
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mlx5r_umr_set_update_xlt_data_seg(&wqe.data_seg, &sg);
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cur_mtt = mtt;
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rdma_for_each_block(mr->umem->sgt_append.sgt.sgl, &biter,
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mr->umem->sgt_append.sgt.nents,
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BIT(mr->page_shift)) {
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if (cur_mtt == (void *)mtt + sg.length) {
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dma_sync_single_for_device(ddev, sg.addr, sg.length,
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DMA_TO_DEVICE);
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err = mlx5r_umr_post_send_wait(dev, mr->mmkey.key, &wqe,
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true);
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if (err)
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goto err;
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dma_sync_single_for_cpu(ddev, sg.addr, sg.length,
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DMA_TO_DEVICE);
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offset += sg.length;
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mlx5r_umr_update_offset(&wqe.ctrl_seg, offset);
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cur_mtt = mtt;
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}
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cur_mtt->ptag =
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cpu_to_be64(rdma_block_iter_dma_address(&biter) |
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MLX5_IB_MTT_PRESENT);
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if (mr->umem->is_dmabuf && (flags & MLX5_IB_UPD_XLT_ZAP))
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cur_mtt->ptag = 0;
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cur_mtt++;
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}
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final_size = (void *)cur_mtt - (void *)mtt;
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sg.length = ALIGN(final_size, MLX5_UMR_MTT_ALIGNMENT);
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memset(cur_mtt, 0, sg.length - final_size);
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mlx5r_umr_final_update_xlt(dev, &wqe, mr, &sg, flags);
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dma_sync_single_for_device(ddev, sg.addr, sg.length, DMA_TO_DEVICE);
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err = mlx5r_umr_post_send_wait(dev, mr->mmkey.key, &wqe, true);
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err:
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sg.length = orig_sg_length;
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mlx5r_umr_unmap_free_xlt(dev, mtt, &sg);
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return err;
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}
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@ -98,5 +98,6 @@ void *mlx5r_umr_create_xlt(struct mlx5_ib_dev *dev, struct ib_sge *sg,
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size_t nents, size_t ent_size, unsigned int flags);
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void mlx5r_umr_unmap_free_xlt(struct mlx5_ib_dev *dev, void *xlt,
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struct ib_sge *sg);
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int mlx5r_umr_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags);
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#endif /* _MLX5_IB_UMR_H */
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