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vfio/pci: remove vfio_pci_nvlink2
This driver never had any open userspace (which for VFIO would include VM kernel drivers) that use it, and thus should never have been added by our normal userspace ABI rules. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Message-Id: <20210326061311.1497642-2-hch@lst.de> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
This commit is contained in:
Christoph Hellwig
Alex Williamson
parent
e49d033bdd
commit
b392a19891
@ -39,9 +39,3 @@ config VFIO_PCI_IGD
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and LPC bridge config space.
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To enable Intel IGD assignment through vfio-pci, say Y.
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config VFIO_PCI_NVLINK2
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def_bool y
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depends on VFIO_PCI && PPC_POWERNV && SPAPR_TCE_IOMMU
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help
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VFIO PCI support for P9 Witherspoon machine with NVIDIA V100 GPUs
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@ -2,7 +2,6 @@
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vfio-pci-y := vfio_pci.o vfio_pci_intrs.o vfio_pci_rdwr.o vfio_pci_config.o
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vfio-pci-$(CONFIG_VFIO_PCI_IGD) += vfio_pci_igd.o
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vfio-pci-$(CONFIG_VFIO_PCI_NVLINK2) += vfio_pci_nvlink2.o
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vfio-pci-$(CONFIG_S390) += vfio_pci_zdev.o
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obj-$(CONFIG_VFIO_PCI) += vfio-pci.o
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@ -389,24 +389,6 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev)
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}
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}
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if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
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IS_ENABLED(CONFIG_VFIO_PCI_NVLINK2)) {
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ret = vfio_pci_nvdia_v100_nvlink2_init(vdev);
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if (ret && ret != -ENODEV) {
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pci_warn(pdev, "Failed to setup NVIDIA NV2 RAM region\n");
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goto disable_exit;
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}
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}
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if (pdev->vendor == PCI_VENDOR_ID_IBM &&
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IS_ENABLED(CONFIG_VFIO_PCI_NVLINK2)) {
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ret = vfio_pci_ibm_npu2_init(vdev);
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if (ret && ret != -ENODEV) {
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pci_warn(pdev, "Failed to setup NVIDIA NV2 ATSD region\n");
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goto disable_exit;
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}
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}
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vfio_pci_probe_mmaps(vdev);
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return 0;
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@ -1,490 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* VFIO PCI NVIDIA Whitherspoon GPU support a.k.a. NVLink2.
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*
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* Copyright (C) 2018 IBM Corp. All rights reserved.
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* Author: Alexey Kardashevskiy <aik@ozlabs.ru>
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*
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* Register an on-GPU RAM region for cacheable access.
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*
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* Derived from original vfio_pci_igd.c:
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* Copyright (C) 2016 Red Hat, Inc. All rights reserved.
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* Author: Alex Williamson <alex.williamson@redhat.com>
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*/
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#include <linux/io.h>
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#include <linux/pci.h>
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#include <linux/uaccess.h>
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#include <linux/vfio.h>
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#include <linux/sched/mm.h>
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#include <linux/mmu_context.h>
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#include <asm/kvm_ppc.h>
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#include "vfio_pci_private.h"
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#define CREATE_TRACE_POINTS
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#include "trace.h"
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EXPORT_TRACEPOINT_SYMBOL_GPL(vfio_pci_nvgpu_mmap_fault);
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EXPORT_TRACEPOINT_SYMBOL_GPL(vfio_pci_nvgpu_mmap);
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EXPORT_TRACEPOINT_SYMBOL_GPL(vfio_pci_npu2_mmap);
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struct vfio_pci_nvgpu_data {
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unsigned long gpu_hpa; /* GPU RAM physical address */
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unsigned long gpu_tgt; /* TGT address of corresponding GPU RAM */
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unsigned long useraddr; /* GPU RAM userspace address */
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unsigned long size; /* Size of the GPU RAM window (usually 128GB) */
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struct mm_struct *mm;
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struct mm_iommu_table_group_mem_t *mem; /* Pre-registered RAM descr. */
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struct pci_dev *gpdev;
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struct notifier_block group_notifier;
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};
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static size_t vfio_pci_nvgpu_rw(struct vfio_pci_device *vdev,
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char __user *buf, size_t count, loff_t *ppos, bool iswrite)
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{
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unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - VFIO_PCI_NUM_REGIONS;
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struct vfio_pci_nvgpu_data *data = vdev->region[i].data;
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loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
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loff_t posaligned = pos & PAGE_MASK, posoff = pos & ~PAGE_MASK;
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size_t sizealigned;
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void __iomem *ptr;
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if (pos >= vdev->region[i].size)
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return -EINVAL;
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count = min(count, (size_t)(vdev->region[i].size - pos));
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/*
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* We map only a bit of GPU RAM for a short time instead of mapping it
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* for the guest lifetime as:
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*
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* 1) we do not know GPU RAM size, only aperture which is 4-8 times
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* bigger than actual RAM size (16/32GB RAM vs. 128GB aperture);
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* 2) mapping GPU RAM allows CPU to prefetch and if this happens
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* before NVLink bridge is reset (which fences GPU RAM),
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* hardware management interrupts (HMI) might happen, this
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* will freeze NVLink bridge.
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*
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* This is not fast path anyway.
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*/
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sizealigned = ALIGN(posoff + count, PAGE_SIZE);
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ptr = ioremap_cache(data->gpu_hpa + posaligned, sizealigned);
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if (!ptr)
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return -EFAULT;
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if (iswrite) {
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if (copy_from_user(ptr + posoff, buf, count))
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count = -EFAULT;
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else
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*ppos += count;
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} else {
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if (copy_to_user(buf, ptr + posoff, count))
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count = -EFAULT;
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else
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*ppos += count;
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}
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iounmap(ptr);
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return count;
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}
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static void vfio_pci_nvgpu_release(struct vfio_pci_device *vdev,
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struct vfio_pci_region *region)
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{
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struct vfio_pci_nvgpu_data *data = region->data;
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long ret;
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/* If there were any mappings at all... */
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if (data->mm) {
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if (data->mem) {
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ret = mm_iommu_put(data->mm, data->mem);
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WARN_ON(ret);
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}
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mmdrop(data->mm);
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}
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vfio_unregister_notifier(&data->gpdev->dev, VFIO_GROUP_NOTIFY,
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&data->group_notifier);
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pnv_npu2_unmap_lpar_dev(data->gpdev);
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kfree(data);
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}
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static vm_fault_t vfio_pci_nvgpu_mmap_fault(struct vm_fault *vmf)
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{
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vm_fault_t ret;
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struct vm_area_struct *vma = vmf->vma;
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struct vfio_pci_region *region = vma->vm_private_data;
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struct vfio_pci_nvgpu_data *data = region->data;
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unsigned long vmf_off = (vmf->address - vma->vm_start) >> PAGE_SHIFT;
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unsigned long nv2pg = data->gpu_hpa >> PAGE_SHIFT;
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unsigned long vm_pgoff = vma->vm_pgoff &
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((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1);
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unsigned long pfn = nv2pg + vm_pgoff + vmf_off;
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ret = vmf_insert_pfn(vma, vmf->address, pfn);
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trace_vfio_pci_nvgpu_mmap_fault(data->gpdev, pfn << PAGE_SHIFT,
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vmf->address, ret);
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return ret;
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}
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static const struct vm_operations_struct vfio_pci_nvgpu_mmap_vmops = {
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.fault = vfio_pci_nvgpu_mmap_fault,
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};
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static int vfio_pci_nvgpu_mmap(struct vfio_pci_device *vdev,
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struct vfio_pci_region *region, struct vm_area_struct *vma)
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{
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int ret;
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struct vfio_pci_nvgpu_data *data = region->data;
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if (data->useraddr)
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return -EPERM;
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if (vma->vm_end - vma->vm_start > data->size)
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return -EINVAL;
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vma->vm_private_data = region;
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vma->vm_flags |= VM_PFNMAP;
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vma->vm_ops = &vfio_pci_nvgpu_mmap_vmops;
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/*
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* Calling mm_iommu_newdev() here once as the region is not
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* registered yet and therefore right initialization will happen now.
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* Other places will use mm_iommu_find() which returns
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* registered @mem and does not go gup().
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*/
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data->useraddr = vma->vm_start;
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data->mm = current->mm;
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mmgrab(data->mm);
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ret = (int) mm_iommu_newdev(data->mm, data->useraddr,
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vma_pages(vma), data->gpu_hpa, &data->mem);
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trace_vfio_pci_nvgpu_mmap(vdev->pdev, data->gpu_hpa, data->useraddr,
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vma->vm_end - vma->vm_start, ret);
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return ret;
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}
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static int vfio_pci_nvgpu_add_capability(struct vfio_pci_device *vdev,
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struct vfio_pci_region *region, struct vfio_info_cap *caps)
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{
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struct vfio_pci_nvgpu_data *data = region->data;
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struct vfio_region_info_cap_nvlink2_ssatgt cap = {
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.header.id = VFIO_REGION_INFO_CAP_NVLINK2_SSATGT,
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.header.version = 1,
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.tgt = data->gpu_tgt
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};
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return vfio_info_add_capability(caps, &cap.header, sizeof(cap));
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}
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static const struct vfio_pci_regops vfio_pci_nvgpu_regops = {
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.rw = vfio_pci_nvgpu_rw,
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.release = vfio_pci_nvgpu_release,
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.mmap = vfio_pci_nvgpu_mmap,
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.add_capability = vfio_pci_nvgpu_add_capability,
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};
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static int vfio_pci_nvgpu_group_notifier(struct notifier_block *nb,
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unsigned long action, void *opaque)
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{
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struct kvm *kvm = opaque;
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struct vfio_pci_nvgpu_data *data = container_of(nb,
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struct vfio_pci_nvgpu_data,
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group_notifier);
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if (action == VFIO_GROUP_NOTIFY_SET_KVM && kvm &&
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pnv_npu2_map_lpar_dev(data->gpdev,
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kvm->arch.lpid, MSR_DR | MSR_PR))
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return NOTIFY_BAD;
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return NOTIFY_OK;
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}
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int vfio_pci_nvdia_v100_nvlink2_init(struct vfio_pci_device *vdev)
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{
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int ret;
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u64 reg[2];
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u64 tgt = 0;
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struct device_node *npu_node, *mem_node;
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struct pci_dev *npu_dev;
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struct vfio_pci_nvgpu_data *data;
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uint32_t mem_phandle = 0;
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unsigned long events = VFIO_GROUP_NOTIFY_SET_KVM;
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/*
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* PCI config space does not tell us about NVLink presense but
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* platform does, use this.
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*/
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npu_dev = pnv_pci_get_npu_dev(vdev->pdev, 0);
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if (!npu_dev)
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return -ENODEV;
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npu_node = pci_device_to_OF_node(npu_dev);
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if (!npu_node)
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return -EINVAL;
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if (of_property_read_u32(npu_node, "memory-region", &mem_phandle))
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return -ENODEV;
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mem_node = of_find_node_by_phandle(mem_phandle);
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if (!mem_node)
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return -EINVAL;
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if (of_property_read_variable_u64_array(mem_node, "reg", reg,
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ARRAY_SIZE(reg), ARRAY_SIZE(reg)) !=
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ARRAY_SIZE(reg))
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return -EINVAL;
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if (of_property_read_u64(npu_node, "ibm,device-tgt-addr", &tgt)) {
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dev_warn(&vdev->pdev->dev, "No ibm,device-tgt-addr found\n");
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return -EFAULT;
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}
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->gpu_hpa = reg[0];
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data->gpu_tgt = tgt;
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data->size = reg[1];
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dev_dbg(&vdev->pdev->dev, "%lx..%lx\n", data->gpu_hpa,
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data->gpu_hpa + data->size - 1);
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data->gpdev = vdev->pdev;
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data->group_notifier.notifier_call = vfio_pci_nvgpu_group_notifier;
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ret = vfio_register_notifier(&data->gpdev->dev, VFIO_GROUP_NOTIFY,
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&events, &data->group_notifier);
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if (ret)
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goto free_exit;
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/*
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* We have just set KVM, we do not need the listener anymore.
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* Also, keeping it registered means that if more than one GPU is
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* assigned, we will get several similar notifiers notifying about
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* the same device again which does not help with anything.
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*/
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vfio_unregister_notifier(&data->gpdev->dev, VFIO_GROUP_NOTIFY,
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&data->group_notifier);
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ret = vfio_pci_register_dev_region(vdev,
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PCI_VENDOR_ID_NVIDIA | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
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VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM,
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&vfio_pci_nvgpu_regops,
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data->size,
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VFIO_REGION_INFO_FLAG_READ |
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VFIO_REGION_INFO_FLAG_WRITE |
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VFIO_REGION_INFO_FLAG_MMAP,
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data);
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if (ret)
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goto free_exit;
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return 0;
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free_exit:
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kfree(data);
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return ret;
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}
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/*
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* IBM NPU2 bridge
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*/
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struct vfio_pci_npu2_data {
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void *base; /* ATSD register virtual address, for emulated access */
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unsigned long mmio_atsd; /* ATSD physical address */
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unsigned long gpu_tgt; /* TGT address of corresponding GPU RAM */
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unsigned int link_speed; /* The link speed from DT's ibm,nvlink-speed */
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};
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static size_t vfio_pci_npu2_rw(struct vfio_pci_device *vdev,
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char __user *buf, size_t count, loff_t *ppos, bool iswrite)
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{
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unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - VFIO_PCI_NUM_REGIONS;
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struct vfio_pci_npu2_data *data = vdev->region[i].data;
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loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
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if (pos >= vdev->region[i].size)
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return -EINVAL;
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count = min(count, (size_t)(vdev->region[i].size - pos));
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if (iswrite) {
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if (copy_from_user(data->base + pos, buf, count))
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return -EFAULT;
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} else {
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if (copy_to_user(buf, data->base + pos, count))
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return -EFAULT;
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}
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*ppos += count;
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return count;
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}
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static int vfio_pci_npu2_mmap(struct vfio_pci_device *vdev,
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struct vfio_pci_region *region, struct vm_area_struct *vma)
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{
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int ret;
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struct vfio_pci_npu2_data *data = region->data;
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unsigned long req_len = vma->vm_end - vma->vm_start;
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if (req_len != PAGE_SIZE)
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return -EINVAL;
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vma->vm_flags |= VM_PFNMAP;
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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ret = remap_pfn_range(vma, vma->vm_start, data->mmio_atsd >> PAGE_SHIFT,
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req_len, vma->vm_page_prot);
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trace_vfio_pci_npu2_mmap(vdev->pdev, data->mmio_atsd, vma->vm_start,
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vma->vm_end - vma->vm_start, ret);
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return ret;
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}
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static void vfio_pci_npu2_release(struct vfio_pci_device *vdev,
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struct vfio_pci_region *region)
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{
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struct vfio_pci_npu2_data *data = region->data;
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memunmap(data->base);
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kfree(data);
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}
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static int vfio_pci_npu2_add_capability(struct vfio_pci_device *vdev,
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struct vfio_pci_region *region, struct vfio_info_cap *caps)
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{
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struct vfio_pci_npu2_data *data = region->data;
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struct vfio_region_info_cap_nvlink2_ssatgt captgt = {
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.header.id = VFIO_REGION_INFO_CAP_NVLINK2_SSATGT,
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.header.version = 1,
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.tgt = data->gpu_tgt
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};
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struct vfio_region_info_cap_nvlink2_lnkspd capspd = {
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.header.id = VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD,
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.header.version = 1,
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.link_speed = data->link_speed
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};
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int ret;
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ret = vfio_info_add_capability(caps, &captgt.header, sizeof(captgt));
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if (ret)
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return ret;
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return vfio_info_add_capability(caps, &capspd.header, sizeof(capspd));
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||||
}
|
||||
|
||||
static const struct vfio_pci_regops vfio_pci_npu2_regops = {
|
||||
.rw = vfio_pci_npu2_rw,
|
||||
.mmap = vfio_pci_npu2_mmap,
|
||||
.release = vfio_pci_npu2_release,
|
||||
.add_capability = vfio_pci_npu2_add_capability,
|
||||
};
|
||||
|
||||
int vfio_pci_ibm_npu2_init(struct vfio_pci_device *vdev)
|
||||
{
|
||||
int ret;
|
||||
struct vfio_pci_npu2_data *data;
|
||||
struct device_node *nvlink_dn;
|
||||
u32 nvlink_index = 0, mem_phandle = 0;
|
||||
struct pci_dev *npdev = vdev->pdev;
|
||||
struct device_node *npu_node = pci_device_to_OF_node(npdev);
|
||||
struct pci_controller *hose = pci_bus_to_host(npdev->bus);
|
||||
u64 mmio_atsd = 0;
|
||||
u64 tgt = 0;
|
||||
u32 link_speed = 0xff;
|
||||
|
||||
/*
|
||||
* PCI config space does not tell us about NVLink presense but
|
||||
* platform does, use this.
|
||||
*/
|
||||
if (!pnv_pci_get_gpu_dev(vdev->pdev))
|
||||
return -ENODEV;
|
||||
|
||||
if (of_property_read_u32(npu_node, "memory-region", &mem_phandle))
|
||||
return -ENODEV;
|
||||
|
||||
/*
|
||||
* NPU2 normally has 8 ATSD registers (for concurrency) and 6 links
|
||||
* so we can allocate one register per link, using nvlink index as
|
||||
* a key.
|
||||
* There is always at least one ATSD register so as long as at least
|
||||
* NVLink bridge #0 is passed to the guest, ATSD will be available.
|
||||
*/
|
||||
nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
|
||||
if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
|
||||
&nvlink_index)))
|
||||
return -ENODEV;
|
||||
|
||||
if (of_property_read_u64_index(hose->dn, "ibm,mmio-atsd", nvlink_index,
|
||||
&mmio_atsd)) {
|
||||
if (of_property_read_u64_index(hose->dn, "ibm,mmio-atsd", 0,
|
||||
&mmio_atsd)) {
|
||||
dev_warn(&vdev->pdev->dev, "No available ATSD found\n");
|
||||
mmio_atsd = 0;
|
||||
} else {
|
||||
dev_warn(&vdev->pdev->dev,
|
||||
"Using fallback ibm,mmio-atsd[0] for ATSD.\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (of_property_read_u64(npu_node, "ibm,device-tgt-addr", &tgt)) {
|
||||
dev_warn(&vdev->pdev->dev, "No ibm,device-tgt-addr found\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(npu_node, "ibm,nvlink-speed", &link_speed)) {
|
||||
dev_warn(&vdev->pdev->dev, "No ibm,nvlink-speed found\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
data->mmio_atsd = mmio_atsd;
|
||||
data->gpu_tgt = tgt;
|
||||
data->link_speed = link_speed;
|
||||
if (data->mmio_atsd) {
|
||||
data->base = memremap(data->mmio_atsd, SZ_64K, MEMREMAP_WT);
|
||||
if (!data->base) {
|
||||
ret = -ENOMEM;
|
||||
goto free_exit;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* We want to expose the capability even if this specific NVLink
|
||||
* did not get its own ATSD register because capabilities
|
||||
* belong to VFIO regions and normally there will be ATSD register
|
||||
* assigned to the NVLink bridge.
|
||||
*/
|
||||
ret = vfio_pci_register_dev_region(vdev,
|
||||
PCI_VENDOR_ID_IBM |
|
||||
VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
|
||||
VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD,
|
||||
&vfio_pci_npu2_regops,
|
||||
data->mmio_atsd ? PAGE_SIZE : 0,
|
||||
VFIO_REGION_INFO_FLAG_READ |
|
||||
VFIO_REGION_INFO_FLAG_WRITE |
|
||||
VFIO_REGION_INFO_FLAG_MMAP,
|
||||
data);
|
||||
if (ret)
|
||||
goto free_exit;
|
||||
|
||||
return 0;
|
||||
|
||||
free_exit:
|
||||
if (data->base)
|
||||
memunmap(data->base);
|
||||
kfree(data);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -199,20 +199,6 @@ static inline int vfio_pci_igd_init(struct vfio_pci_device *vdev)
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_VFIO_PCI_NVLINK2
|
||||
extern int vfio_pci_nvdia_v100_nvlink2_init(struct vfio_pci_device *vdev);
|
||||
extern int vfio_pci_ibm_npu2_init(struct vfio_pci_device *vdev);
|
||||
#else
|
||||
static inline int vfio_pci_nvdia_v100_nvlink2_init(struct vfio_pci_device *vdev)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int vfio_pci_ibm_npu2_init(struct vfio_pci_device *vdev)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_S390
|
||||
extern int vfio_pci_info_zdev_add_caps(struct vfio_pci_device *vdev,
|
||||
|
||||
@ -333,17 +333,10 @@ struct vfio_region_info_cap_type {
|
||||
#define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3)
|
||||
|
||||
/* 10de vendor PCI sub-types */
|
||||
/*
|
||||
* NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space.
|
||||
*/
|
||||
#define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1)
|
||||
/* subtype 1 was VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM, don't use */
|
||||
|
||||
/* 1014 vendor PCI sub-types */
|
||||
/*
|
||||
* IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU
|
||||
* to do TLB invalidation on a GPU.
|
||||
*/
|
||||
#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1)
|
||||
/* subtype 1 was VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD, don't use */
|
||||
|
||||
/* sub-types for VFIO_REGION_TYPE_GFX */
|
||||
#define VFIO_REGION_SUBTYPE_GFX_EDID (1)
|
||||
@ -637,32 +630,9 @@ struct vfio_device_migration_info {
|
||||
*/
|
||||
#define VFIO_REGION_INFO_CAP_MSIX_MAPPABLE 3
|
||||
|
||||
/*
|
||||
* Capability with compressed real address (aka SSA - small system address)
|
||||
* where GPU RAM is mapped on a system bus. Used by a GPU for DMA routing
|
||||
* and by the userspace to associate a NVLink bridge with a GPU.
|
||||
*/
|
||||
#define VFIO_REGION_INFO_CAP_NVLINK2_SSATGT 4
|
||||
/* subtype 4 was VFIO_REGION_INFO_CAP_NVLINK2_SSATGT, don't use */
|
||||
|
||||
struct vfio_region_info_cap_nvlink2_ssatgt {
|
||||
struct vfio_info_cap_header header;
|
||||
__u64 tgt;
|
||||
};
|
||||
|
||||
/*
|
||||
* Capability with an NVLink link speed. The value is read by
|
||||
* the NVlink2 bridge driver from the bridge's "ibm,nvlink-speed"
|
||||
* property in the device tree. The value is fixed in the hardware
|
||||
* and failing to provide the correct value results in the link
|
||||
* not working with no indication from the driver why.
|
||||
*/
|
||||
#define VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD 5
|
||||
|
||||
struct vfio_region_info_cap_nvlink2_lnkspd {
|
||||
struct vfio_info_cap_header header;
|
||||
__u32 link_speed;
|
||||
__u32 __pad;
|
||||
};
|
||||
/* subtype 5 was VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD, don't use */
|
||||
|
||||
/**
|
||||
* VFIO_DEVICE_GET_IRQ_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 9,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user