i2c: rk3x: reword according to newest specification

Change the wording of this driver wrt. the newest I2C v7 and SMBus 3.2
specifications and replace "master/slave" with more appropriate terms.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
This commit is contained in:
Wolfram Sang 2024-07-06 13:20:42 +02:00 committed by Andi Shyti
parent e1571b1fb4
commit b340db7351

View File

@ -28,8 +28,8 @@
/* Register Map */
#define REG_CON 0x00 /* control register */
#define REG_CLKDIV 0x04 /* clock divisor register */
#define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */
#define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */
#define REG_MRXADDR 0x08 /* target address for REGISTER_TX */
#define REG_MRXRADDR 0x0c /* target register address for REGISTER_TX */
#define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
#define REG_MRXCNT 0x14 /* number of bytes to be received */
#define REG_IEN 0x18 /* interrupt enable */
@ -68,8 +68,8 @@ enum {
/* REG_IEN/REG_IPD bits */
#define REG_INT_BTF BIT(0) /* a byte was transmitted */
#define REG_INT_BRF BIT(1) /* a byte was received */
#define REG_INT_MBTF BIT(2) /* master data transmit finished */
#define REG_INT_MBRF BIT(3) /* master data receive finished */
#define REG_INT_MBTF BIT(2) /* controller data transmit finished */
#define REG_INT_MBRF BIT(3) /* controller data receive finished */
#define REG_INT_START BIT(4) /* START condition generated */
#define REG_INT_STOP BIT(5) /* STOP condition generated */
#define REG_INT_NAKRCV BIT(6) /* NACK received */
@ -184,7 +184,7 @@ struct rk3x_i2c_soc_data {
* @wait: the waitqueue to wait for i2c transfer
* @busy: the condition for the event to wait for
* @msg: current i2c message
* @addr: addr of i2c slave device
* @addr: addr of i2c target device
* @mode: mode of i2c transfer
* @is_last_msg: flag determines whether it is the last msg in this transfer
* @state: state of i2c transfer
@ -979,7 +979,7 @@ static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
/*
* The I2C adapter can issue a small (len < 4) write packet before
* reading. This speeds up SMBus-style register reads.
* The MRXADDR/MRXRADDR hold the slave address and the slave register
* The MRXADDR/MRXRADDR hold the target address and the target register
* address in this case.
*/
@ -1016,7 +1016,7 @@ static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
addr |= 1; /* set read bit */
/*
* We have to transmit the slave addr first. Use
* We have to transmit the target addr first. Use
* MOD_REGISTER_TX for that purpose.
*/
i2c->mode = REG_CON_MOD_REGISTER_TX;
@ -1160,9 +1160,9 @@ static u32 rk3x_i2c_func(struct i2c_adapter *adap)
}
static const struct i2c_algorithm rk3x_i2c_algorithm = {
.master_xfer = rk3x_i2c_xfer,
.master_xfer_atomic = rk3x_i2c_xfer_polling,
.functionality = rk3x_i2c_func,
.xfer = rk3x_i2c_xfer,
.xfer_atomic = rk3x_i2c_xfer_polling,
.functionality = rk3x_i2c_func,
};
static const struct rk3x_i2c_soc_data rv1108_soc_data = {