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ARM: SoC updates for 6.3

Browse Source 
The majority of the changes are for the OMAP2 platform, mostly
 removing some dead code that got left behind from previous cleanups.
 
 Aside from that, there are very minor updates and correctness fixes for
 Zynq, i.MX, Samsung, Broadcom, AT91, ep93xx, and OMAP1.
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Merge tag 'arm-soc-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC updates from Arnd Bergmann:
 "The majority of the changes are for the OMAP2 platform, mostly
  removing some dead code that got left behind from previous cleanups.

  Aside from that, there are very minor updates and correctness fixes
  for Zynq, i.MX, Samsung, Broadcom, AT91, ep93xx, and OMAP1"

* tag 'arm-soc-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (26 commits)
  dt-bindings: soc: samsung: exynos-pmu: allow phys as child
  ARM: imx: mach-imx6ul: add imx6ulz support
  ARM: imx: Call ida_simple_remove() for ida_simple_get
  arm64: drop redundant "ARMv8" from Kconfig option title
  ARM: ep93xx: Convert to use descriptors for GPIO LEDs
  ARM: s3c: fix s3c64xx_set_timer_source prototype
  ARM: OMAP2+: Fix spelling typos in comment
  ARM: OMAP2+: Remove unneeded #include <linux/pinctrl/machine.h>
  ARM: OMAP2+: Remove unneeded #include <linux/pinctrl/pinmux.h>
  ARM: OMAP1: call platform_device_put() in error case in omap1_dm_timer_init()
  ARM: BCM63xx: remove useless goto statement
  ARM: omap2: make functions static
  ARM: omap2: remove unused omap2_pm_init
  ARM: omap2: remove unused declarations
  ARM: omap2: remove unused functions
  ARM: omap2: smartreflex: remove on_init control
  ARM: omap2: remove APLL control
  ARM: omap2: simplify clock2xxx header
  ARM: omap2: remove unused omap_hwmod_reset.c
  ARM: omap2: remove unused headers
  ...
This commit is contained in:
Linus Torvalds 2023-02-20 15:36:37 -08:00
commit b32c6e029c
77 changed files with 155 additions and 1578 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
View File

@ -31,7 +31,8 @@ select:
properties:
compatible:
items:
oneOf:
- items:
- enum:
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
@ -45,6 +46,13 @@ properties:
- samsung,exynos850-pmu
- samsung-s5pv210-pmu
- const: syscon
- items:
- enum:
- samsung,exynos5250-pmu
- samsung,exynos5420-pmu
- samsung,exynos5433-pmu
- const: simple-mfd
- const: syscon
reg:
maxItems: 1
@ -64,6 +72,10 @@ properties:
minItems: 1
maxItems: 32
dp-phy:
$ref: /schemas/phy/samsung,dp-video-phy.yaml
unevaluatedProperties: false
interrupt-controller:
description:
Some PMUs are capable of behaving as an interrupt controller (mostly
@ -74,6 +86,10 @@ properties:
Must be identical to the that of the parent interrupt controller.
const: 3
mipi-phy:
$ref: /schemas/phy/samsung,mipi-video-phy.yaml
unevaluatedProperties: false
reboot-mode:
$ref: /schemas/power/reset/syscon-reboot-mode.yaml
type: object
@ -117,6 +133,23 @@ allOf:
- clock-names
- clocks
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5250-pmu
- samsung,exynos5420-pmu
- samsung,exynos5433-pmu
then:
properties:
dp-phy: true
mipi-phy: true
else:
properties:
dp-phy: false
mipi-phy: false
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
@ -130,4 +163,14 @@ examples:
#clock-cells = <1>;
clock-names = "clkout16";
clocks = <&clock CLK_FIN_PLL>;
dp-phy {
compatible = "samsung,exynos5250-dp-video-phy";
#phy-cells = <0>;
};
mipi-phy {
compatible = "samsung,s5pv210-mipi-video-phy";
#phy-cells = <1>;
};
};

3
arch/arm/mach-bcm/bcm63xx_smp.c
View File

@ -142,8 +142,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu,
*/
ret = bcm63xx_pmb_power_on_cpu(dn);
of_node_put(dn);
if (ret)
goto out;
out:
iounmap(bootlut_base);

13
arch/arm/mach-ep93xx/core.c
View File

@ -426,10 +426,8 @@ void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
static const struct gpio_led ep93xx_led_pins[] __initconst = {
{
.name = "platform:grled",
.gpio = EP93XX_GPIO_LINE_GRLED,
}, {
.name = "platform:rdled",
.gpio = EP93XX_GPIO_LINE_RDLED,
},
};
@ -438,6 +436,16 @@ static const struct gpio_led_platform_data ep93xx_led_data __initconst = {
.leds = ep93xx_led_pins,
};
static struct gpiod_lookup_table ep93xx_leds_gpio_table = {
.dev_id = "leds-gpio",
.table = {
/* Use local offsets on gpiochip/port "E" */
GPIO_LOOKUP_IDX("E", 0, NULL, 0, GPIO_ACTIVE_HIGH),
GPIO_LOOKUP_IDX("E", 1, NULL, 1, GPIO_ACTIVE_HIGH),
{ }
},
};
/*************************************************************************
* EP93xx pwm peripheral handling
*************************************************************************/
@ -990,6 +998,7 @@ struct device __init *ep93xx_init_devices(void)
platform_device_register(&ep93xx_ohci_device);
platform_device_register(&ep93xx_wdt_device);
gpiod_add_lookup_table(&ep93xx_leds_gpio_table);
gpio_led_register_device(-1, &ep93xx_led_data);
return parent;

1
arch/arm/mach-imx/mach-imx6ul.c
View File

@ -63,6 +63,7 @@ static void __init imx6ul_init_late(void)
static const char * const imx6ul_dt_compat[] __initconst = {
"fsl,imx6ul",
"fsl,imx6ull",
"fsl,imx6ulz",
NULL,
};

24
arch/arm/mach-imx/mmdc.c
View File

@ -99,6 +99,7 @@ struct mmdc_pmu {
cpumask_t cpu;
struct hrtimer hrtimer;
unsigned int active_events;
int id;
struct device *dev;
struct perf_event *mmdc_events[MMDC_NUM_COUNTERS];
struct hlist_node node;
@ -433,8 +434,6 @@ static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer)
static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
void __iomem *mmdc_base, struct device *dev)
{
int mmdc_num;
*pmu_mmdc = (struct mmdc_pmu) {
.pmu = (struct pmu) {
.task_ctx_nr = perf_invalid_context,
@ -452,15 +451,16 @@ static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc,
.active_events = 0,
};
mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
pmu_mmdc->id = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL);
return mmdc_num;
return pmu_mmdc->id;
}
static int imx_mmdc_remove(struct platform_device *pdev)
{
struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev);
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
perf_pmu_unregister(&pmu_mmdc->pmu);
iounmap(pmu_mmdc->mmdc_base);
@ -474,7 +474,6 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
{
struct mmdc_pmu *pmu_mmdc;
char *name;
int mmdc_num;
int ret;
const struct of_device_id *of_id =
of_match_device(imx_mmdc_dt_ids, &pdev->dev);
@ -497,14 +496,14 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
cpuhp_mmdc_state = ret;
}
mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
if (mmdc_num == 0)
name = "mmdc";
else
name = devm_kasprintf(&pdev->dev,
GFP_KERNEL, "mmdc%d", mmdc_num);
ret = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev);
if (ret < 0)
goto pmu_free;
name = devm_kasprintf(&pdev->dev,
GFP_KERNEL, "mmdc%d", ret);
pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,
@ -525,6 +524,7 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b
pmu_register_err:
pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret);
ida_simple_remove(&mmdc_ida, pmu_mmdc->id);
cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node);
hrtimer_cancel(&pmu_mmdc->hrtimer);
pmu_free:

2
arch/arm/mach-omap1/timer.c
View File

@ -158,7 +158,7 @@ err_free_pdata:
kfree(pdata);
err_free_pdev:
platform_device_unregister(pdev);
platform_device_put(pdev);
return ret;
}

3
arch/arm/mach-omap2/Makefile
View File

@ -7,7 +7,7 @@
obj-y := id.o io.o control.o devices.o fb.o pm.o \
common.o dma.o omap-headsmp.o sram.o
hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
hwmod-common = omap_hwmod.o \
omap_hwmod_common_data.o \
omap_hwmod_common_ipblock_data.o \
omap_device.o display.o hdq1w.o \
@ -80,7 +80,6 @@ obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
omap-4-5-pm-common += pm44xx.o

2
arch/arm/mach-omap2/board-n8x0.c
View File

@ -504,7 +504,7 @@ static void __init n8x0_mmc_init(void)
}
#else
static struct omap_mmc_platform_data mmc1_data;
void __init n8x0_mmc_init(void)
static void __init n8x0_mmc_init(void)
{
}
#endif /* CONFIG_MMC_OMAP */

1
arch/arm/mach-omap2/clkt2xxx_dpllcore.c
View File

@ -20,6 +20,7 @@
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/clk/ti.h>
#include <linux/io.h>
#include "clock.h"

12
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
View File

@ -39,6 +39,8 @@
#include "sdrc.h"
#include "sram.h"
static u16 cpu_mask;
const struct prcm_config *curr_prcm_set;
const struct prcm_config *rate_table;
@ -55,7 +57,7 @@ static unsigned long sys_ck_rate;
*
* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
*/
unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
static unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
unsigned long parent_rate)
{
return curr_prcm_set->mpu_speed;
@ -68,7 +70,7 @@ unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
* just uses the ARM rates.
*/
long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
static long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
const struct prcm_config *ptr;
@ -92,7 +94,7 @@ long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
}
/* Sets basic clocks based on the specified rate */
int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
static int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
u32 cur_rate, done_rate, bypass = 0;
@ -167,7 +169,7 @@ int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
* global to point to the active rate set when found; otherwise, sets
* it to NULL. No return value;
*/
void omap2xxx_clkt_vps_check_bootloader_rates(void)
static void omap2xxx_clkt_vps_check_bootloader_rates(void)
{
const struct prcm_config *prcm = NULL;
unsigned long rate;
@ -193,7 +195,7 @@ void omap2xxx_clkt_vps_check_bootloader_rates(void)
* sys_ck rate, but before the virt_prcm_set clock rate is
* recalculated. No return value.
*/
void omap2xxx_clkt_vps_late_init(void)
static void omap2xxx_clkt_vps_late_init(void)
{
struct clk *c;

2
arch/arm/mach-omap2/clock.c
View File

@ -36,8 +36,6 @@
#include "cm-regbits-34xx.h"
#include "common.h"
u16 cpu_mask;
/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000

7
arch/arm/mach-omap2/clock.h
View File

@ -63,13 +63,6 @@
extern struct ti_clk_ll_ops omap_clk_ll_ops;
extern u16 cpu_mask;
extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_omap2_dflt;
extern struct clk_functions omap2_clk_functions;
int __init omap2_clk_setup_ll_ops(void);
void __init ti_clk_init_features(void);

29
arch/arm/mach-omap2/clock2xxx.h
View File

@ -12,35 +12,6 @@
#include <linux/clk-provider.h>
#include "clock.h"
unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
unsigned long parent_rate);
int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate);
long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate);
unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
unsigned long parent_rate);
unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
unsigned long parent_rate);
void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
unsigned long omap2xxx_clk_get_core_rate(void);
u32 omap2xxx_get_sysclkdiv(void);
void omap2xxx_clk_prepare_for_reboot(void);
void omap2xxx_clkt_vps_check_bootloader_rates(void);
void omap2xxx_clkt_vps_late_init(void);
#ifdef CONFIG_SOC_OMAP2420
int omap2420_clk_init(void);
#else
#define omap2420_clk_init() do { } while(0)
#endif
#ifdef CONFIG_SOC_OMAP2430
int omap2430_clk_init(void);
#else
#define omap2430_clk_init() do { } while(0)
#endif
extern struct clk_hw *dclk_hw;
#endif

21
arch/arm/mach-omap2/clock3xxx.h
View File

@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* OMAP3-common clock function prototypes and macros
*
* Copyright (C) 2007-2010 Texas Instruments, Inc.
* Copyright (C) 2007-2010 Nokia Corporation
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
int omap3xxx_clk_init(void);
int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
unsigned long parent_rate);
extern struct clk *sdrc_ick_p;
extern struct clk *arm_fck_p;
extern const struct clkops clkops_noncore_dpll_ops;
#endif

44
arch/arm/mach-omap2/clockdomain.c
View File

@ -831,7 +831,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
* -EINVAL if @clkdm is NULL or if clockdomain does not support
* software-initiated sleep; 0 upon success.
*/
int clkdm_sleep_nolock(struct clockdomain *clkdm)
static int clkdm_sleep_nolock(struct clockdomain *clkdm)
{
int ret;
@ -885,7 +885,7 @@ int clkdm_sleep(struct clockdomain *clkdm)
* -EINVAL if @clkdm is NULL or if the clockdomain does not support
* software-controlled wakeup; 0 upon success.
*/
int clkdm_wakeup_nolock(struct clockdomain *clkdm)
static int clkdm_wakeup_nolock(struct clockdomain *clkdm)
{
int ret;
@ -1043,46 +1043,6 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
pwrdm_unlock(clkdm->pwrdm.ptr);
}
/**
* clkdm_in_hwsup - is clockdomain @clkdm have hardware-supervised idle enabled?
* @clkdm: struct clockdomain *
*
* Returns true if clockdomain @clkdm currently has
* hardware-supervised idle enabled, or false if it does not or if
* @clkdm is NULL. It is only valid to call this function after
* clkdm_init() has been called. This function does not actually read
* bits from the hardware; it instead tests an in-memory flag that is
* changed whenever the clockdomain code changes the auto-idle mode.
*/
bool clkdm_in_hwsup(struct clockdomain *clkdm)
{
bool ret;
if (!clkdm)
return false;
ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
return ret;
}
/**
* clkdm_missing_idle_reporting - can @clkdm enter autoidle even if in use?
* @clkdm: struct clockdomain *
*
* Returns true if clockdomain @clkdm has the
* CLKDM_MISSING_IDLE_REPORTING flag set, or false if not or @clkdm is
* null. More information is available in the documentation for the
* CLKDM_MISSING_IDLE_REPORTING macro.
*/
bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
{
if (!clkdm)
return false;
return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
}
/* Public autodep handling functions (deprecated) */
/**

4
arch/arm/mach-omap2/clockdomain.h
View File

@ -203,12 +203,8 @@ void clkdm_allow_idle_nolock(struct clockdomain *clkdm);
void clkdm_allow_idle(struct clockdomain *clkdm);
void clkdm_deny_idle_nolock(struct clockdomain *clkdm);
void clkdm_deny_idle(struct clockdomain *clkdm);
bool clkdm_in_hwsup(struct clockdomain *clkdm);
bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
int clkdm_wakeup_nolock(struct clockdomain *clkdm);
int clkdm_wakeup(struct clockdomain *clkdm);
int clkdm_sleep_nolock(struct clockdomain *clkdm);
int clkdm_sleep(struct clockdomain *clkdm);
int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);

99
arch/arm/mach-omap2/cm2xxx.c
View File

@ -95,103 +95,6 @@ void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
_omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
}
/*
* APLL control
*/
static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
{
u32 v;
v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
v &= ~mask;
v |= m << __ffs(mask);
omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
}
void omap2xxx_cm_set_apll54_disable_autoidle(void)
{
_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
OMAP24XX_AUTO_54M_MASK);
}
void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
{
_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
OMAP24XX_AUTO_54M_MASK);
}
void omap2xxx_cm_set_apll96_disable_autoidle(void)
{
_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
OMAP24XX_AUTO_96M_MASK);
}
void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
{
_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
OMAP24XX_AUTO_96M_MASK);
}
/* Enable an APLL if off */
static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit)
{
u32 v, m;
m = EN_APLL_LOCKED << enable_bit;
v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
if (v & m)
return 0; /* apll already enabled */
v |= m;
omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
omap2xxx_cm_wait_module_ready(0, PLL_MOD, 1, status_bit);
/*
* REVISIT: Should we return an error code if
* omap2xxx_cm_wait_module_ready() fails?
*/
return 0;
}
/* Stop APLL */
static void _omap2xxx_apll_disable(u8 enable_bit)
{
u32 v;
v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
v &= ~(EN_APLL_LOCKED << enable_bit);
omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
}
/* Enable an APLL if off */
int omap2xxx_cm_apll54_enable(void)
{
return _omap2xxx_apll_enable(OMAP24XX_EN_54M_PLL_SHIFT,
OMAP24XX_ST_54M_APLL_SHIFT);
}
/* Enable an APLL if off */
int omap2xxx_cm_apll96_enable(void)
{
return _omap2xxx_apll_enable(OMAP24XX_EN_96M_PLL_SHIFT,
OMAP24XX_ST_96M_APLL_SHIFT);
}
/* Stop APLL */
void omap2xxx_cm_apll54_disable(void)
{
_omap2xxx_apll_disable(OMAP24XX_EN_54M_PLL_SHIFT);
}
/* Stop APLL */
void omap2xxx_cm_apll96_disable(void)
{
_omap2xxx_apll_disable(OMAP24XX_EN_96M_PLL_SHIFT);
}
/**
* omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
* @idlest_reg: CM_IDLEST* virtual address
@ -242,7 +145,7 @@ static int omap2xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
* (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
* success or -EBUSY if the module doesn't enable in time.
*/
int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
static int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
u8 idlest_shift)
{
int ena = 0, i = 0;

7
arch/arm/mach-omap2/cm2xxx.h
View File

@ -46,13 +46,6 @@
extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
u8 idlest_shift);
extern int omap2xxx_cm_fclks_active(void);
extern int omap2xxx_cm_mpu_retention_allowed(void);
extern u32 omap2xxx_cm_get_core_clk_src(void);

5
arch/arm/mach-omap2/cm2xxx_3xxx.h
View File

@ -93,11 +93,6 @@ static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
}
extern int omap2xxx_cm_apll54_enable(void);
extern void omap2xxx_cm_apll54_disable(void);
extern int omap2xxx_cm_apll96_enable(void);
extern void omap2xxx_cm_apll96_disable(void);
#endif
/* CM register bits shared between 24XX and 3430 */

28
arch/arm/mach-omap2/common.h
View File

@ -38,24 +38,12 @@
#include <asm/hardware/cache-l2x0.h>
#include "i2c.h"
#include "serial.h"
#include "usb.h"
#define OMAP_INTC_START NR_IRQS
extern int (*omap_pm_soc_init)(void);
int omap_pm_nop_init(void);
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
int omap2_pm_init(void);
#else
static inline int omap2_pm_init(void)
{
return 0;
}
#endif
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
int omap3_pm_init(void);
#else
@ -90,12 +78,6 @@ static inline int amx3_common_pm_init(void)
}
#endif
extern void omap2_init_common_infrastructure(void);
extern void omap_init_time(void);
extern void omap3_secure_sync32k_timer_init(void);
extern void omap3_gptimer_timer_init(void);
extern void omap4_local_timer_init(void);
#ifdef CONFIG_CACHE_L2X0
int omap_l2_cache_init(void);
#define OMAP_L2C_AUX_CTRL (L2C_AUX_CTRL_SHARED_OVERRIDE | \
@ -123,9 +105,7 @@ static inline void omap5_realtime_timer_init(void)
void omap2420_init_early(void);
void omap2430_init_early(void);
void omap3430_init_early(void);
void omap35xx_init_early(void);
void omap3630_init_early(void);
void omap3_init_early(void); /* Do not use this one */
void am33xx_init_early(void);
void am35xx_init_early(void);
void ti814x_init_early(void);
@ -136,12 +116,9 @@ void omap4430_init_early(void);
void omap5_init_early(void);
void omap3_init_late(void);
void omap4430_init_late(void);
void omap2420_init_late(void);
void omap2430_init_late(void);
void ti81xx_init_late(void);
void am33xx_init_late(void);
void omap5_init_late(void);
int omap2_common_pm_late_init(void);
void dra7xx_init_early(void);
void dra7xx_init_late(void);
@ -235,11 +212,6 @@ void __init ti81xx_map_io(void);
} \
})
extern struct device *omap2_get_mpuss_device(void);
extern struct device *omap2_get_iva_device(void);
extern struct device *omap2_get_l3_device(void);
extern struct device *omap4_get_dsp_device(void);
void omap_gic_of_init(void);
#ifdef CONFIG_CACHE_L2X0

73
arch/arm/mach-omap2/control.c
View File

@ -226,68 +226,7 @@ void omap3_ctrl_write_boot_mode(u8 bootmode)
#endif
/**
* omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
* @bootaddr: physical address of the boot loader
*
* Set boot address for the boot loader of a supported processor
* when a power ON sequence occurs.
*/
void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
{
u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
0;
if (!offset) {
pr_err("%s: unsupported omap type\n", __func__);
return;
}
omap_ctrl_writel(bootaddr, offset);
}
/**
* omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
* @bootmode: 8-bit value to pass to some boot code
*
* Sets boot mode for the boot loader of a supported processor
* when a power ON sequence occurs.
*/
void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
{
u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
0;
if (!offset) {
pr_err("%s: unsupported omap type\n", __func__);
return;
}
omap_ctrl_writel(bootmode, offset);
}
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
/*
* Clears the scratchpad contents in case of cold boot-
* called during bootup
*/
void omap3_clear_scratchpad_contents(void)
{
u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
void __iomem *v_addr;
u32 offset = 0;
v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
if (omap3xxx_prm_clear_global_cold_reset()) {
for ( ; offset <= max_offset; offset += 0x4)
writel_relaxed(0x0, (v_addr + offset));
}
}
/* Populate the scratchpad structure with restore structure */
void omap3_save_scratchpad_contents(void)
{
@ -846,15 +785,3 @@ of_node_put:
return ret;
}
/**
* omap3_control_legacy_iomap_init - legacy iomap init for clock providers
*
* Legacy iomap init for clock provider. Needed only by legacy boot mode,
* where the base addresses are not parsed from DT, but still required
* by the clock driver to be setup properly.
*/
void __init omap3_control_legacy_iomap_init(void)
{
omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
}

5
arch/arm/mach-omap2/control.h
View File

@ -512,8 +512,6 @@ extern void omap_ctrl_writeb(u8 val, u16 offset);
extern void omap_ctrl_writew(u16 val, u16 offset);
extern void omap_ctrl_writel(u32 val, u16 offset);
extern void omap3_save_scratchpad_contents(void);
extern void omap3_clear_scratchpad_contents(void);
extern void omap3_restore(void);
extern void omap3_restore_es3(void);
extern void omap3_restore_3630(void);
@ -521,14 +519,11 @@ extern u32 omap3_arm_context[128];
extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
extern void omap3_ctrl_write_boot_mode(u8 bootmode);
extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
extern void omap3630_ctrl_disable_rta(void);
extern int omap3_ctrl_save_padconf(void);
void omap3_ctrl_init(void);
int omap2_control_base_init(void);
int omap_control_init(void);
void __init omap3_control_legacy_iomap_init(void);
#else
#define omap_ctrl_readb(x) 0
#define omap_ctrl_readw(x) 0

1
arch/arm/mach-omap2/devices.c
View File

@ -14,7 +14,6 @@
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/pinctrl/machine.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>

2
arch/arm/mach-omap2/id.c
View File

@ -117,7 +117,7 @@ static struct omap_id omap_ids[] __initdata = {
static void __iomem *tap_base;
static u16 tap_prod_id;
void omap_get_die_id(struct omap_die_id *odi)
static void omap_get_die_id(struct omap_die_id *odi)
{
if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);

2
arch/arm/mach-omap2/id.h
View File

@ -14,6 +14,4 @@ struct omap_die_id {
u32 id_3;
};
void omap_get_die_id(struct omap_die_id *odi);
#endif

21
arch/arm/mach-omap2/io.c
View File

@ -32,11 +32,8 @@
#include "clockdomain.h"
#include "common.h"
#include "clock.h"
#include "clock2xxx.h"
#include "clock3xxx.h"
#include "sdrc.h"
#include "control.h"
#include "serial.h"
#include "sram.h"
#include "cm2xxx.h"
#include "cm3xxx.h"
@ -438,11 +435,6 @@ void __init omap2420_init_early(void)
omap_clk_soc_init = omap2420_dt_clk_init;
rate_table = omap2420_rate_table;
}
void __init omap2420_init_late(void)
{
omap_pm_soc_init = omap2_pm_init;
}
#endif
#ifdef CONFIG_SOC_OMAP2430
@ -462,11 +454,6 @@ void __init omap2430_init_early(void)
omap_clk_soc_init = omap2430_dt_clk_init;
rate_table = omap2430_rate_table;
}
void __init omap2430_init_late(void)
{
omap_pm_soc_init = omap2_pm_init;
}
#endif
/*
@ -474,7 +461,7 @@ void __init omap2430_init_late(void)
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
*/
#ifdef CONFIG_ARCH_OMAP3
void __init omap3_init_early(void)
static void __init omap3_init_early(void)
{
omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
@ -497,12 +484,6 @@ void __init omap3430_init_early(void)
omap_clk_soc_init = omap3430_dt_clk_init;
}
void __init omap35xx_init_early(void)
{
omap3_init_early();
omap_clk_soc_init = omap3430_dt_clk_init;
}
void __init omap3630_init_early(void)
{
omap3_init_early();

7
arch/arm/mach-omap2/omap-secure.c
View File

@ -118,11 +118,6 @@ int __init omap_secure_ram_reserve_memblock(void)
return 0;
}
phys_addr_t omap_secure_ram_mempool_base(void)
{
return omap_secure_memblock_base;
}
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
u32 omap3_save_secure_ram(void *addr, int size)
{
@ -157,7 +152,7 @@ u32 omap3_save_secure_ram(void *addr, int size)
* NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
* it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
*/
u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
static u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
u32 arg1, u32 arg2, u32 arg3, u32 arg4)
{
static u32 param[5];

3
arch/arm/mach-omap2/omap-secure.h
View File

@ -70,13 +70,10 @@ extern void omap_smccc_smc(u32 fn, u32 arg);
extern void omap_smc1(u32 fn, u32 arg);
extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
extern phys_addr_t omap_secure_ram_mempool_base(void);
extern int omap_secure_ram_reserve_memblock(void);
extern u32 save_secure_ram_context(u32 args_pa);
extern u32 omap3_save_secure_ram(void *save_regs, int size);
extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
u32 arg1, u32 arg2, u32 arg3, u32 arg4);
extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);

1
arch/arm/mach-omap2/omap4-common.c
View File

@ -140,6 +140,7 @@ static int __init omap4_sram_init(void)
__func__);
else
sram_sync = (void __iomem *)gen_pool_alloc(sram_pool, PAGE_SIZE);
of_node_put(np);
return 0;
}

74
arch/arm/mach-omap2/omap_device.c
View File

@ -39,6 +39,12 @@
#include "omap_device.h"
#include "omap_hwmod.h"
static struct omap_device *omap_device_alloc(struct platform_device *pdev,
struct omap_hwmod **ohs, int oh_cnt);
static void omap_device_delete(struct omap_device *od);
static struct dev_pm_domain omap_device_fail_pm_domain;
static struct dev_pm_domain omap_device_pm_domain;
/* Private functions */
static void _add_clkdev(struct omap_device *od, const char *clk_alias,
@ -285,34 +291,6 @@ static int _omap_device_idle_hwmods(struct omap_device *od)
/* Public functions for use by core code */
/**
* omap_device_get_context_loss_count - get lost context count
* @pdev: The platform device to update.
*
* Using the primary hwmod, query the context loss count for this
* device.
*
* Callers should consider context for this device lost any time this
* function returns a value different than the value the caller got
* the last time it called this function.
*
* If any hwmods exist for the omap_device associated with @pdev,
* return the context loss counter for that hwmod, otherwise return
* zero.
*/
int omap_device_get_context_loss_count(struct platform_device *pdev)
{
struct omap_device *od;
u32 ret = 0;
od = to_omap_device(pdev);
if (od->hwmods_cnt)
ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
return ret;
}
/**
* omap_device_alloc - allocate an omap_device
* @pdev: platform_device that will be included in this omap_device
@ -324,7 +302,7 @@ int omap_device_get_context_loss_count(struct platform_device *pdev)
*
* Returns an struct omap_device pointer or ERR_PTR() on error;
*/
struct omap_device *omap_device_alloc(struct platform_device *pdev,
static struct omap_device *omap_device_alloc(struct platform_device *pdev,
struct omap_hwmod **ohs, int oh_cnt)
{
int ret = -ENOMEM;
@ -361,7 +339,7 @@ oda_exit1:
return ERR_PTR(ret);
}
void omap_device_delete(struct omap_device *od)
static void omap_device_delete(struct omap_device *od)
{
if (!od)
return;
@ -453,14 +431,14 @@ static int _od_resume_noirq(struct device *dev)
#define _od_resume_noirq NULL
#endif
struct dev_pm_domain omap_device_fail_pm_domain = {
static struct dev_pm_domain omap_device_fail_pm_domain = {
.ops = {
SET_RUNTIME_PM_OPS(_od_fail_runtime_suspend,
_od_fail_runtime_resume, NULL)
}
};
struct dev_pm_domain omap_device_pm_domain = {
static struct dev_pm_domain omap_device_pm_domain = {
.ops = {
SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
NULL)
@ -592,38 +570,6 @@ int omap_device_deassert_hardreset(struct platform_device *pdev,
return ret;
}
/**
* omap_device_get_by_hwmod_name() - convert a hwmod name to
* device pointer.
* @oh_name: name of the hwmod device
*
* Returns back a struct device * pointer associated with a hwmod
* device represented by a hwmod_name
*/
struct device *omap_device_get_by_hwmod_name(const char *oh_name)
{
struct omap_hwmod *oh;
if (!oh_name) {
WARN(1, "%s: no hwmod name!\n", __func__);
return ERR_PTR(-EINVAL);
}
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
WARN(1, "%s: no hwmod for %s\n", __func__,
oh_name);
return ERR_PTR(-ENODEV);
}
if (!oh->od) {
WARN(1, "%s: no omap_device for %s\n", __func__,
oh_name);
return ERR_PTR(-ENODEV);
}
return &oh->od->pdev->dev;
}
static struct notifier_block platform_nb = {
.notifier_call = _omap_device_notifier_call,
};

14
arch/arm/mach-omap2/omap_device.h
View File

@ -25,9 +25,6 @@
#include "omap_hwmod.h"
extern struct dev_pm_domain omap_device_pm_domain;
extern struct dev_pm_domain omap_device_fail_pm_domain;
/* omap_device._state values */
#define OMAP_DEVICE_STATE_UNKNOWN 0
#define OMAP_DEVICE_STATE_ENABLED 1
@ -66,17 +63,6 @@ struct omap_device {
int omap_device_enable(struct platform_device *pdev);
int omap_device_idle(struct platform_device *pdev);
/* Core code interface */
struct omap_device *omap_device_alloc(struct platform_device *pdev,
struct omap_hwmod **ohs, int oh_cnt);
void omap_device_delete(struct omap_device *od);
struct device *omap_device_get_by_hwmod_name(const char *oh_name);
/* OMAP PM interface */
int omap_device_get_context_loss_count(struct platform_device *pdev);
/* Other */
int omap_device_assert_hardreset(struct platform_device *pdev,

94
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -3054,6 +3054,8 @@ int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
return 0;
}
static int __init omap_hwmod_setup_one(const char *oh_name);
/**
* _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
* @oh: pointer to the hwmod currently being set up (usually not the MPU)
@ -3084,7 +3086,7 @@ static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh)
* registered omap_hwmod. Also calls _setup() on each hwmod. Returns
* -EINVAL upon error or 0 upon success.
*/
int __init omap_hwmod_setup_one(const char *oh_name)
static int __init omap_hwmod_setup_one(const char *oh_name)
{
struct omap_hwmod *oh;
@ -3763,55 +3765,6 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
* IP block data retrieval functions
*/
/**
* omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
* @oh: struct omap_hwmod *
*
* Return the powerdomain pointer associated with the OMAP module
* @oh's main clock. If @oh does not have a main clk, return the
* powerdomain associated with the interface clock associated with the
* module's MPU port. (XXX Perhaps this should use the SDMA port
* instead?) Returns NULL on error, or a struct powerdomain * on
* success.
*/
struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
{
struct clk *c;
struct omap_hwmod_ocp_if *oi;
struct clockdomain *clkdm;
struct clk_hw_omap *clk;
struct clk_hw *hw;
if (!oh)
return NULL;
if (oh->clkdm)
return oh->clkdm->pwrdm.ptr;
if (oh->_clk) {
c = oh->_clk;
} else {
oi = _find_mpu_rt_port(oh);
if (!oi)
return NULL;
c = oi->_clk;
}
hw = __clk_get_hw(c);
if (!hw)
return NULL;
clk = to_clk_hw_omap(hw);
if (!clk)
return NULL;
clkdm = clk->clkdm;
if (!clkdm)
return NULL;
return clkdm->pwrdm.ptr;
}
/**
* omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU)
* @oh: struct omap_hwmod *
@ -3977,32 +3930,6 @@ ohsps_unlock:
return ret;
}
/**
* omap_hwmod_get_context_loss_count - get lost context count
* @oh: struct omap_hwmod *
*
* Returns the context loss count of associated @oh
* upon success, or zero if no context loss data is available.
*
* On OMAP4, this queries the per-hwmod context loss register,
* assuming one exists. If not, or on OMAP2/3, this queries the
* enclosing powerdomain context loss count.
*/
int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
{
struct powerdomain *pwrdm;
int ret = 0;
if (soc_ops.get_context_lost)
return soc_ops.get_context_lost(oh);
pwrdm = omap_hwmod_get_pwrdm(oh);
if (pwrdm)
ret = pwrdm_get_context_loss_count(pwrdm);
return ret;
}
/**
* omap_hwmod_init - initialize the hwmod code
*
@ -4054,18 +3981,3 @@ void __init omap_hwmod_init(void)
inited = true;
}
/**
* omap_hwmod_get_main_clk - get pointer to main clock name
* @oh: struct omap_hwmod *
*
* Returns the main clock name assocated with @oh upon success,
* or NULL if @oh is NULL.
*/
const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh)
{
if (!oh)
return NULL;
return oh->main_clk;
}

21
arch/arm/mach-omap2/omap_hwmod.h
View File

@ -615,7 +615,6 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name);
int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
void *data);
int __init omap_hwmod_setup_one(const char *name);
int omap_hwmod_parse_module_range(struct omap_hwmod *oh,
struct device_node *np,
struct resource *res);
@ -638,12 +637,6 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
int omap_hwmod_softreset(struct omap_hwmod *oh);
int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags);
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
const char *name, struct resource *res);
struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
int omap_hwmod_for_each_by_class(const char *classname,
@ -652,12 +645,9 @@ int omap_hwmod_for_each_by_class(const char *classname,
void *user);
int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
extern void __init omap_hwmod_init(void);
const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
#else /* CONFIG_OMAP_HWMOD */
static inline int
@ -669,13 +659,6 @@ omap_hwmod_for_each_by_class(const char *classname,
}
#endif /* CONFIG_OMAP_HWMOD */
/*
*
*/
void omap_hwmod_rtc_unlock(struct omap_hwmod *oh);
void omap_hwmod_rtc_lock(struct omap_hwmod *oh);
/*
* Chip variant-specific hwmod init routines - XXX should be converted
* to use initcalls once the initial boot ordering is straightened out
@ -683,12 +666,8 @@ void omap_hwmod_rtc_lock(struct omap_hwmod *oh);
extern int omap2420_hwmod_init(void);
extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
extern int am33xx_hwmod_init(void);
extern int dm814x_hwmod_init(void);
extern int dm816x_hwmod_init(void);
extern int dra7xx_hwmod_init(void);
int am43xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);

1
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

@ -22,7 +22,6 @@
#include "prm-regbits-24xx.h"
#include "i2c.h"
#include "mmc.h"
#include "serial.h"
#include "wd_timer.h"
/*

2
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
View File

@ -62,7 +62,7 @@ struct omap_hwmod_class iva_hwmod_class = {
.name = "iva",
};
struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
static struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x14,
.syss_offs = 0x18,

1
arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
View File

@ -13,7 +13,6 @@
#include "omap_hwmod.h"
#include "l3_2xxx.h"
#include "l4_2xxx.h"
#include "serial.h"
#include "omap_hwmod_common_data.h"

12
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
View File

@ -30,7 +30,7 @@ static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_dispc_hwmod_class = {
static struct omap_hwmod_class omap2_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap2_dispc_sysc,
};
@ -47,7 +47,7 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
static struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
.name = "timer",
.sysc = &omap2xxx_timer_sysc,
};
@ -67,7 +67,7 @@ static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
static struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap2xxx_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable,
@ -189,12 +189,6 @@ struct omap_hwmod omap2xxx_mpu_hwmod = {
.main_clk = "mpu_ck",
};
/* IVA2 */
struct omap_hwmod omap2xxx_iva_hwmod = {
.name = "iva",
.class = &iva_hwmod_class,
};
/* timer3 */
struct omap_hwmod omap2xxx_timer3_hwmod = {
.name = "timer3",

1
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -27,7 +27,6 @@
#include "i2c.h"
#include "wd_timer.h"
#include "serial.h"
/*
* OMAP3xxx hardware module integration data

6
arch/arm/mach-omap2/omap_hwmod_common_data.h
View File

@ -20,7 +20,6 @@ extern struct omap_hwmod omap2xxx_l3_main_hwmod;
extern struct omap_hwmod omap2xxx_l4_core_hwmod;
extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
extern struct omap_hwmod omap2xxx_mpu_hwmod;
extern struct omap_hwmod omap2xxx_iva_hwmod;
extern struct omap_hwmod omap2xxx_timer3_hwmod;
extern struct omap_hwmod omap2xxx_timer4_hwmod;
extern struct omap_hwmod omap2xxx_timer5_hwmod;
@ -60,7 +59,6 @@ extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
@ -86,14 +84,10 @@ extern struct omap_hwmod_class mpu_hwmod_class;
extern struct omap_hwmod_class iva_hwmod_class;
extern struct omap_hwmod_class omap2_uart_class;
extern struct omap_hwmod_class omap2_dss_hwmod_class;
extern struct omap_hwmod_class omap2_dispc_hwmod_class;
extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
extern struct omap_hwmod_class omap2_venc_hwmod_class;
extern struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc;
extern struct omap_hwmod_class omap2_hdq1w_class;
extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mcspi_class;

98
arch/arm/mach-omap2/omap_hwmod_reset.c
View File

@ -1,98 +0,0 @@
/*
* OMAP IP block custom reset and preprogramming stubs
*
* Copyright (C) 2012 Texas Instruments, Inc.
* Paul Walmsley
*
* A small number of IP blocks need custom reset and preprogramming
* functions. The stubs in this file provide a standard way for the
* hwmod code to call these functions, which are to be located under
* drivers/.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include "omap_hwmod.h"
#include "common.h"
#define OMAP_RTC_STATUS_REG 0x44
#define OMAP_RTC_KICK0_REG 0x6c
#define OMAP_RTC_KICK1_REG 0x70
#define OMAP_RTC_KICK0_VALUE 0x83E70B13
#define OMAP_RTC_KICK1_VALUE 0x95A4F1E0
#define OMAP_RTC_STATUS_BUSY BIT(0)
#define OMAP_RTC_MAX_READY_TIME 50
/**
* omap_rtc_wait_not_busy - Wait for the RTC BUSY flag
* @oh: struct omap_hwmod *
*
* For updating certain RTC registers, the MPU must wait
* for the BUSY status in OMAP_RTC_STATUS_REG to become zero.
* Once the BUSY status is zero, there is a 15 microseconds access
* period in which the MPU can program.
*/
static void omap_rtc_wait_not_busy(struct omap_hwmod *oh)
{
int i;
/* BUSY may stay active for 1/32768 second (~30 usec) */
omap_test_timeout(omap_hwmod_read(oh, OMAP_RTC_STATUS_REG)
& OMAP_RTC_STATUS_BUSY, OMAP_RTC_MAX_READY_TIME, i);
/* now we have ~15 microseconds to read/write various registers */
}
/**
* omap_hwmod_rtc_unlock - Unlock the Kicker mechanism.
* @oh: struct omap_hwmod *
*
* RTC IP have kicker feature. This prevents spurious writes to its registers.
* In order to write into any of the RTC registers, KICK values has te be
* written in respective KICK registers. This is needed for hwmod to write into
* sysconfig register.
*/
void omap_hwmod_rtc_unlock(struct omap_hwmod *oh)
{
unsigned long flags;
local_irq_save(flags);
omap_rtc_wait_not_busy(oh);
omap_hwmod_write(OMAP_RTC_KICK0_VALUE, oh, OMAP_RTC_KICK0_REG);
omap_hwmod_write(OMAP_RTC_KICK1_VALUE, oh, OMAP_RTC_KICK1_REG);
local_irq_restore(flags);
}
/**
* omap_hwmod_rtc_lock - Lock the Kicker mechanism.
* @oh: struct omap_hwmod *
*
* RTC IP have kicker feature. This prevents spurious writes to its registers.
* Once the RTC registers are written, KICK mechanism needs to be locked,
* in order to prevent any spurious writes. This function locks back the RTC
* registers once hwmod completes its write into sysconfig register.
*/
void omap_hwmod_rtc_lock(struct omap_hwmod *oh)
{
unsigned long flags;
local_irq_save(flags);
omap_rtc_wait_not_busy(oh);
omap_hwmod_write(0x0, oh, OMAP_RTC_KICK0_REG);
omap_hwmod_write(0x0, oh, OMAP_RTC_KICK1_REG);
local_irq_restore(flags);
}

5
arch/arm/mach-omap2/omap_opp_data.h
View File

@ -71,11 +71,6 @@ struct omap_opp_def {
.vp_errgain = _errgain \
}
/* Use this to initialize the default table */
extern int __init omap_init_opp_table(struct omap_opp_def *opp_def,
u32 opp_def_size);
extern struct omap_volt_data omap34xx_vddmpu_volt_data[];
extern struct omap_volt_data omap34xx_vddcore_volt_data[];
extern struct omap_volt_data omap36xx_vddmpu_volt_data[];

87
arch/arm/mach-omap2/omap_phy_internal.c
View File

@ -19,7 +19,6 @@
#include "soc.h"
#include "control.h"
#include "usb.h"
#define CONTROL_DEV_CONF 0x300
#define PHY_PD 0x1
@ -52,89 +51,3 @@ static int __init omap4430_phy_power_down(void)
return 0;
}
omap_early_initcall(omap4430_phy_power_down);
void am35x_musb_reset(void)
{
u32 regval;
/* Reset the musb interface */
regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
regval |= AM35XX_USBOTGSS_SW_RST;
omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
regval &= ~AM35XX_USBOTGSS_SW_RST;
omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
}
void am35x_musb_phy_power(u8 on)
{
unsigned long timeout = jiffies + msecs_to_jiffies(100);
u32 devconf2;
if (on) {
/*
* Start the on-chip PHY and its PLL.
*/
devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
devconf2 |= CONF2_PHY_PLLON;
omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
pr_info("Waiting for PHY clock good...\n");
while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
& CONF2_PHYCLKGD)) {
cpu_relax();
if (time_after(jiffies, timeout)) {
pr_err("musb PHY clock good timed out\n");
break;
}
}
} else {
/*
* Power down the on-chip PHY.
*/
devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
devconf2 &= ~CONF2_PHY_PLLON;
devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
}
}
void am35x_musb_clear_irq(void)
{
u32 regval;
regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
regval |= AM35XX_USBOTGSS_INT_CLR;
omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
}
void am35x_set_mode(u8 musb_mode)
{
u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
devconf2 &= ~CONF2_OTGMODE;
switch (musb_mode) {
case MUSB_HOST: /* Force VBUS valid, ID = 0 */
devconf2 |= CONF2_FORCE_HOST;
break;
case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
devconf2 |= CONF2_FORCE_DEVICE;
break;
case MUSB_OTG: /* Don't override the VBUS/ID comparators */
devconf2 |= CONF2_NO_OVERRIDE;
break;
default:
pr_info("Unsupported mode %u\n", musb_mode);
}
omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
}

8
arch/arm/mach-omap2/pm.c
View File

@ -54,12 +54,6 @@ static struct omap2_oscillator oscillator = {
.shutdown_time = ULONG_MAX,
};
void omap_pm_setup_oscillator(u32 tstart, u32 tshut)
{
oscillator.startup_time = tstart;
oscillator.shutdown_time = tshut;
}
void omap_pm_get_oscillator(u32 *tstart, u32 *tshut)
{
if (!tstart || !tshut)
@ -140,7 +134,7 @@ int __maybe_unused omap_pm_nop_init(void)
int (*omap_pm_soc_init)(void);
int __init omap2_common_pm_late_init(void)
static int __init omap2_common_pm_late_init(void)
{
int error;

25
arch/arm/mach-omap2/pm.h
View File

@ -32,20 +32,6 @@ extern void omap3_pm_off_mode_enable(int);
extern void omap_sram_idle(void);
extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
#if defined(CONFIG_PM_OPP)
extern int omap3_opp_init(void);
extern int omap4_opp_init(void);
#else
static inline int omap3_opp_init(void)
{
return -EINVAL;
}
static inline int omap4_opp_init(void)
{
return -EINVAL;
}
#endif
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
@ -58,9 +44,6 @@ extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
#endif /* CONFIG_PM_DEBUG */
/* 24xx */
extern void omap24xx_idle_loop_suspend(void);
extern unsigned int omap24xx_idle_loop_suspend_sz;
extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
void __iomem *sdrc_power);
extern unsigned int omap24xx_cpu_suspend_sz;
@ -110,20 +93,16 @@ extern u16 pm44xx_errata;
#ifdef CONFIG_POWER_AVS_OMAP
extern int omap_devinit_smartreflex(void);
extern void omap_enable_smartreflex_on_init(void);
#else
static inline int omap_devinit_smartreflex(void)
{
return -EINVAL;
}
static inline void omap_enable_smartreflex_on_init(void) {}
#endif
#ifdef CONFIG_TWL4030_CORE
extern int omap3_twl_init(void);
extern int omap4_twl_init(void);
extern int omap3_twl_set_sr_bit(bool enable);
#else
static inline int omap3_twl_init(void)
{
@ -145,13 +124,9 @@ static inline int omap4_cpcap_init(void)
#endif
#ifdef CONFIG_PM
extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);
extern void omap_pm_setup_sr_i2c_pcb_length(u32 mm);
#else
static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { }
static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = *tshut = 0; }
static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { }
#endif
#ifdef CONFIG_SUSPEND

312
arch/arm/mach-omap2/pm24xx.c
View File

@ -1,312 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP2 Power Management Routines
*
* Copyright (C) 2005 Texas Instruments, Inc.
* Copyright (C) 2006-2008 Nokia Corporation
*
* Written by:
* Richard Woodruff <r-woodruff2@ti.com>
* Tony Lindgren
* Juha Yrjola
* Amit Kucheria <amit.kucheria@nokia.com>
* Igor Stoppa <igor.stoppa@nokia.com>
*
* Based on pm.c for omap1
*/
#include <linux/cpu_pm.h>
#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <asm/fncpy.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
#include <asm/system_misc.h>
#include <linux/omap-dma.h>
#include "soc.h"
#include "common.h"
#include "clock.h"
#include "prm2xxx.h"
#include "prm-regbits-24xx.h"
#include "cm2xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "sram.h"
#include "pm.h"
#include "control.h"
#include "powerdomain.h"
#include "clockdomain.h"
static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
void __iomem *sdrc_power);
static struct powerdomain *mpu_pwrdm, *core_pwrdm;
static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
static struct clk *osc_ck, *emul_ck;
static int omap2_enter_full_retention(void)
{
u32 l;
/* There is 1 reference hold for all children of the oscillator
* clock, the following will remove it. If no one else uses the
* oscillator itself it will be disabled if/when we enter retention
* mode.
*/
clk_disable(osc_ck);
/* Clear old wake-up events */
/* REVISIT: These write to reserved bits? */
omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
/* Workaround to kill USB */
l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
/* One last check for pending IRQs to avoid extra latency due
* to sleeping unnecessarily. */
if (omap_irq_pending())
goto no_sleep;
/* Jump to SRAM suspend code */
omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
OMAP_SDRC_REGADDR(SDRC_POWER));
no_sleep:
clk_enable(osc_ck);
/* clear CORE wake-up events */
omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
/* MPU domain wake events */
omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
return 0;
}
static int sti_console_enabled;
static int omap2_allow_mpu_retention(void)
{
if (!omap2xxx_cm_mpu_retention_allowed())
return 0;
if (sti_console_enabled)
return 0;
return 1;
}
static void omap2_enter_mpu_retention(void)
{
const int zero = 0;
/* The peripherals seem not to be able to wake up the MPU when
* it is in retention mode. */
if (omap2_allow_mpu_retention()) {
/* REVISIT: These write to reserved bits? */
omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
/* Try to enter MPU retention */
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
} else {
/* Block MPU retention */
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
}
/* WFI */
asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
}
static int omap2_can_sleep(void)
{
if (omap2xxx_cm_fclks_active())
return 0;
if (__clk_is_enabled(osc_ck))
return 0;
return 1;
}
static void omap2_pm_idle(void)
{
int error;
if (omap_irq_pending())
return;
error = cpu_cluster_pm_enter();
if (error || !omap2_can_sleep()) {
omap2_enter_mpu_retention();
goto out_cpu_cluster_pm;
}
omap2_enter_full_retention();
out_cpu_cluster_pm:
cpu_cluster_pm_exit();
}
static void __init prcm_setup_regs(void)
{
int i, num_mem_banks;
struct powerdomain *pwrdm;
/*
* Enable autoidle
* XXX This should be handled by hwmod code or PRCM init code
*/
omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
OMAP2_PRCM_SYSCONFIG_OFFSET);
/*
* Set CORE powerdomain memory banks to retain their contents
* during RETENTION
*/
num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
for (i = 0; i < num_mem_banks; i++)
pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
/* Force-power down DSP, GFX powerdomains */
pwrdm = clkdm_get_pwrdm(dsp_clkdm);
pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
pwrdm = clkdm_get_pwrdm(gfx_clkdm);
pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
/* Enable hardware-supervised idle for all clkdms */
clkdm_for_each(omap_pm_clkdms_setup, NULL);
clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
omap_common_suspend_init(omap2_enter_full_retention);
/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
* stabilisation */
omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
OMAP2_PRCM_CLKSSETUP_OFFSET);
/* Configure automatic voltage transition */
omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
OMAP2_PRCM_VOLTSETUP_OFFSET);
omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
OMAP24XX_MEMRETCTRL_MASK |
(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
/* Enable wake-up events */
omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
WKUP_MOD, PM_WKEN);
/* Enable SYS_CLKEN control when all domains idle */
omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
}
int __init omap2_pm_init(void)
{
u32 l;
printk(KERN_INFO "Power Management for OMAP2 initializing\n");
l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
/* Look up important powerdomains */
mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
if (!mpu_pwrdm)
pr_err("PM: mpu_pwrdm not found\n");
core_pwrdm = pwrdm_lookup("core_pwrdm");
if (!core_pwrdm)
pr_err("PM: core_pwrdm not found\n");
/* Look up important clockdomains */
mpu_clkdm = clkdm_lookup("mpu_clkdm");
if (!mpu_clkdm)
pr_err("PM: mpu_clkdm not found\n");
wkup_clkdm = clkdm_lookup("wkup_clkdm");
if (!wkup_clkdm)
pr_err("PM: wkup_clkdm not found\n");
dsp_clkdm = clkdm_lookup("dsp_clkdm");
if (!dsp_clkdm)
pr_err("PM: dsp_clkdm not found\n");
gfx_clkdm = clkdm_lookup("gfx_clkdm");
if (!gfx_clkdm)
pr_err("PM: gfx_clkdm not found\n");
osc_ck = clk_get(NULL, "osc_ck");
if (IS_ERR(osc_ck)) {
printk(KERN_ERR "could not get osc_ck\n");
return -ENODEV;
}
if (cpu_is_omap242x()) {
emul_ck = clk_get(NULL, "emul_ck");
if (IS_ERR(emul_ck)) {
printk(KERN_ERR "could not get emul_ck\n");
clk_put(osc_ck);
return -ENODEV;
}
}
prcm_setup_regs();
/*
* We copy the assembler sleep/wakeup routines to SRAM.
* These routines need to be in SRAM as that's the only
* memory the MPU can see when it wakes up after the entire
* chip enters idle.
*/
omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
omap24xx_cpu_suspend_sz);
arm_pm_idle = omap2_pm_idle;
return 0;
}

1
arch/arm/mach-omap2/pm33xx-core.c
View File

@ -16,7 +16,6 @@
#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/wkup_m3_ipc.h>
#include <linux/of.h>
#include <linux/rtc.h>

108
arch/arm/mach-omap2/powerdomain.c
View File

@ -37,8 +37,8 @@
#define PWRDM_TRACE_STATES_FLAG (1<<31)
void pwrdms_save_context(void);
void pwrdms_restore_context(void);
static void pwrdms_save_context(void);
static void pwrdms_restore_context(void);
enum {
PWRDM_STATE_NOW = 0,
@ -1148,82 +1148,6 @@ osps_out:
return ret;
}
/**
* pwrdm_get_context_loss_count - get powerdomain's context loss count
* @pwrdm: struct powerdomain * to wait for
*
* Context loss count is the sum of powerdomain off-mode counter, the
* logic off counter and the per-bank memory off counter. Returns negative
* (and WARNs) upon error, otherwise, returns the context loss count.
*/
int pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
{
int i, count;
if (!pwrdm) {
WARN(1, "powerdomain: %s: pwrdm is null\n", __func__);
return -ENODEV;
}
count = pwrdm->state_counter[PWRDM_POWER_OFF];
count += pwrdm->ret_logic_off_counter;
for (i = 0; i < pwrdm->banks; i++)
count += pwrdm->ret_mem_off_counter[i];
/*
* Context loss count has to be a non-negative value. Clear the sign
* bit to get a value range from 0 to INT_MAX.
*/
count &= INT_MAX;
pr_debug("powerdomain: %s: context loss count = %d\n",
pwrdm->name, count);
return count;
}
/**
* pwrdm_can_ever_lose_context - can this powerdomain ever lose context?
* @pwrdm: struct powerdomain *
*
* Given a struct powerdomain * @pwrdm, returns 1 if the powerdomain
* can lose either memory or logic context or if @pwrdm is invalid, or
* returns 0 otherwise. This function is not concerned with how the
* powerdomain registers are programmed (i.e., to go off or not); it's
* concerned with whether it's ever possible for this powerdomain to
* go off while some other part of the chip is active. This function
* assumes that every powerdomain can go to either ON or INACTIVE.
*/
bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm)
{
int i;
if (!pwrdm) {
pr_debug("powerdomain: %s: invalid powerdomain pointer\n",
__func__);
return true;
}
if (pwrdm->pwrsts & PWRSTS_OFF)
return true;
if (pwrdm->pwrsts & PWRSTS_RET) {
if (pwrdm->pwrsts_logic_ret & PWRSTS_OFF)
return true;
for (i = 0; i < pwrdm->banks; i++)
if (pwrdm->pwrsts_mem_ret[i] & PWRSTS_OFF)
return true;
}
for (i = 0; i < pwrdm->banks; i++)
if (pwrdm->pwrsts_mem_on[i] & PWRSTS_OFF)
return true;
return false;
}
/**
* pwrdm_save_context - save powerdomain registers
*
@ -1250,36 +1174,12 @@ static int pwrdm_restore_context(struct powerdomain *pwrdm, void *unused)
return 0;
}
static int pwrdm_lost_power(struct powerdomain *pwrdm, void *unused)
{
int state;
/*
* Power has been lost across all powerdomains, increment the
* counter.
*/
state = pwrdm_read_pwrst(pwrdm);
if (state != PWRDM_POWER_OFF) {
pwrdm->state_counter[state]++;
pwrdm->state_counter[PWRDM_POWER_OFF]++;
}
pwrdm->state = state;
return 0;
}
void pwrdms_save_context(void)
static void pwrdms_save_context(void)
{
pwrdm_for_each(pwrdm_save_context, NULL);
}
void pwrdms_restore_context(void)
static void pwrdms_restore_context(void)
{
pwrdm_for_each(pwrdm_restore_context, NULL);
}
void pwrdms_lost_power(void)
{
pwrdm_for_each(pwrdm_lost_power, NULL);
}

8
arch/arm/mach-omap2/powerdomain.h
View File

@ -208,8 +208,6 @@ struct powerdomain *pwrdm_lookup(const char *name);
int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
void *user);
int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
void *user);
int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
@ -243,8 +241,6 @@ int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
int pwrdm_state_switch(struct powerdomain *pwrdm);
int pwrdm_pre_transition(struct powerdomain *pwrdm);
int pwrdm_post_transition(struct powerdomain *pwrdm);
int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
@ -273,8 +269,4 @@ extern struct powerdomain gfx_omap2_pwrdm;
extern void pwrdm_lock(struct powerdomain *pwrdm);
extern void pwrdm_unlock(struct powerdomain *pwrdm);
extern void pwrdms_save_context(void);
extern void pwrdms_restore_context(void);
extern void pwrdms_lost_power(void);
#endif

1
arch/arm/mach-omap2/prcm-common.h
View File

@ -550,7 +550,6 @@ struct omap_prcm_init_data {
struct device_node *np;
};
extern void omap_prcm_irq_cleanup(void);
extern int omap_prcm_register_chain_handler(
struct omap_prcm_irq_setup *irq_setup);
extern int omap_prcm_event_to_irq(const char *event);

12
arch/arm/mach-omap2/prcm_mpu44xx.c
View File

@ -35,18 +35,6 @@ void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
}
u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
{
u32 v;
v = omap4_prcm_mpu_read_inst_reg(inst, reg);
v &= ~mask;
v |= bits;
omap4_prcm_mpu_write_inst_reg(v, inst, reg);
return v;
}
/**
* omap2_set_globals_prcm_mpu - set the MPU PRCM base address (for early use)
* @prcm_mpu: PRCM_MPU base virtual address

2
arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
View File

@ -26,8 +26,6 @@ extern struct omap_domain_base prcm_mpu_base;
extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
s16 idx);
extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
#endif

4
arch/arm/mach-omap2/prm.h
View File

@ -15,9 +15,7 @@
# ifndef __ASSEMBLER__
extern struct omap_domain_base prm_base;
extern u16 prm_features;
extern void omap2_set_globals_prm(void __iomem *prm);
int omap_prcm_init(void);
int omap2_prm_base_init(void);
int omap2_prcm_base_init(void);
# endif
@ -156,12 +154,10 @@ int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset);
int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
u16 offset, u16 st_offset);
int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
extern u32 prm_read_reset_sources(void);
extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
void omap_prm_reset_system(void);
void omap_prm_reconfigure_io_chain(void);
int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
/*

3
arch/arm/mach-omap2/prm2xxx_3xxx.h
View File

@ -104,9 +104,6 @@ int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
s16 prm_mod, u16 reset_offset,
u16 st_offset);
extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
u8 pwrst);
extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,

5
arch/arm/mach-omap2/prm3xxx.c
View File

@ -32,6 +32,7 @@ static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
static void omap3xxx_prm_ocp_barrier(void);
static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
static void omap3xxx_prm_restore_irqen(u32 *saved_mask);
static void omap3xxx_prm_iva_idle(void);
static const struct omap_prcm_irq omap3_prcm_irqs[] = {
OMAP_PRCM_IRQ("wkup", 0, 0),
@ -268,7 +269,7 @@ static int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
* Toggles the reset signal to modem IP block. Required to allow
* OMAP3430 without stacked modem to idle properly.
*/
void __init omap3_prm_reset_modem(void)
static void __init omap3_prm_reset_modem(void)
{
omap2_prm_write_mod_reg(
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
@ -469,7 +470,7 @@ static u32 omap3xxx_prm_read_reset_sources(void)
* function forces the IVA2 into idle state so it can go
* into retention/off and thus allow full-chip retention/off.
*/
void omap3xxx_prm_iva_idle(void)
static void omap3xxx_prm_iva_idle(void)
{
/* ensure IVA2 clock is disabled */
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);

2
arch/arm/mach-omap2/prm3xxx.h
View File

@ -138,8 +138,6 @@ extern void omap3_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
void omap3xxx_prm_iva_idle(void);
void omap3_prm_reset_modem(void);
int omap3xxx_prm_clear_global_cold_reset(void);
void omap3_prm_save_scratchpad_contents(u32 *ptr);
void omap3_prm_init_pm(bool has_uart4, bool has_iva);

55
arch/arm/mach-omap2/prm_common.c
View File

@ -187,7 +187,7 @@ int omap_prcm_event_to_irq(const char *name)
*
* No return value.
*/
void omap_prcm_irq_cleanup(void)
static void omap_prcm_irq_cleanup(void)
{
unsigned int irq;
int i;
@ -344,41 +344,6 @@ err:
return -ENOMEM;
}
/**
* omap2_set_globals_prm - set the PRM base address (for early use)
* @prm: PRM base virtual address
*
* XXX Will be replaced when the PRM/CM drivers are completed.
*/
void __init omap2_set_globals_prm(void __iomem *prm)
{
prm_base.va = prm;
}
/**
* prm_read_reset_sources - return the sources of the SoC's last reset
*
* Return a u32 bitmask representing the reset sources that caused the
* SoC to reset. The low-level per-SoC functions called by this
* function remap the SoC-specific reset source bits into an
* OMAP-common set of reset source bits, defined in
* arch/arm/mach-omap2/prm.h. Returns the standardized reset source
* u32 bitmask from the hardware upon success, or returns (1 <<
* OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
* function was registered.
*/
u32 prm_read_reset_sources(void)
{
u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
if (prm_ll_data->read_reset_sources)
ret = prm_ll_data->read_reset_sources();
else
WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
return ret;
}
/**
* prm_was_any_context_lost_old - was device context lost? (old API)
* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
@ -488,22 +453,6 @@ int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
return prm_ll_data->is_hardreset_asserted(shift, part, prm_mod, offset);
}
/**
* omap_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
*
* Clear any previously-latched I/O wakeup events and ensure that the
* I/O wakeup gates are aligned with the current mux settings.
* Calls SoC specific I/O chain reconfigure function if available,
* otherwise does nothing.
*/
void omap_prm_reconfigure_io_chain(void)
{
if (!prcm_irq_setup || !prcm_irq_setup->reconfigure_io_chain)
return;
prcm_irq_setup->reconfigure_io_chain();
}
/**
* omap_prm_reset_system - trigger global SW reset
*
@ -740,7 +689,7 @@ static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
* on the DT data. Returns 0 in success, negative error value
* otherwise.
*/
int __init omap2_prm_base_init(void)
static int __init omap2_prm_base_init(void)
{
struct device_node *np;
const struct of_device_id *match;

51
arch/arm/mach-omap2/sdrc.c
View File

@ -45,7 +45,7 @@ static struct omap2_sms_regs sms_context;
*
* Save SMS registers that need to be restored after off mode.
*/
void omap2_sms_save_context(void)
static void omap2_sms_save_context(void)
{
sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
}
@ -60,55 +60,6 @@ void omap2_sms_restore_context(void)
sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
}
/**
* omap2_sdrc_get_params - return SDRC register values for a given clock rate
* @r: SDRC clock rate (in Hz)
* @sdrc_cs0: chip select 0 ram timings **
* @sdrc_cs1: chip select 1 ram timings **
*
* Return pre-calculated values for the SDRC_ACTIM_CTRLA,
* SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
* structs,for a given SDRC clock rate 'r'.
* These parameters control various timing delays in the SDRAM controller
* that are expressed in terms of the number of SDRC clock cycles to
* wait; hence the clock rate dependency.
*
* Supports 2 different timing parameters for both chip selects.
*
* Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
* Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
* as sdrc_init_params_cs_0.
*
* Fills in the struct omap_sdrc_params * for each chip select.
* Returns 0 upon success or -1 upon failure.
*/
int omap2_sdrc_get_params(unsigned long r,
struct omap_sdrc_params **sdrc_cs0,
struct omap_sdrc_params **sdrc_cs1)
{
struct omap_sdrc_params *sp0, *sp1;
if (!sdrc_init_params_cs0)
return -1;
sp0 = sdrc_init_params_cs0;
sp1 = sdrc_init_params_cs1;
while (sp0->rate && sp0->rate != r) {
sp0++;
if (sdrc_init_params_cs1)
sp1++;
}
if (!sp0->rate)
return -1;
*sdrc_cs0 = sp0;
*sdrc_cs1 = sp1;
return 0;
}
void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms)
{
omap2_sdrc_base = sdrc;

5
arch/arm/mach-omap2/sdrc.h
View File

@ -80,10 +80,6 @@ static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1) {};
#endif
int omap2_sdrc_get_params(unsigned long r,
struct omap_sdrc_params **sdrc_cs0,
struct omap_sdrc_params **sdrc_cs1);
void omap2_sms_save_context(void);
void omap2_sms_restore_context(void);
struct memory_timings {
@ -95,7 +91,6 @@ struct memory_timings {
};
extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
struct omap_sdrc_params *rx51_get_sdram_timings(void);
u32 omap2xxx_sdrc_dll_is_unlocked(void);
u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);

66
arch/arm/mach-omap2/serial.h
View File

@ -1,66 +0,0 @@
/*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* OMAP2 serial ports */
#define OMAP2_UART1_BASE 0x4806a000
#define OMAP2_UART2_BASE 0x4806c000
#define OMAP2_UART3_BASE 0x4806e000
/* OMAP3 serial ports */
#define OMAP3_UART1_BASE OMAP2_UART1_BASE
#define OMAP3_UART2_BASE OMAP2_UART2_BASE
#define OMAP3_UART3_BASE 0x49020000
#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
/* OMAP4 serial ports */
#define OMAP4_UART1_BASE OMAP2_UART1_BASE
#define OMAP4_UART2_BASE OMAP2_UART2_BASE
#define OMAP4_UART3_BASE 0x48020000
#define OMAP4_UART4_BASE 0x4806e000
/* TI81XX serial ports */
#define TI81XX_UART1_BASE 0x48020000
#define TI81XX_UART2_BASE 0x48022000
#define TI81XX_UART3_BASE 0x48024000
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
/* AM33XX serial port */
#define AM33XX_UART1_BASE 0x44E09000
/* OMAP5 serial ports */
#define OMAP5_UART1_BASE OMAP2_UART1_BASE
#define OMAP5_UART2_BASE OMAP2_UART2_BASE
#define OMAP5_UART3_BASE OMAP4_UART3_BASE
#define OMAP5_UART4_BASE OMAP4_UART4_BASE
#define OMAP5_UART5_BASE 0x48066000
#define OMAP5_UART6_BASE 0x48068000
/* External port on Zoom2/3 */
#define ZOOM_UART_BASE 0x10000000
#define ZOOM_UART_VIRT 0xfa400000
#define OMAP_PORT_SHIFT 2
#define ZOOM_PORT_SHIFT 1
#define OMAP24XX_BASE_BAUD (48000000/16)
#ifndef __ASSEMBLER__
struct omap_board_data;
struct omap_uart_port_info;
extern void omap_serial_init(void);
extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
extern void omap_serial_init_port(struct omap_board_data *bdata,
struct omap_uart_port_info *platform_data);
#endif

2
arch/arm/mach-omap2/sleep34xx.S
View File

@ -465,7 +465,7 @@ l2_inv_gp:
mov r12, #0x2
smc #0 @ Call SMI monitor (smieq)
logic_l1_restore:
adr r0, l2dis_3630_offset @ adress for offset
adr r0, l2dis_3630_offset @ address for offset
ldr r1, [r0] @ value for offset
ldr r1, [r0, r1] @ value at l2dis_3630
cmp r1, #0x1 @ Test if L2 re-enable needed on 3630

13
arch/arm/mach-omap2/sr_device.c
View File

@ -26,8 +26,6 @@
#include "control.h"
#include "pm.h"
static bool sr_enable_on_init;
/* Read EFUSE values from control registers for OMAP3430 */
static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
struct omap_sr_data *sr_data)
@ -144,8 +142,6 @@ static int __init sr_init_by_name(const char *name, const char *voltdm)
sr_set_nvalues(volt_data, sr_data);
sr_data->enable_on_init = sr_enable_on_init;
exit:
i++;
@ -173,15 +169,6 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
}
#endif
/*
* API to be called from board files to enable smartreflex
* autocompensation at init.
*/
void __init omap_enable_smartreflex_on_init(void)
{
sr_enable_on_init = true;
}
static const char * const omap4_sr_instances[] = {
"mpu",
"iva",

4
arch/arm/mach-omap2/sram.h
View File

@ -17,10 +17,6 @@ extern int __init omap_sram_init(void);
extern void *omap_sram_push(void *funcp, unsigned long size);
/* Do not use these */
extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
extern unsigned long omap24xx_sram_reprogram_clock_sz;
extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
u32 base_cs, u32 force_unlock);
extern unsigned long omap242x_sram_ddr_init_sz;

1
arch/arm/mach-omap2/timer.c
View File

@ -76,6 +76,7 @@ static void __init realtime_counter_init(void)
}
rate = clk_get_rate(sys_clk);
clk_put(sys_clk);
if (soc_is_dra7xx()) {
/*

6
arch/arm/mach-omap2/usb-tusb6010.c
View File

@ -97,7 +97,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
}
/* tusb driver calls this when it changes the chip's clocking */
int tusb6010_platform_retime(unsigned is_refclk)
static int tusb6010_platform_retime(unsigned is_refclk)
{
static const char error[] =
KERN_ERR "tusb6010 %s retime error %d\n";
@ -121,7 +121,6 @@ int tusb6010_platform_retime(unsigned is_refclk)
done:
return status;
}
EXPORT_SYMBOL_GPL(tusb6010_platform_retime);
static struct resource tusb_resources[] = {
/* Order is significant! The start/end fields
@ -154,8 +153,7 @@ static struct platform_device tusb_device = {
/* this may be called only from board-*.c setup code */
int __init
tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
int __init tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
unsigned ps_refclk, unsigned waitpin,
unsigned async, unsigned sync,
unsigned irq, unsigned dmachan)

71
arch/arm/mach-omap2/usb.h
View File

@ -1,71 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/platform_data/usb-omap.h>
/* AM35x */
/* USB 2.0 PHY Control */
#define CONF2_PHY_GPIOMODE (1 << 23)
#define CONF2_OTGMODE (3 << 14)
#define CONF2_NO_OVERRIDE (0 << 14)
#define CONF2_FORCE_HOST (1 << 14)
#define CONF2_FORCE_DEVICE (2 << 14)
#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
#define CONF2_SESENDEN (1 << 13)
#define CONF2_VBDTCTEN (1 << 12)
#define CONF2_REFFREQ_24MHZ (2 << 8)
#define CONF2_REFFREQ_26MHZ (7 << 8)
#define CONF2_REFFREQ_13MHZ (6 << 8)
#define CONF2_REFFREQ (0xf << 8)
#define CONF2_PHYCLKGD (1 << 7)
#define CONF2_VBUSSENSE (1 << 6)
#define CONF2_PHY_PLLON (1 << 5)
#define CONF2_RESET (1 << 4)
#define CONF2_PHYPWRDN (1 << 3)
#define CONF2_OTGPWRDN (1 << 2)
#define CONF2_DATPOL (1 << 1)
/* TI81XX specific definitions */
#define USBCTRL0 0x620
#define USBSTAT0 0x624
/* TI816X PHY controls bits */
#define TI816X_USBPHY0_NORMAL_MODE (1 << 0)
#define TI816X_USBPHY_REFCLK_OSC (1 << 8)
/* TI814X PHY controls bits */
#define USBPHY_CM_PWRDN (1 << 0)
#define USBPHY_OTG_PWRDN (1 << 1)
#define USBPHY_CHGDET_DIS (1 << 2)
#define USBPHY_CHGDET_RSTRT (1 << 3)
#define USBPHY_SRCONDM (1 << 4)
#define USBPHY_SINKONDP (1 << 5)
#define USBPHY_CHGISINK_EN (1 << 6)
#define USBPHY_CHGVSRC_EN (1 << 7)
#define USBPHY_DMPULLUP (1 << 8)
#define USBPHY_DPPULLUP (1 << 9)
#define USBPHY_CDET_EXTCTL (1 << 10)
#define USBPHY_GPIO_MODE (1 << 12)
#define USBPHY_DPOPBUFCTL (1 << 13)
#define USBPHY_DMOPBUFCTL (1 << 14)
#define USBPHY_DPINPUT (1 << 15)
#define USBPHY_DMINPUT (1 << 16)
#define USBPHY_DPGPIO_PD (1 << 17)
#define USBPHY_DMGPIO_PD (1 << 18)
#define USBPHY_OTGVDET_EN (1 << 19)
#define USBPHY_OTGSESSEND_EN (1 << 20)
#define USBPHY_DATA_POLARITY (1 << 23)
struct usbhs_phy_data {
int port; /* 1 indexed port number */
int reset_gpio;
int vcc_gpio;
bool vcc_polarity; /* 1 active high, 0 active low */
};
extern void usb_musb_init(struct omap_musb_board_data *board_data);
extern void usbhs_init(struct usbhs_omap_platform_data *pdata);
extern int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys);
extern void am35x_musb_reset(void);
extern void am35x_musb_phy_power(u8 on);
extern void am35x_musb_clear_irq(void);
extern void am35x_set_mode(u8 musb_mode);

15
arch/arm/mach-omap2/vc.c
View File

@ -802,21 +802,6 @@ static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
return voltdm->pmic->uv_to_vsel(uvolt);
}
#ifdef CONFIG_PM
/**
* omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
* @mm: length of the PCB trace in millimetres
*
* Sets the PCB trace length for the I2C channel. By default uses 63mm.
* This is needed for properly calculating the capacitance value for
* the PCB trace, and for setting the SR I2C channel timing parameters.
*/
void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm)
{
sr_i2c_pcb_length = mm;
}
#endif
void __init omap_vc_init_channel(struct voltagedomain *voltdm)
{
struct omap_vc_channel *vc = voltdm->vc;

2
arch/arm/mach-omap2/voltage.c
View File

@ -67,7 +67,7 @@ unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
* This API should be called by the kernel to do the voltage scaling
* for a particular voltage domain during DVFS.
*/
int voltdm_scale(struct voltagedomain *voltdm,
static int voltdm_scale(struct voltagedomain *voltdm,
unsigned long target_volt)
{
int ret, i;

2
arch/arm/mach-omap2/voltage.h
View File

@ -163,8 +163,6 @@ extern void omap54xx_voltagedomains_init(void);
struct voltagedomain *voltdm_lookup(const char *name);
void voltdm_init(struct voltagedomain **voltdm_list);
int voltdm_add_pwrdm(struct voltagedomain *voltdm, struct powerdomain *pwrdm);
int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
void voltdm_reset(struct voltagedomain *voltdm);
unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
#endif

3
arch/arm/mach-s3c/s3c64xx.c
View File

@ -165,7 +165,8 @@ static struct samsung_pwm_variant s3c64xx_pwm_variant = {
.tclk_mask = (1 << 7) | (1 << 6) | (1 << 5),
};
void __init s3c64xx_set_timer_source(unsigned int event, unsigned int source)
void __init s3c64xx_set_timer_source(enum s3c64xx_timer_mode event,
enum s3c64xx_timer_mode source)
{
s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));

1
arch/arm/mach-zynq/slcr.c
View File

@ -213,6 +213,7 @@ int __init zynq_early_slcr_init(void)
zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
if (IS_ERR(zynq_slcr_regmap)) {
pr_err("%s: failed to find zynq-slcr\n", __func__);
of_node_put(np);
return -ENODEV;
}

10
arch/arm64/Kconfig.platforms
View File

@ -95,7 +95,7 @@ config ARCH_BITMAIN
This enables support for the Bitmain SoC Family.
config ARCH_EXYNOS
bool "ARMv8 based Samsung Exynos SoC family"
bool "Samsung Exynos SoC family"
select COMMON_CLK_SAMSUNG
select CLKSRC_EXYNOS_MCT
select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
@ -108,7 +108,7 @@ config ARCH_EXYNOS
This enables support for ARMv8 based Samsung Exynos SoC family.
config ARCH_SPARX5
bool "ARMv8 based Microchip Sparx5 SoC family"
bool "Microchip Sparx5 SoC family"
select PINCTRL
select DW_APB_TIMER_OF
help
@ -199,13 +199,13 @@ menuconfig ARCH_NXP
if ARCH_NXP
config ARCH_LAYERSCAPE
bool "ARMv8 based Freescale Layerscape SoC family"
bool "Freescale Layerscape SoC family"
select EDAC_SUPPORT
help
This enables support for the Freescale Layerscape SoC family.
config ARCH_MXC
bool "ARMv8 based NXP i.MX SoC family"
bool "NXP i.MX SoC family"
select ARM64_ERRATUM_843419
select ARM64_ERRATUM_845719 if COMPAT
select IMX_GPCV2
@ -296,7 +296,7 @@ config ARCH_TEGRA
This enables support for the NVIDIA Tegra SoC family.
config ARCH_TESLA_FSD
bool "ARMv8 based Tesla platform"
bool "Tesla platform"
depends on ARCH_EXYNOS
help
Support for ARMv8 based Tesla platforms.

9
drivers/soc/atmel/soc.c
View File

@ -235,6 +235,15 @@ static const struct at91_soc socs[] __initconst = {
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,
"sama7g54", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D1G_EXID_MATCH,
"SAMA7G54 1Gb DDR3L SiP", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D2G_EXID_MATCH,
"SAMA7G54 2Gb DDR3L SiP", "sama7g5"),
AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_D4G_EXID_MATCH,
"SAMA7G54 4Gb DDR3L SiP", "sama7g5"),
#endif
{ /* sentinel */ },
};

3
drivers/soc/atmel/soc.h
View File

@ -70,6 +70,9 @@ at91_soc_init(const struct at91_soc *socs);
#define SAMA7G52_EXID_MATCH 0x2
#define SAMA7G53_EXID_MATCH 0x1
#define SAMA7G54_EXID_MATCH 0x0
#define SAMA7G54_D1G_EXID_MATCH 0x00000018
#define SAMA7G54_D2G_EXID_MATCH 0x00000020
#define SAMA7G54_D4G_EXID_MATCH 0x00000028
#define AT91SAM9XE128_CIDR_MATCH 0x329973a0
#define AT91SAM9XE256_CIDR_MATCH 0x329a93a0

4
drivers/soc/ti/smartreflex.c
View File

@ -198,7 +198,6 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
*/
static int sr_late_init(struct omap_sr *sr_info)
{
struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
int ret = 0;
if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
@ -209,9 +208,6 @@ static int sr_late_init(struct omap_sr *sr_info)
disable_irq(sr_info->irq);
}
if (pdata && pdata->enable_on_init)
sr_start_vddautocomp(sr_info);
return ret;
error:

1
include/linux/platform_data/voltage-omap.h
View File

@ -29,7 +29,6 @@ struct omap_volt_data {
struct voltagedomain;
struct voltagedomain *voltdm_lookup(const char *name);
int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
unsigned long volt);

3
include/linux/power/smartreflex.h
View File

@ -273,8 +273,6 @@ struct omap_sr_nvalue_table {
* @senn_avgweight SENNAVGWEIGHT value of the sr AVGWEIGHT register
* @senp_avgweight SENPAVGWEIGHT value of the sr AVGWEIGHT register
* @nvalue_count: Number of distinct nvalues in the nvalue table
* @enable_on_init: whether this sr module needs to enabled at
* boot up or not.
* @nvalue_table: table containing the efuse offsets and nvalues
* corresponding to them.
* @voltdm: Pointer to the voltage domain associated with the SR
@ -290,7 +288,6 @@ struct omap_sr_data {
u32 senn_avgweight;
u32 senp_avgweight;
int nvalue_count;
bool enable_on_init;
struct omap_sr_nvalue_table *nvalue_table;
struct voltagedomain *voltdm;
};

2
include/linux/usb/musb.h
View File

@ -143,8 +143,6 @@ extern int __init tusb6010_setup_interface(
unsigned async_cs, unsigned sync_cs,
unsigned irq, unsigned dmachan);
extern int tusb6010_platform_retime(unsigned is_refclk);
#endif /* OMAP2 */
#endif /* __LINUX_USB_MUSB_H */