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ARM udpates for 6.3-rc1
- Improve Kconfig help text for Cortex A8 and Cortex A9 errata - Kconfig spelling and grammar fixes - Allow kernel-mode VFP/Neon in softirq context - Use Neon in softirq context - Implement AES-CTR/GHASH version of GCM -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuNNh8scc2k/wOAE+9OeQG+StrGQFAmP0w4IACgkQ9OeQG+St rGRJJhAAnfBwqXA9FFToKt3dzLWUKcHM0wB0K1ABGJVovL1LZY1kDjVZ/nkJMlYn 2MCf7ImEv8k8QRRi1O3YjnAJ9JrIM2e5sEcPPzFAzcfxjdYQ7scfQZOE+4HU0i35 MxSoUp9nrF69rs4aL3sUNGoUoOmpvmMbeeYu/FTL0jWbr1ywfsn8JaXRwk9Xrfqw R/kWbDpIYmtG8qitv6aMOlSJeagxvo9PooIgd9u2OeCkl30jfuU/nqaHwuJEPzRh d+WYx4xC6twAORNc9odUqNOPIng2w2Tt99ChYAhvtcF5twW9baFiajK5kHL71Ykm 0y8RxdNP8aNuyP/XCABJkY87lnCNP0l4fIvWRPu+W5MWQMpdKE6+y5EK17rksk3Y zyV1v6ca9twK1HQs13xUgIRTQ5dYYwrEoSBhcBb5KhwYdP/xqx6FmES47gsGQWBg d6ammthp9zeMfJp/oiYvg4ZLsxSxH+kjNyqaTjJaSAsX4z8fH5onlxn+6r43tsTc nKEqCWBNhW0M3vFghuSHacxjGfWDhBarWmdGgXSQt0MNmvcY6YcHHO9blUHkShW/ FvsdqXFJYnTgv83zQPwrzPd7IG/8ytA0bxxH9prhbdEu3Xb0XtwxGpgDFmLH7d/B MDbda3vD319hpnxjOOSjzvcrJtJsSYBVZyVilcrRsvb6t5GQgdQ= =Wdob -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm Pull ARM udpates from Russell King: - Improve Kconfig help text for Cortex A8 and Cortex A9 errata - Kconfig spelling and grammar fixes - Allow kernel-mode VFP/Neon in softirq context - Use Neon in softirq context - Implement AES-CTR/GHASH version of GCM * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 9289/1: Allow pre-ARMv5 builds with ld.lld 16.0.0 and newer ARM: 9288/1: Kconfigs: fix spelling & grammar ARM: 9286/1: crypto: Implement fused AES-CTR/GHASH version of GCM ARM: 9285/1: remove meaningless arch/arm/mach-rda/Makefile ARM: 9283/1: permit non-nested kernel mode NEON in softirq context ARM: 9282/1: vfp: Manipulate task VFP state with softirqs disabled ARM: 9281/1: improve Cortex A8/A9 errata help text
This commit is contained in:
Linus Torvalds
commit
b327dfe052
@ -344,14 +344,16 @@ comment "CPU Core family selection"
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config ARCH_MULTI_V4
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bool "ARMv4 based platforms (FA526, StrongARM)"
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depends on !ARCH_MULTI_V6_V7
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depends on !LD_IS_LLD
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# https://github.com/llvm/llvm-project/issues/50764
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depends on !LD_IS_LLD || LLD_VERSION >= 160000
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select ARCH_MULTI_V4_V5
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select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
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config ARCH_MULTI_V4T
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bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
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depends on !ARCH_MULTI_V6_V7
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depends on !LD_IS_LLD
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# https://github.com/llvm/llvm-project/issues/50764
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depends on !LD_IS_LLD || LLD_VERSION >= 160000
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select ARCH_MULTI_V4_V5
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select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
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CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
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@ -656,7 +658,9 @@ config ARM_ERRATA_458693
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hazard might then cause a processor deadlock. The workaround enables
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the L1 caching of the NEON accesses and disables the PLD instruction
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in the ACTLR register. Note that setting specific bits in the ACTLR
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register may not be available in non-secure mode.
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register may not be available in non-secure mode and thus is not
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available on a multiplatform kernel. This should be applied by the
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bootloader instead.
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config ARM_ERRATA_460075
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bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
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@ -669,7 +673,9 @@ config ARM_ERRATA_460075
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and overwritten with stale memory contents from external memory. The
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workaround disables the write-allocate mode for the L2 cache via the
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ACTLR register. Note that setting specific bits in the ACTLR register
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may not be available in non-secure mode.
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may not be available in non-secure mode and thus is not available on
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a multiplatform kernel. This should be applied by the bootloader
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instead.
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config ARM_ERRATA_742230
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bool "ARM errata: DMB operation may be faulty"
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@ -682,7 +688,10 @@ config ARM_ERRATA_742230
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ordering of the two writes. This workaround sets a specific bit in
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the diagnostic register of the Cortex-A9 which causes the DMB
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instruction to behave as a DSB, ensuring the correct behaviour of
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the two writes.
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the two writes. Note that setting specific bits in the diagnostics
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register may not be available in non-secure mode and thus is not
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available on a multiplatform kernel. This should be applied by the
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bootloader instead.
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config ARM_ERRATA_742231
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bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
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@ -697,7 +706,10 @@ config ARM_ERRATA_742231
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replaced from one of the CPUs at the same time as another CPU is
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accessing it. This workaround sets specific bits in the diagnostic
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register of the Cortex-A9 which reduces the linefill issuing
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capabilities of the processor.
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capabilities of the processor. Note that setting specific bits in the
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diagnostics register may not be available in non-secure mode and thus
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is not available on a multiplatform kernel. This should be applied by
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the bootloader instead.
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config ARM_ERRATA_643719
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bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
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@ -734,7 +746,9 @@ config ARM_ERRATA_743622
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register of the Cortex-A9 which disables the Store Buffer
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optimisation, preventing the defect from occurring. This has no
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visible impact on the overall performance or power consumption of the
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processor.
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processor. Note that setting specific bits in the diagnostics register
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may not be available in non-secure mode and thus is not available on a
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multiplatform kernel. This should be applied by the bootloader instead.
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config ARM_ERRATA_751472
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bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
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@ -746,6 +760,10 @@ config ARM_ERRATA_751472
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completion of a following broadcasted operation if the second
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operation is received by a CPU before the ICIALLUIS has completed,
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potentially leading to corrupted entries in the cache or TLB.
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Note that setting specific bits in the diagnostics register may
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not be available in non-secure mode and thus is not available on
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a multiplatform kernel. This should be applied by the bootloader
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instead.
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config ARM_ERRATA_754322
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bool "ARM errata: possible faulty MMU translations following an ASID switch"
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@ -1206,8 +1206,8 @@ choice
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depends on MACH_STM32MP157
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select DEBUG_STM32_UART
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help
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Say Y here if you want kernel low-level debugging support
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on STM32MP1 based platforms, wich default UART is wired on
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Say Y here if you want kernel low-level debugging support on
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STM32MP1-based platforms, where the default UART is wired to
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UART4, but another UART instance can be selected by modifying
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CONFIG_DEBUG_UART_PHYS and CONFIG_DEBUG_UART_VIRT.
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@ -209,7 +209,6 @@ machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
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machine-$(CONFIG_ARCH_ORION5X) += orion5x
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machine-$(CONFIG_ARCH_PXA) += pxa
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machine-$(CONFIG_ARCH_QCOM) += qcom
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machine-$(CONFIG_ARCH_RDA) += rda
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machine-$(CONFIG_ARCH_REALTEK) += realtek
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machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
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machine-$(CONFIG_ARCH_RPC) += rpc
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@ -16,8 +16,10 @@ config CRYPTO_CURVE25519_NEON
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config CRYPTO_GHASH_ARM_CE
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tristate "Hash functions: GHASH (PMULL/NEON/ARMv8 Crypto Extensions)"
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depends on KERNEL_MODE_NEON
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select CRYPTO_AEAD
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select CRYPTO_HASH
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select CRYPTO_CRYPTD
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select CRYPTO_LIB_AES
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select CRYPTO_LIB_GF128MUL
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help
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GCM GHASH function (NIST SP800-38D)
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@ -2,7 +2,8 @@
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/*
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* Accelerated GHASH implementation with NEON/ARMv8 vmull.p8/64 instructions.
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*
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* Copyright (C) 2015 - 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
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* Copyright (C) 2015 - 2017 Linaro Ltd.
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* Copyright (C) 2023 Google LLC. <ardb@google.com>
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*/
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#include <linux/linkage.h>
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@ -44,7 +45,7 @@
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t2q .req q7
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t3q .req q8
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t4q .req q9
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T2 .req q9
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XH2 .req q9
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s1l .req d20
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s1h .req d21
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@ -80,7 +81,7 @@
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XL2 .req q5
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XM2 .req q6
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XH2 .req q7
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T2 .req q7
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T3 .req q8
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XL2_L .req d10
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@ -192,9 +193,10 @@
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vshr.u64 XL, XL, #1
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.endm
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.macro ghash_update, pn
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.macro ghash_update, pn, enc, aggregate=1, head=1
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vld1.64 {XL}, [r1]
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.if \head
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/* do the head block first, if supplied */
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ldr ip, [sp]
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teq ip, #0
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@ -202,13 +204,32 @@
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vld1.64 {T1}, [ip]
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teq r0, #0
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b 3f
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.endif
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0: .ifc \pn, p64
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.if \aggregate
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tst r0, #3 // skip until #blocks is a
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bne 2f // round multiple of 4
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vld1.8 {XL2-XM2}, [r2]!
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1: vld1.8 {T3-T2}, [r2]!
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1: vld1.8 {T2-T3}, [r2]!
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.ifnb \enc
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\enc\()_4x XL2, XM2, T2, T3
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add ip, r3, #16
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vld1.64 {HH}, [ip, :128]!
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vld1.64 {HH3-HH4}, [ip, :128]
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veor SHASH2_p64, SHASH_L, SHASH_H
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veor SHASH2_H, HH_L, HH_H
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veor HH34_L, HH3_L, HH3_H
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veor HH34_H, HH4_L, HH4_H
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vmov.i8 MASK, #0xe1
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vshl.u64 MASK, MASK, #57
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.endif
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vrev64.8 XL2, XL2
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vrev64.8 XM2, XM2
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@ -218,8 +239,8 @@
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veor XL2_H, XL2_H, XL_L
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veor XL, XL, T1
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vrev64.8 T3, T3
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vrev64.8 T1, T2
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vrev64.8 T1, T3
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vrev64.8 T3, T2
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vmull.p64 XH, HH4_H, XL_H // a1 * b1
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veor XL2_H, XL2_H, XL_H
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@ -267,14 +288,22 @@
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b 1b
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.endif
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.endif
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2: vld1.8 {T1}, [r2]!
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.ifnb \enc
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\enc\()_1x T1
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veor SHASH2_p64, SHASH_L, SHASH_H
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vmov.i8 MASK, #0xe1
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vshl.u64 MASK, MASK, #57
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.endif
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2: vld1.64 {T1}, [r2]!
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subs r0, r0, #1
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3: /* multiply XL by SHASH in GF(2^128) */
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#ifndef CONFIG_CPU_BIG_ENDIAN
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vrev64.8 T1, T1
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#endif
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vext.8 IN1, T1, T1, #8
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veor T1_L, T1_L, XL_H
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veor XL, XL, IN1
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@ -293,9 +322,6 @@
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veor XL, XL, T1
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bne 0b
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vst1.64 {XL}, [r1]
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bx lr
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.endm
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/*
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@ -316,6 +342,9 @@ ENTRY(pmull_ghash_update_p64)
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vshl.u64 MASK, MASK, #57
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ghash_update p64
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vst1.64 {XL}, [r1]
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bx lr
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ENDPROC(pmull_ghash_update_p64)
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ENTRY(pmull_ghash_update_p8)
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@ -336,4 +365,331 @@ ENTRY(pmull_ghash_update_p8)
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vmov.i64 k48, #0xffffffffffff
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ghash_update p8
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vst1.64 {XL}, [r1]
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bx lr
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ENDPROC(pmull_ghash_update_p8)
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e0 .req q9
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e1 .req q10
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e2 .req q11
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e3 .req q12
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e0l .req d18
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e0h .req d19
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e2l .req d22
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e2h .req d23
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e3l .req d24
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e3h .req d25
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ctr .req q13
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ctr0 .req d26
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ctr1 .req d27
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ek0 .req q14
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ek1 .req q15
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.macro round, rk:req, regs:vararg
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.irp r, \regs
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aese.8 \r, \rk
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aesmc.8 \r, \r
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.endr
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.endm
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.macro aes_encrypt, rkp, rounds, regs:vararg
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vld1.8 {ek0-ek1}, [\rkp, :128]!
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cmp \rounds, #12
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blt .L\@ // AES-128
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round ek0, \regs
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vld1.8 {ek0}, [\rkp, :128]!
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round ek1, \regs
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vld1.8 {ek1}, [\rkp, :128]!
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beq .L\@ // AES-192
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round ek0, \regs
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vld1.8 {ek0}, [\rkp, :128]!
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||||
round ek1, \regs
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vld1.8 {ek1}, [\rkp, :128]!
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||||
|
||||
.L\@: .rept 4
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||||
round ek0, \regs
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||||
vld1.8 {ek0}, [\rkp, :128]!
|
||||
round ek1, \regs
|
||||
vld1.8 {ek1}, [\rkp, :128]!
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||||
.endr
|
||||
|
||||
round ek0, \regs
|
||||
vld1.8 {ek0}, [\rkp, :128]
|
||||
|
||||
.irp r, \regs
|
||||
aese.8 \r, ek1
|
||||
.endr
|
||||
.irp r, \regs
|
||||
veor \r, \r, ek0
|
||||
.endr
|
||||
.endm
|
||||
|
||||
pmull_aes_encrypt:
|
||||
add ip, r5, #4
|
||||
vld1.8 {ctr0}, [r5] // load 12 byte IV
|
||||
vld1.8 {ctr1}, [ip]
|
||||
rev r8, r7
|
||||
vext.8 ctr1, ctr1, ctr1, #4
|
||||
add r7, r7, #1
|
||||
vmov.32 ctr1[1], r8
|
||||
vmov e0, ctr
|
||||
|
||||
add ip, r3, #64
|
||||
aes_encrypt ip, r6, e0
|
||||
bx lr
|
||||
ENDPROC(pmull_aes_encrypt)
|
||||
|
||||
pmull_aes_encrypt_4x:
|
||||
add ip, r5, #4
|
||||
vld1.8 {ctr0}, [r5]
|
||||
vld1.8 {ctr1}, [ip]
|
||||
rev r8, r7
|
||||
vext.8 ctr1, ctr1, ctr1, #4
|
||||
add r7, r7, #1
|
||||
vmov.32 ctr1[1], r8
|
||||
rev ip, r7
|
||||
vmov e0, ctr
|
||||
add r7, r7, #1
|
||||
vmov.32 ctr1[1], ip
|
||||
rev r8, r7
|
||||
vmov e1, ctr
|
||||
add r7, r7, #1
|
||||
vmov.32 ctr1[1], r8
|
||||
rev ip, r7
|
||||
vmov e2, ctr
|
||||
add r7, r7, #1
|
||||
vmov.32 ctr1[1], ip
|
||||
vmov e3, ctr
|
||||
|
||||
add ip, r3, #64
|
||||
aes_encrypt ip, r6, e0, e1, e2, e3
|
||||
bx lr
|
||||
ENDPROC(pmull_aes_encrypt_4x)
|
||||
|
||||
pmull_aes_encrypt_final:
|
||||
add ip, r5, #4
|
||||
vld1.8 {ctr0}, [r5]
|
||||
vld1.8 {ctr1}, [ip]
|
||||
rev r8, r7
|
||||
vext.8 ctr1, ctr1, ctr1, #4
|
||||
mov r7, #1 << 24 // BE #1 for the tag
|
||||
vmov.32 ctr1[1], r8
|
||||
vmov e0, ctr
|
||||
vmov.32 ctr1[1], r7
|
||||
vmov e1, ctr
|
||||
|
||||
add ip, r3, #64
|
||||
aes_encrypt ip, r6, e0, e1
|
||||
bx lr
|
||||
ENDPROC(pmull_aes_encrypt_final)
|
||||
|
||||
.macro enc_1x, in0
|
||||
bl pmull_aes_encrypt
|
||||
veor \in0, \in0, e0
|
||||
vst1.8 {\in0}, [r4]!
|
||||
.endm
|
||||
|
||||
.macro dec_1x, in0
|
||||
bl pmull_aes_encrypt
|
||||
veor e0, e0, \in0
|
||||
vst1.8 {e0}, [r4]!
|
||||
.endm
|
||||
|
||||
.macro enc_4x, in0, in1, in2, in3
|
||||
bl pmull_aes_encrypt_4x
|
||||
|
||||
veor \in0, \in0, e0
|
||||
veor \in1, \in1, e1
|
||||
veor \in2, \in2, e2
|
||||
veor \in3, \in3, e3
|
||||
|
||||
vst1.8 {\in0-\in1}, [r4]!
|
||||
vst1.8 {\in2-\in3}, [r4]!
|
||||
.endm
|
||||
|
||||
.macro dec_4x, in0, in1, in2, in3
|
||||
bl pmull_aes_encrypt_4x
|
||||
|
||||
veor e0, e0, \in0
|
||||
veor e1, e1, \in1
|
||||
veor e2, e2, \in2
|
||||
veor e3, e3, \in3
|
||||
|
||||
vst1.8 {e0-e1}, [r4]!
|
||||
vst1.8 {e2-e3}, [r4]!
|
||||
.endm
|
||||
|
||||
/*
|
||||
* void pmull_gcm_encrypt(int blocks, u64 dg[], const char *src,
|
||||
* struct gcm_key const *k, char *dst,
|
||||
* char *iv, int rounds, u32 counter)
|
||||
*/
|
||||
ENTRY(pmull_gcm_encrypt)
|
||||
push {r4-r8, lr}
|
||||
ldrd r4, r5, [sp, #24]
|
||||
ldrd r6, r7, [sp, #32]
|
||||
|
||||
vld1.64 {SHASH}, [r3]
|
||||
|
||||
ghash_update p64, enc, head=0
|
||||
vst1.64 {XL}, [r1]
|
||||
|
||||
pop {r4-r8, pc}
|
||||
ENDPROC(pmull_gcm_encrypt)
|
||||
|
||||
/*
|
||||
* void pmull_gcm_decrypt(int blocks, u64 dg[], const char *src,
|
||||
* struct gcm_key const *k, char *dst,
|
||||
* char *iv, int rounds, u32 counter)
|
||||
*/
|
||||
ENTRY(pmull_gcm_decrypt)
|
||||
push {r4-r8, lr}
|
||||
ldrd r4, r5, [sp, #24]
|
||||
ldrd r6, r7, [sp, #32]
|
||||
|
||||
vld1.64 {SHASH}, [r3]
|
||||
|
||||
ghash_update p64, dec, head=0
|
||||
vst1.64 {XL}, [r1]
|
||||
|
||||
pop {r4-r8, pc}
|
||||
ENDPROC(pmull_gcm_decrypt)
|
||||
|
||||
/*
|
||||
* void pmull_gcm_enc_final(int bytes, u64 dg[], char *tag,
|
||||
* struct gcm_key const *k, char *head,
|
||||
* char *iv, int rounds, u32 counter)
|
||||
*/
|
||||
ENTRY(pmull_gcm_enc_final)
|
||||
push {r4-r8, lr}
|
||||
ldrd r4, r5, [sp, #24]
|
||||
ldrd r6, r7, [sp, #32]
|
||||
|
||||
bl pmull_aes_encrypt_final
|
||||
|
||||
cmp r0, #0
|
||||
beq .Lenc_final
|
||||
|
||||
mov_l ip, .Lpermute
|
||||
sub r4, r4, #16
|
||||
add r8, ip, r0
|
||||
add ip, ip, #32
|
||||
add r4, r4, r0
|
||||
sub ip, ip, r0
|
||||
|
||||
vld1.8 {e3}, [r8] // permute vector for key stream
|
||||
vld1.8 {e2}, [ip] // permute vector for ghash input
|
||||
|
||||
vtbl.8 e3l, {e0}, e3l
|
||||
vtbl.8 e3h, {e0}, e3h
|
||||
|
||||
vld1.8 {e0}, [r4] // encrypt tail block
|
||||
veor e0, e0, e3
|
||||
vst1.8 {e0}, [r4]
|
||||
|
||||
vtbl.8 T1_L, {e0}, e2l
|
||||
vtbl.8 T1_H, {e0}, e2h
|
||||
|
||||
vld1.64 {XL}, [r1]
|
||||
.Lenc_final:
|
||||
vld1.64 {SHASH}, [r3, :128]
|
||||
vmov.i8 MASK, #0xe1
|
||||
veor SHASH2_p64, SHASH_L, SHASH_H
|
||||
vshl.u64 MASK, MASK, #57
|
||||
mov r0, #1
|
||||
bne 3f // process head block first
|
||||
ghash_update p64, aggregate=0, head=0
|
||||
|
||||
vrev64.8 XL, XL
|
||||
vext.8 XL, XL, XL, #8
|
||||
veor XL, XL, e1
|
||||
|
||||
sub r2, r2, #16 // rewind src pointer
|
||||
vst1.8 {XL}, [r2] // store tag
|
||||
|
||||
pop {r4-r8, pc}
|
||||
ENDPROC(pmull_gcm_enc_final)
|
||||
|
||||
/*
|
||||
* int pmull_gcm_dec_final(int bytes, u64 dg[], char *tag,
|
||||
* struct gcm_key const *k, char *head,
|
||||
* char *iv, int rounds, u32 counter,
|
||||
* const char *otag, int authsize)
|
||||
*/
|
||||
ENTRY(pmull_gcm_dec_final)
|
||||
push {r4-r8, lr}
|
||||
ldrd r4, r5, [sp, #24]
|
||||
ldrd r6, r7, [sp, #32]
|
||||
|
||||
bl pmull_aes_encrypt_final
|
||||
|
||||
cmp r0, #0
|
||||
beq .Ldec_final
|
||||
|
||||
mov_l ip, .Lpermute
|
||||
sub r4, r4, #16
|
||||
add r8, ip, r0
|
||||
add ip, ip, #32
|
||||
add r4, r4, r0
|
||||
sub ip, ip, r0
|
||||
|
||||
vld1.8 {e3}, [r8] // permute vector for key stream
|
||||
vld1.8 {e2}, [ip] // permute vector for ghash input
|
||||
|
||||
vtbl.8 e3l, {e0}, e3l
|
||||
vtbl.8 e3h, {e0}, e3h
|
||||
|
||||
vld1.8 {e0}, [r4]
|
||||
|
||||
vtbl.8 T1_L, {e0}, e2l
|
||||
vtbl.8 T1_H, {e0}, e2h
|
||||
|
||||
veor e0, e0, e3
|
||||
vst1.8 {e0}, [r4]
|
||||
|
||||
vld1.64 {XL}, [r1]
|
||||
.Ldec_final:
|
||||
vld1.64 {SHASH}, [r3]
|
||||
vmov.i8 MASK, #0xe1
|
||||
veor SHASH2_p64, SHASH_L, SHASH_H
|
||||
vshl.u64 MASK, MASK, #57
|
||||
mov r0, #1
|
||||
bne 3f // process head block first
|
||||
ghash_update p64, aggregate=0, head=0
|
||||
|
||||
vrev64.8 XL, XL
|
||||
vext.8 XL, XL, XL, #8
|
||||
veor XL, XL, e1
|
||||
|
||||
mov_l ip, .Lpermute
|
||||
ldrd r2, r3, [sp, #40] // otag and authsize
|
||||
vld1.8 {T1}, [r2]
|
||||
add ip, ip, r3
|
||||
vceq.i8 T1, T1, XL // compare tags
|
||||
vmvn T1, T1 // 0 for eq, -1 for ne
|
||||
|
||||
vld1.8 {e0}, [ip]
|
||||
vtbl.8 XL_L, {T1}, e0l // keep authsize bytes only
|
||||
vtbl.8 XL_H, {T1}, e0h
|
||||
|
||||
vpmin.s8 XL_L, XL_L, XL_H // take the minimum s8 across the vector
|
||||
vpmin.s8 XL_L, XL_L, XL_L
|
||||
vmov.32 r0, XL_L[0] // fail if != 0x0
|
||||
|
||||
pop {r4-r8, pc}
|
||||
ENDPROC(pmull_gcm_dec_final)
|
||||
|
||||
.section ".rodata", "a", %progbits
|
||||
.align 5
|
||||
.Lpermute:
|
||||
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
|
||||
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
|
||||
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07
|
||||
.byte 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f
|
||||
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
|
||||
.byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
|
||||
|
||||
@ -2,36 +2,53 @@
|
||||
/*
|
||||
* Accelerated GHASH implementation with ARMv8 vmull.p64 instructions.
|
||||
*
|
||||
* Copyright (C) 2015 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
|
||||
* Copyright (C) 2015 - 2018 Linaro Ltd.
|
||||
* Copyright (C) 2023 Google LLC.
|
||||
*/
|
||||
|
||||
#include <asm/hwcap.h>
|
||||
#include <asm/neon.h>
|
||||
#include <asm/simd.h>
|
||||
#include <asm/unaligned.h>
|
||||
#include <crypto/aes.h>
|
||||
#include <crypto/gcm.h>
|
||||
#include <crypto/b128ops.h>
|
||||
#include <crypto/cryptd.h>
|
||||
#include <crypto/internal/aead.h>
|
||||
#include <crypto/internal/hash.h>
|
||||
#include <crypto/internal/simd.h>
|
||||
#include <crypto/internal/skcipher.h>
|
||||
#include <crypto/gf128mul.h>
|
||||
#include <crypto/scatterwalk.h>
|
||||
#include <linux/cpufeature.h>
|
||||
#include <linux/crypto.h>
|
||||
#include <linux/jump_label.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
MODULE_DESCRIPTION("GHASH hash function using ARMv8 Crypto Extensions");
|
||||
MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Ard Biesheuvel <ardb@kernel.org>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS_CRYPTO("ghash");
|
||||
MODULE_ALIAS_CRYPTO("gcm(aes)");
|
||||
MODULE_ALIAS_CRYPTO("rfc4106(gcm(aes))");
|
||||
|
||||
#define GHASH_BLOCK_SIZE 16
|
||||
#define GHASH_DIGEST_SIZE 16
|
||||
|
||||
#define RFC4106_NONCE_SIZE 4
|
||||
|
||||
struct ghash_key {
|
||||
be128 k;
|
||||
u64 h[][2];
|
||||
};
|
||||
|
||||
struct gcm_key {
|
||||
u64 h[4][2];
|
||||
u32 rk[AES_MAX_KEYLENGTH_U32];
|
||||
int rounds;
|
||||
u8 nonce[]; // for RFC4106 nonce
|
||||
};
|
||||
|
||||
struct ghash_desc_ctx {
|
||||
u64 digest[GHASH_DIGEST_SIZE/sizeof(u64)];
|
||||
u8 buf[GHASH_BLOCK_SIZE];
|
||||
@ -344,6 +361,393 @@ static struct ahash_alg ghash_async_alg = {
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
void pmull_gcm_encrypt(int blocks, u64 dg[], const char *src,
|
||||
struct gcm_key const *k, char *dst,
|
||||
const char *iv, int rounds, u32 counter);
|
||||
|
||||
void pmull_gcm_enc_final(int blocks, u64 dg[], char *tag,
|
||||
struct gcm_key const *k, char *head,
|
||||
const char *iv, int rounds, u32 counter);
|
||||
|
||||
void pmull_gcm_decrypt(int bytes, u64 dg[], const char *src,
|
||||
struct gcm_key const *k, char *dst,
|
||||
const char *iv, int rounds, u32 counter);
|
||||
|
||||
int pmull_gcm_dec_final(int bytes, u64 dg[], char *tag,
|
||||
struct gcm_key const *k, char *head,
|
||||
const char *iv, int rounds, u32 counter,
|
||||
const char *otag, int authsize);
|
||||
|
||||
static int gcm_aes_setkey(struct crypto_aead *tfm, const u8 *inkey,
|
||||
unsigned int keylen)
|
||||
{
|
||||
struct gcm_key *ctx = crypto_aead_ctx(tfm);
|
||||
struct crypto_aes_ctx aes_ctx;
|
||||
be128 h, k;
|
||||
int ret;
|
||||
|
||||
ret = aes_expandkey(&aes_ctx, inkey, keylen);
|
||||
if (ret)
|
||||
return -EINVAL;
|
||||
|
||||
aes_encrypt(&aes_ctx, (u8 *)&k, (u8[AES_BLOCK_SIZE]){});
|
||||
|
||||
memcpy(ctx->rk, aes_ctx.key_enc, sizeof(ctx->rk));
|
||||
ctx->rounds = 6 + keylen / 4;
|
||||
|
||||
memzero_explicit(&aes_ctx, sizeof(aes_ctx));
|
||||
|
||||
ghash_reflect(ctx->h[0], &k);
|
||||
|
||||
h = k;
|
||||
gf128mul_lle(&h, &k);
|
||||
ghash_reflect(ctx->h[1], &h);
|
||||
|
||||
gf128mul_lle(&h, &k);
|
||||
ghash_reflect(ctx->h[2], &h);
|
||||
|
||||
gf128mul_lle(&h, &k);
|
||||
ghash_reflect(ctx->h[3], &h);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gcm_aes_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
|
||||
{
|
||||
return crypto_gcm_check_authsize(authsize);
|
||||
}
|
||||
|
||||
static void gcm_update_mac(u64 dg[], const u8 *src, int count, u8 buf[],
|
||||
int *buf_count, struct gcm_key *ctx)
|
||||
{
|
||||
if (*buf_count > 0) {
|
||||
int buf_added = min(count, GHASH_BLOCK_SIZE - *buf_count);
|
||||
|
||||
memcpy(&buf[*buf_count], src, buf_added);
|
||||
|
||||
*buf_count += buf_added;
|
||||
src += buf_added;
|
||||
count -= buf_added;
|
||||
}
|
||||
|
||||
if (count >= GHASH_BLOCK_SIZE || *buf_count == GHASH_BLOCK_SIZE) {
|
||||
int blocks = count / GHASH_BLOCK_SIZE;
|
||||
|
||||
pmull_ghash_update_p64(blocks, dg, src, ctx->h,
|
||||
*buf_count ? buf : NULL);
|
||||
|
||||
src += blocks * GHASH_BLOCK_SIZE;
|
||||
count %= GHASH_BLOCK_SIZE;
|
||||
*buf_count = 0;
|
||||
}
|
||||
|
||||
if (count > 0) {
|
||||
memcpy(buf, src, count);
|
||||
*buf_count = count;
|
||||
}
|
||||
}
|
||||
|
||||
static void gcm_calculate_auth_mac(struct aead_request *req, u64 dg[], u32 len)
|
||||
{
|
||||
struct crypto_aead *aead = crypto_aead_reqtfm(req);
|
||||
struct gcm_key *ctx = crypto_aead_ctx(aead);
|
||||
u8 buf[GHASH_BLOCK_SIZE];
|
||||
struct scatter_walk walk;
|
||||
int buf_count = 0;
|
||||
|
||||
scatterwalk_start(&walk, req->src);
|
||||
|
||||
do {
|
||||
u32 n = scatterwalk_clamp(&walk, len);
|
||||
u8 *p;
|
||||
|
||||
if (!n) {
|
||||
scatterwalk_start(&walk, sg_next(walk.sg));
|
||||
n = scatterwalk_clamp(&walk, len);
|
||||
}
|
||||
|
||||
p = scatterwalk_map(&walk);
|
||||
gcm_update_mac(dg, p, n, buf, &buf_count, ctx);
|
||||
scatterwalk_unmap(p);
|
||||
|
||||
if (unlikely(len / SZ_4K > (len - n) / SZ_4K)) {
|
||||
kernel_neon_end();
|
||||
kernel_neon_begin();
|
||||
}
|
||||
|
||||
len -= n;
|
||||
scatterwalk_advance(&walk, n);
|
||||
scatterwalk_done(&walk, 0, len);
|
||||
} while (len);
|
||||
|
||||
if (buf_count) {
|
||||
memset(&buf[buf_count], 0, GHASH_BLOCK_SIZE - buf_count);
|
||||
pmull_ghash_update_p64(1, dg, buf, ctx->h, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
static int gcm_encrypt(struct aead_request *req, const u8 *iv, u32 assoclen)
|
||||
{
|
||||
struct crypto_aead *aead = crypto_aead_reqtfm(req);
|
||||
struct gcm_key *ctx = crypto_aead_ctx(aead);
|
||||
struct skcipher_walk walk;
|
||||
u8 buf[AES_BLOCK_SIZE];
|
||||
u32 counter = 2;
|
||||
u64 dg[2] = {};
|
||||
be128 lengths;
|
||||
const u8 *src;
|
||||
u8 *tag, *dst;
|
||||
int tail, err;
|
||||
|
||||
if (WARN_ON_ONCE(!may_use_simd()))
|
||||
return -EBUSY;
|
||||
|
||||
err = skcipher_walk_aead_encrypt(&walk, req, false);
|
||||
|
||||
kernel_neon_begin();
|
||||
|
||||
if (assoclen)
|
||||
gcm_calculate_auth_mac(req, dg, assoclen);
|
||||
|
||||
src = walk.src.virt.addr;
|
||||
dst = walk.dst.virt.addr;
|
||||
|
||||
while (walk.nbytes >= AES_BLOCK_SIZE) {
|
||||
int nblocks = walk.nbytes / AES_BLOCK_SIZE;
|
||||
|
||||
pmull_gcm_encrypt(nblocks, dg, src, ctx, dst, iv,
|
||||
ctx->rounds, counter);
|
||||
counter += nblocks;
|
||||
|
||||
if (walk.nbytes == walk.total) {
|
||||
src += nblocks * AES_BLOCK_SIZE;
|
||||
dst += nblocks * AES_BLOCK_SIZE;
|
||||
break;
|
||||
}
|
||||
|
||||
kernel_neon_end();
|
||||
|
||||
err = skcipher_walk_done(&walk,
|
||||
walk.nbytes % AES_BLOCK_SIZE);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
src = walk.src.virt.addr;
|
||||
dst = walk.dst.virt.addr;
|
||||
|
||||
kernel_neon_begin();
|
||||
}
|
||||
|
||||
|
||||
lengths.a = cpu_to_be64(assoclen * 8);
|
||||
lengths.b = cpu_to_be64(req->cryptlen * 8);
|
||||
|
||||
tag = (u8 *)&lengths;
|
||||
tail = walk.nbytes % AES_BLOCK_SIZE;
|
||||
|
||||
/*
|
||||
* Bounce via a buffer unless we are encrypting in place and src/dst
|
||||
* are not pointing to the start of the walk buffer. In that case, we
|
||||
* can do a NEON load/xor/store sequence in place as long as we move
|
||||
* the plain/ciphertext and keystream to the start of the register. If
|
||||
* not, do a memcpy() to the end of the buffer so we can reuse the same
|
||||
* logic.
|
||||
*/
|
||||
if (unlikely(tail && (tail == walk.nbytes || src != dst)))
|
||||
src = memcpy(buf + sizeof(buf) - tail, src, tail);
|
||||
|
||||
pmull_gcm_enc_final(tail, dg, tag, ctx, (u8 *)src, iv,
|
||||
ctx->rounds, counter);
|
||||
kernel_neon_end();
|
||||
|
||||
if (unlikely(tail && src != dst))
|
||||
memcpy(dst, src, tail);
|
||||
|
||||
if (walk.nbytes) {
|
||||
err = skcipher_walk_done(&walk, 0);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
/* copy authtag to end of dst */
|
||||
scatterwalk_map_and_copy(tag, req->dst, req->assoclen + req->cryptlen,
|
||||
crypto_aead_authsize(aead), 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gcm_decrypt(struct aead_request *req, const u8 *iv, u32 assoclen)
|
||||
{
|
||||
struct crypto_aead *aead = crypto_aead_reqtfm(req);
|
||||
struct gcm_key *ctx = crypto_aead_ctx(aead);
|
||||
int authsize = crypto_aead_authsize(aead);
|
||||
struct skcipher_walk walk;
|
||||
u8 otag[AES_BLOCK_SIZE];
|
||||
u8 buf[AES_BLOCK_SIZE];
|
||||
u32 counter = 2;
|
||||
u64 dg[2] = {};
|
||||
be128 lengths;
|
||||
const u8 *src;
|
||||
u8 *tag, *dst;
|
||||
int tail, err, ret;
|
||||
|
||||
if (WARN_ON_ONCE(!may_use_simd()))
|
||||
return -EBUSY;
|
||||
|
||||
scatterwalk_map_and_copy(otag, req->src,
|
||||
req->assoclen + req->cryptlen - authsize,
|
||||
authsize, 0);
|
||||
|
||||
err = skcipher_walk_aead_decrypt(&walk, req, false);
|
||||
|
||||
kernel_neon_begin();
|
||||
|
||||
if (assoclen)
|
||||
gcm_calculate_auth_mac(req, dg, assoclen);
|
||||
|
||||
src = walk.src.virt.addr;
|
||||
dst = walk.dst.virt.addr;
|
||||
|
||||
while (walk.nbytes >= AES_BLOCK_SIZE) {
|
||||
int nblocks = walk.nbytes / AES_BLOCK_SIZE;
|
||||
|
||||
pmull_gcm_decrypt(nblocks, dg, src, ctx, dst, iv,
|
||||
ctx->rounds, counter);
|
||||
counter += nblocks;
|
||||
|
||||
if (walk.nbytes == walk.total) {
|
||||
src += nblocks * AES_BLOCK_SIZE;
|
||||
dst += nblocks * AES_BLOCK_SIZE;
|
||||
break;
|
||||
}
|
||||
|
||||
kernel_neon_end();
|
||||
|
||||
err = skcipher_walk_done(&walk,
|
||||
walk.nbytes % AES_BLOCK_SIZE);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
src = walk.src.virt.addr;
|
||||
dst = walk.dst.virt.addr;
|
||||
|
||||
kernel_neon_begin();
|
||||
}
|
||||
|
||||
lengths.a = cpu_to_be64(assoclen * 8);
|
||||
lengths.b = cpu_to_be64((req->cryptlen - authsize) * 8);
|
||||
|
||||
tag = (u8 *)&lengths;
|
||||
tail = walk.nbytes % AES_BLOCK_SIZE;
|
||||
|
||||
if (unlikely(tail && (tail == walk.nbytes || src != dst)))
|
||||
src = memcpy(buf + sizeof(buf) - tail, src, tail);
|
||||
|
||||
ret = pmull_gcm_dec_final(tail, dg, tag, ctx, (u8 *)src, iv,
|
||||
ctx->rounds, counter, otag, authsize);
|
||||
kernel_neon_end();
|
||||
|
||||
if (unlikely(tail && src != dst))
|
||||
memcpy(dst, src, tail);
|
||||
|
||||
if (walk.nbytes) {
|
||||
err = skcipher_walk_done(&walk, 0);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return ret ? -EBADMSG : 0;
|
||||
}
|
||||
|
||||
static int gcm_aes_encrypt(struct aead_request *req)
|
||||
{
|
||||
return gcm_encrypt(req, req->iv, req->assoclen);
|
||||
}
|
||||
|
||||
static int gcm_aes_decrypt(struct aead_request *req)
|
||||
{
|
||||
return gcm_decrypt(req, req->iv, req->assoclen);
|
||||
}
|
||||
|
||||
static int rfc4106_setkey(struct crypto_aead *tfm, const u8 *inkey,
|
||||
unsigned int keylen)
|
||||
{
|
||||
struct gcm_key *ctx = crypto_aead_ctx(tfm);
|
||||
int err;
|
||||
|
||||
keylen -= RFC4106_NONCE_SIZE;
|
||||
err = gcm_aes_setkey(tfm, inkey, keylen);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
memcpy(ctx->nonce, inkey + keylen, RFC4106_NONCE_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rfc4106_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
|
||||
{
|
||||
return crypto_rfc4106_check_authsize(authsize);
|
||||
}
|
||||
|
||||
static int rfc4106_encrypt(struct aead_request *req)
|
||||
{
|
||||
struct crypto_aead *aead = crypto_aead_reqtfm(req);
|
||||
struct gcm_key *ctx = crypto_aead_ctx(aead);
|
||||
u8 iv[GCM_AES_IV_SIZE];
|
||||
|
||||
memcpy(iv, ctx->nonce, RFC4106_NONCE_SIZE);
|
||||
memcpy(iv + RFC4106_NONCE_SIZE, req->iv, GCM_RFC4106_IV_SIZE);
|
||||
|
||||
return crypto_ipsec_check_assoclen(req->assoclen) ?:
|
||||
gcm_encrypt(req, iv, req->assoclen - GCM_RFC4106_IV_SIZE);
|
||||
}
|
||||
|
||||
static int rfc4106_decrypt(struct aead_request *req)
|
||||
{
|
||||
struct crypto_aead *aead = crypto_aead_reqtfm(req);
|
||||
struct gcm_key *ctx = crypto_aead_ctx(aead);
|
||||
u8 iv[GCM_AES_IV_SIZE];
|
||||
|
||||
memcpy(iv, ctx->nonce, RFC4106_NONCE_SIZE);
|
||||
memcpy(iv + RFC4106_NONCE_SIZE, req->iv, GCM_RFC4106_IV_SIZE);
|
||||
|
||||
return crypto_ipsec_check_assoclen(req->assoclen) ?:
|
||||
gcm_decrypt(req, iv, req->assoclen - GCM_RFC4106_IV_SIZE);
|
||||
}
|
||||
|
||||
static struct aead_alg gcm_aes_algs[] = {{
|
||||
.ivsize = GCM_AES_IV_SIZE,
|
||||
.chunksize = AES_BLOCK_SIZE,
|
||||
.maxauthsize = AES_BLOCK_SIZE,
|
||||
.setkey = gcm_aes_setkey,
|
||||
.setauthsize = gcm_aes_setauthsize,
|
||||
.encrypt = gcm_aes_encrypt,
|
||||
.decrypt = gcm_aes_decrypt,
|
||||
|
||||
.base.cra_name = "gcm(aes)",
|
||||
.base.cra_driver_name = "gcm-aes-ce",
|
||||
.base.cra_priority = 400,
|
||||
.base.cra_blocksize = 1,
|
||||
.base.cra_ctxsize = sizeof(struct gcm_key),
|
||||
.base.cra_module = THIS_MODULE,
|
||||
}, {
|
||||
.ivsize = GCM_RFC4106_IV_SIZE,
|
||||
.chunksize = AES_BLOCK_SIZE,
|
||||
.maxauthsize = AES_BLOCK_SIZE,
|
||||
.setkey = rfc4106_setkey,
|
||||
.setauthsize = rfc4106_setauthsize,
|
||||
.encrypt = rfc4106_encrypt,
|
||||
.decrypt = rfc4106_decrypt,
|
||||
|
||||
.base.cra_name = "rfc4106(gcm(aes))",
|
||||
.base.cra_driver_name = "rfc4106-gcm-aes-ce",
|
||||
.base.cra_priority = 400,
|
||||
.base.cra_blocksize = 1,
|
||||
.base.cra_ctxsize = sizeof(struct gcm_key) + RFC4106_NONCE_SIZE,
|
||||
.base.cra_module = THIS_MODULE,
|
||||
}};
|
||||
|
||||
static int __init ghash_ce_mod_init(void)
|
||||
{
|
||||
int err;
|
||||
@ -352,13 +756,17 @@ static int __init ghash_ce_mod_init(void)
|
||||
return -ENODEV;
|
||||
|
||||
if (elf_hwcap2 & HWCAP2_PMULL) {
|
||||
err = crypto_register_aeads(gcm_aes_algs,
|
||||
ARRAY_SIZE(gcm_aes_algs));
|
||||
if (err)
|
||||
return err;
|
||||
ghash_alg.base.cra_ctxsize += 3 * sizeof(u64[2]);
|
||||
static_branch_enable(&use_p64);
|
||||
}
|
||||
|
||||
err = crypto_register_shash(&ghash_alg);
|
||||
if (err)
|
||||
return err;
|
||||
goto err_aead;
|
||||
err = crypto_register_ahash(&ghash_async_alg);
|
||||
if (err)
|
||||
goto err_shash;
|
||||
@ -367,6 +775,10 @@ static int __init ghash_ce_mod_init(void)
|
||||
|
||||
err_shash:
|
||||
crypto_unregister_shash(&ghash_alg);
|
||||
err_aead:
|
||||
if (elf_hwcap2 & HWCAP2_PMULL)
|
||||
crypto_unregister_aeads(gcm_aes_algs,
|
||||
ARRAY_SIZE(gcm_aes_algs));
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -374,6 +786,9 @@ static void __exit ghash_ce_mod_exit(void)
|
||||
{
|
||||
crypto_unregister_ahash(&ghash_async_alg);
|
||||
crypto_unregister_shash(&ghash_alg);
|
||||
if (elf_hwcap2 & HWCAP2_PMULL)
|
||||
crypto_unregister_aeads(gcm_aes_algs,
|
||||
ARRAY_SIZE(gcm_aes_algs));
|
||||
}
|
||||
|
||||
module_init(ghash_ce_mod_init);
|
||||
|
||||
@ -236,22 +236,27 @@ THUMB( fpreg .req r7 )
|
||||
sub \tmp, \tmp, #1 @ decrement it
|
||||
str \tmp, [\ti, #TI_PREEMPT]
|
||||
.endm
|
||||
|
||||
.macro dec_preempt_count_ti, ti, tmp
|
||||
get_thread_info \ti
|
||||
dec_preempt_count \ti, \tmp
|
||||
.endm
|
||||
#else
|
||||
.macro inc_preempt_count, ti, tmp
|
||||
.endm
|
||||
|
||||
.macro dec_preempt_count, ti, tmp
|
||||
.endm
|
||||
|
||||
.macro dec_preempt_count_ti, ti, tmp
|
||||
.endm
|
||||
#endif
|
||||
|
||||
.macro local_bh_disable, ti, tmp
|
||||
ldr \tmp, [\ti, #TI_PREEMPT]
|
||||
add \tmp, \tmp, #SOFTIRQ_DISABLE_OFFSET
|
||||
str \tmp, [\ti, #TI_PREEMPT]
|
||||
.endm
|
||||
|
||||
.macro local_bh_enable_ti, ti, tmp
|
||||
get_thread_info \ti
|
||||
ldr \tmp, [\ti, #TI_PREEMPT]
|
||||
sub \tmp, \tmp, #SOFTIRQ_DISABLE_OFFSET
|
||||
str \tmp, [\ti, #TI_PREEMPT]
|
||||
.endm
|
||||
|
||||
#define USERL(l, x...) \
|
||||
9999: x; \
|
||||
.pushsection __ex_table,"a"; \
|
||||
|
||||
8
arch/arm/include/asm/simd.h
Normal file
8
arch/arm/include/asm/simd.h
Normal file
@ -0,0 +1,8 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#include <linux/hardirq.h>
|
||||
|
||||
static __must_check inline bool may_use_simd(void)
|
||||
{
|
||||
return IS_ENABLED(CONFIG_KERNEL_MODE_NEON) && !in_hardirq();
|
||||
}
|
||||
@ -56,6 +56,7 @@ int main(void)
|
||||
DEFINE(VFP_CPU, offsetof(union vfp_state, hard.cpu));
|
||||
#endif
|
||||
#endif
|
||||
DEFINE(SOFTIRQ_DISABLE_OFFSET,SOFTIRQ_DISABLE_OFFSET);
|
||||
#ifdef CONFIG_ARM_THUMBEE
|
||||
DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state));
|
||||
#endif
|
||||
|
||||
@ -1,2 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj- += dummy.o
|
||||
@ -743,7 +743,7 @@ config SWP_EMULATE
|
||||
If unsure, say Y.
|
||||
|
||||
choice
|
||||
prompt "CPU Endianess"
|
||||
prompt "CPU Endianness"
|
||||
default CPU_LITTLE_ENDIAN
|
||||
|
||||
config CPU_LITTLE_ENDIAN
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
@ IRQs enabled.
|
||||
@
|
||||
ENTRY(do_vfp)
|
||||
inc_preempt_count r10, r4
|
||||
local_bh_disable r10, r4
|
||||
ldr r4, .LCvfp
|
||||
ldr r11, [r10, #TI_CPU] @ CPU number
|
||||
add r10, r10, #TI_VFPSTATE @ r10 = workspace
|
||||
@ -30,7 +30,7 @@ ENTRY(do_vfp)
|
||||
ENDPROC(do_vfp)
|
||||
|
||||
ENTRY(vfp_null_entry)
|
||||
dec_preempt_count_ti r10, r4
|
||||
local_bh_enable_ti r10, r4
|
||||
ret lr
|
||||
ENDPROC(vfp_null_entry)
|
||||
|
||||
|
||||
@ -175,7 +175,7 @@ vfp_hw_state_valid:
|
||||
@ else it's one 32-bit instruction, so
|
||||
@ always subtract 4 from the following
|
||||
@ instruction address.
|
||||
dec_preempt_count_ti r10, r4
|
||||
local_bh_enable_ti r10, r4
|
||||
ret r9 @ we think we have handled things
|
||||
|
||||
|
||||
@ -200,7 +200,7 @@ skip:
|
||||
@ not recognised by VFP
|
||||
|
||||
DBGSTR "not VFP"
|
||||
dec_preempt_count_ti r10, r4
|
||||
local_bh_enable_ti r10, r4
|
||||
ret lr
|
||||
|
||||
process_exception:
|
||||
|
||||
@ -416,7 +416,7 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
|
||||
if (exceptions)
|
||||
vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
|
||||
exit:
|
||||
preempt_enable();
|
||||
local_bh_enable();
|
||||
}
|
||||
|
||||
static void vfp_enable(void *unused)
|
||||
@ -517,6 +517,8 @@ void vfp_sync_hwstate(struct thread_info *thread)
|
||||
{
|
||||
unsigned int cpu = get_cpu();
|
||||
|
||||
local_bh_disable();
|
||||
|
||||
if (vfp_state_in_hw(cpu, thread)) {
|
||||
u32 fpexc = fmrx(FPEXC);
|
||||
|
||||
@ -528,6 +530,7 @@ void vfp_sync_hwstate(struct thread_info *thread)
|
||||
fmxr(FPEXC, fpexc);
|
||||
}
|
||||
|
||||
local_bh_enable();
|
||||
put_cpu();
|
||||
}
|
||||
|
||||
@ -717,13 +720,15 @@ void kernel_neon_begin(void)
|
||||
unsigned int cpu;
|
||||
u32 fpexc;
|
||||
|
||||
local_bh_disable();
|
||||
|
||||
/*
|
||||
* Kernel mode NEON is only allowed outside of interrupt context
|
||||
* with preemption disabled. This will make sure that the kernel
|
||||
* mode NEON register contents never need to be preserved.
|
||||
* Kernel mode NEON is only allowed outside of hardirq context with
|
||||
* preemption and softirq processing disabled. This will make sure that
|
||||
* the kernel mode NEON register contents never need to be preserved.
|
||||
*/
|
||||
BUG_ON(in_interrupt());
|
||||
cpu = get_cpu();
|
||||
BUG_ON(in_hardirq());
|
||||
cpu = __smp_processor_id();
|
||||
|
||||
fpexc = fmrx(FPEXC) | FPEXC_EN;
|
||||
fmxr(FPEXC, fpexc);
|
||||
@ -746,7 +751,7 @@ void kernel_neon_end(void)
|
||||
{
|
||||
/* Disable the NEON/VFP unit. */
|
||||
fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
|
||||
put_cpu();
|
||||
local_bh_enable();
|
||||
}
|
||||
EXPORT_SYMBOL(kernel_neon_end);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user