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powerpc/mem: Move cache flushing functions into mm/cacheflush.c
Cache flushing functions are in the middle of completely unrelated stuff in mm/mem.c Create a dedicated mm/cacheflush.c for those functions. Also cleanup the list of included headers. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/7bf6f1600acad146e541a4e220940062f2e5b03d.1617895813.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
ff0b4155ae
commit
b26e8f2725
@ -8,7 +8,8 @@ ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
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obj-y := fault.o mem.o pgtable.o mmap.o maccess.o \
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init_$(BITS).o pgtable_$(BITS).o \
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pgtable-frag.o ioremap.o ioremap_$(BITS).o \
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init-common.o mmu_context.o drmem.o
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init-common.o mmu_context.o drmem.o \
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cacheflush.o
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obj-$(CONFIG_PPC_MMU_NOHASH) += nohash/
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obj-$(CONFIG_PPC_BOOK3S_32) += book3s32/
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obj-$(CONFIG_PPC_BOOK3S_64) += book3s64/
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255
arch/powerpc/mm/cacheflush.c
Normal file
255
arch/powerpc/mm/cacheflush.c
Normal file
@ -0,0 +1,255 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <linux/highmem.h>
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#include <linux/kprobes.h>
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/**
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* flush_coherent_icache() - if a CPU has a coherent icache, flush it
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* @addr: The base address to use (can be any valid address, the whole cache will be flushed)
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* Return true if the cache was flushed, false otherwise
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*/
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static inline bool flush_coherent_icache(unsigned long addr)
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{
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/*
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* For a snooping icache, we still need a dummy icbi to purge all the
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* prefetched instructions from the ifetch buffers. We also need a sync
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* before the icbi to order the the actual stores to memory that might
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* have modified instructions with the icbi.
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*/
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if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
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mb(); /* sync */
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allow_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
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icbi((void *)addr);
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prevent_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
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mb(); /* sync */
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isync();
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return true;
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}
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return false;
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}
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/**
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* invalidate_icache_range() - Flush the icache by issuing icbi across an address range
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* @start: the start address
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* @stop: the stop address (exclusive)
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*/
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static void invalidate_icache_range(unsigned long start, unsigned long stop)
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{
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unsigned long shift = l1_icache_shift();
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unsigned long bytes = l1_icache_bytes();
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char *addr = (char *)(start & ~(bytes - 1));
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unsigned long size = stop - (unsigned long)addr + (bytes - 1);
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unsigned long i;
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for (i = 0; i < size >> shift; i++, addr += bytes)
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icbi(addr);
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mb(); /* sync */
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isync();
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}
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/**
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* flush_icache_range: Write any modified data cache blocks out to memory
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* and invalidate the corresponding blocks in the instruction cache
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*
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* Generic code will call this after writing memory, before executing from it.
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*
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* @start: the start address
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* @stop: the stop address (exclusive)
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*/
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void flush_icache_range(unsigned long start, unsigned long stop)
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{
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if (flush_coherent_icache(start))
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return;
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clean_dcache_range(start, stop);
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if (IS_ENABLED(CONFIG_44x)) {
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/*
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* Flash invalidate on 44x because we are passed kmapped
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* addresses and this doesn't work for userspace pages due to
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* the virtually tagged icache.
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*/
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iccci((void *)start);
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mb(); /* sync */
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isync();
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} else
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invalidate_icache_range(start, stop);
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}
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EXPORT_SYMBOL(flush_icache_range);
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#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
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/**
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* flush_dcache_icache_phys() - Flush a page by it's physical address
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* @physaddr: the physical address of the page
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*/
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static void flush_dcache_icache_phys(unsigned long physaddr)
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{
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unsigned long bytes = l1_dcache_bytes();
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unsigned long nb = PAGE_SIZE / bytes;
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unsigned long addr = physaddr & PAGE_MASK;
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unsigned long msr, msr0;
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unsigned long loop1 = addr, loop2 = addr;
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msr0 = mfmsr();
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msr = msr0 & ~MSR_DR;
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/*
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* This must remain as ASM to prevent potential memory accesses
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* while the data MMU is disabled
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*/
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asm volatile(
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" mtctr %2;\n"
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" mtmsr %3;\n"
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" isync;\n"
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"0: dcbst 0, %0;\n"
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" addi %0, %0, %4;\n"
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" bdnz 0b;\n"
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" sync;\n"
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" mtctr %2;\n"
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"1: icbi 0, %1;\n"
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" addi %1, %1, %4;\n"
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" bdnz 1b;\n"
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" sync;\n"
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" mtmsr %5;\n"
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" isync;\n"
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: "+&r" (loop1), "+&r" (loop2)
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: "r" (nb), "r" (msr), "i" (bytes), "r" (msr0)
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: "ctr", "memory");
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}
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NOKPROBE_SYMBOL(flush_dcache_icache_phys)
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#endif // !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
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/*
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* This is called when a page has been modified by the kernel.
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* It just marks the page as not i-cache clean. We do the i-cache
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* flush later when the page is given to a user process, if necessary.
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*/
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void flush_dcache_page(struct page *page)
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{
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if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
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return;
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/* avoid an atomic op if possible */
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if (test_bit(PG_dcache_clean, &page->flags))
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clear_bit(PG_dcache_clean, &page->flags);
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}
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EXPORT_SYMBOL(flush_dcache_page);
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static void flush_dcache_icache_hugepage(struct page *page)
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{
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int i;
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void *start;
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BUG_ON(!PageCompound(page));
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for (i = 0; i < compound_nr(page); i++) {
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if (!PageHighMem(page)) {
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__flush_dcache_icache(page_address(page+i));
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} else {
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start = kmap_atomic(page+i);
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__flush_dcache_icache(start);
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kunmap_atomic(start);
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}
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}
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}
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void flush_dcache_icache_page(struct page *page)
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{
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if (PageCompound(page))
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return flush_dcache_icache_hugepage(page);
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#if defined(CONFIG_PPC_8xx) || defined(CONFIG_PPC64)
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/* On 8xx there is no need to kmap since highmem is not supported */
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__flush_dcache_icache(page_address(page));
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#else
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if (IS_ENABLED(CONFIG_BOOKE) || sizeof(phys_addr_t) > sizeof(void *)) {
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void *start = kmap_atomic(page);
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__flush_dcache_icache(start);
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kunmap_atomic(start);
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} else {
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unsigned long addr = page_to_pfn(page) << PAGE_SHIFT;
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if (flush_coherent_icache(addr))
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return;
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flush_dcache_icache_phys(addr);
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}
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#endif
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}
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EXPORT_SYMBOL(flush_dcache_icache_page);
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/**
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* __flush_dcache_icache(): Flush a particular page from the data cache to RAM.
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* Note: this is necessary because the instruction cache does *not*
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* snoop from the data cache.
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*
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* @page: the address of the page to flush
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*/
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void __flush_dcache_icache(void *p)
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{
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unsigned long addr = (unsigned long)p;
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if (flush_coherent_icache(addr))
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return;
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clean_dcache_range(addr, addr + PAGE_SIZE);
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/*
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* We don't flush the icache on 44x. Those have a virtual icache and we
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* don't have access to the virtual address here (it's not the page
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* vaddr but where it's mapped in user space). The flushing of the
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* icache on these is handled elsewhere, when a change in the address
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* space occurs, before returning to user space.
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*/
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if (mmu_has_feature(MMU_FTR_TYPE_44x))
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return;
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invalidate_icache_range(addr, addr + PAGE_SIZE);
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}
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void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
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{
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clear_page(page);
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/*
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* We shouldn't have to do this, but some versions of glibc
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* require it (ld.so assumes zero filled pages are icache clean)
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* - Anton
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*/
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flush_dcache_page(pg);
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}
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EXPORT_SYMBOL(clear_user_page);
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void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
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struct page *pg)
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{
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copy_page(vto, vfrom);
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/*
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* We should be able to use the following optimisation, however
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* there are two problems.
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* Firstly a bug in some versions of binutils meant PLT sections
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* were not marked executable.
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* Secondly the first word in the GOT section is blrl, used
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* to establish the GOT address. Until recently the GOT was
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* not marked executable.
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* - Anton
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*/
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#if 0
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if (!vma->vm_file && ((vma->vm_flags & VM_EXEC) == 0))
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return;
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#endif
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flush_dcache_page(pg);
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}
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void flush_icache_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long addr, int len)
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{
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unsigned long maddr;
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maddr = (unsigned long) kmap(page) + (addr & ~PAGE_MASK);
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flush_icache_range(maddr, maddr + len);
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kunmap(page);
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}
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@ -12,45 +12,15 @@
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*/
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/gfp.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/memblock.h>
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#include <linux/highmem.h>
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#include <linux/initrd.h>
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#include <linux/pagemap.h>
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#include <linux/suspend.h>
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#include <linux/hugetlb.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include <linux/memremap.h>
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#include <linux/dma-direct.h>
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#include <linux/kprobes.h>
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#include <asm/prom.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <asm/mmu.h>
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#include <asm/smp.h>
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#include <asm/machdep.h>
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#include <asm/btext.h>
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#include <asm/tlb.h>
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#include <asm/sections.h>
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#include <asm/sparsemem.h>
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#include <asm/vdso.h>
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#include <asm/fixmap.h>
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#include <asm/swiotlb.h>
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#include <asm/rtas.h>
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#include <asm/kasan.h>
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#include <asm/svm.h>
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#include <asm/mmzone.h>
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#include <mm/mmu_decl.h>
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@ -340,257 +310,6 @@ void free_initmem(void)
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free_initmem_default(POISON_FREE_INITMEM);
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}
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/**
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* flush_coherent_icache() - if a CPU has a coherent icache, flush it
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* @addr: The base address to use (can be any valid address, the whole cache will be flushed)
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* Return true if the cache was flushed, false otherwise
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*/
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static inline bool flush_coherent_icache(unsigned long addr)
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{
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/*
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* For a snooping icache, we still need a dummy icbi to purge all the
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* prefetched instructions from the ifetch buffers. We also need a sync
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* before the icbi to order the the actual stores to memory that might
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* have modified instructions with the icbi.
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*/
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if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
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mb(); /* sync */
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allow_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
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icbi((void *)addr);
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prevent_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
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mb(); /* sync */
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isync();
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return true;
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}
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return false;
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}
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/**
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* invalidate_icache_range() - Flush the icache by issuing icbi across an address range
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* @start: the start address
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* @stop: the stop address (exclusive)
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*/
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static void invalidate_icache_range(unsigned long start, unsigned long stop)
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{
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unsigned long shift = l1_icache_shift();
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unsigned long bytes = l1_icache_bytes();
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char *addr = (char *)(start & ~(bytes - 1));
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unsigned long size = stop - (unsigned long)addr + (bytes - 1);
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unsigned long i;
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for (i = 0; i < size >> shift; i++, addr += bytes)
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icbi(addr);
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mb(); /* sync */
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isync();
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}
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/**
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* flush_icache_range: Write any modified data cache blocks out to memory
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* and invalidate the corresponding blocks in the instruction cache
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*
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* Generic code will call this after writing memory, before executing from it.
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*
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* @start: the start address
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* @stop: the stop address (exclusive)
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*/
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void flush_icache_range(unsigned long start, unsigned long stop)
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{
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if (flush_coherent_icache(start))
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return;
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clean_dcache_range(start, stop);
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if (IS_ENABLED(CONFIG_44x)) {
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/*
|
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* Flash invalidate on 44x because we are passed kmapped
|
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* addresses and this doesn't work for userspace pages due to
|
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* the virtually tagged icache.
|
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*/
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iccci((void *)start);
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mb(); /* sync */
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isync();
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} else
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invalidate_icache_range(start, stop);
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}
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EXPORT_SYMBOL(flush_icache_range);
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#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
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/**
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* flush_dcache_icache_phys() - Flush a page by it's physical address
|
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* @physaddr: the physical address of the page
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*/
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static void flush_dcache_icache_phys(unsigned long physaddr)
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{
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unsigned long bytes = l1_dcache_bytes();
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unsigned long nb = PAGE_SIZE / bytes;
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unsigned long addr = physaddr & PAGE_MASK;
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unsigned long msr, msr0;
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unsigned long loop1 = addr, loop2 = addr;
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msr0 = mfmsr();
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msr = msr0 & ~MSR_DR;
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/*
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* This must remain as ASM to prevent potential memory accesses
|
||||
* while the data MMU is disabled
|
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*/
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asm volatile(
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" mtctr %2;\n"
|
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" mtmsr %3;\n"
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" isync;\n"
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"0: dcbst 0, %0;\n"
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" addi %0, %0, %4;\n"
|
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" bdnz 0b;\n"
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" sync;\n"
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" mtctr %2;\n"
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"1: icbi 0, %1;\n"
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" addi %1, %1, %4;\n"
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" bdnz 1b;\n"
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" sync;\n"
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" mtmsr %5;\n"
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" isync;\n"
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: "+&r" (loop1), "+&r" (loop2)
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: "r" (nb), "r" (msr), "i" (bytes), "r" (msr0)
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: "ctr", "memory");
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}
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NOKPROBE_SYMBOL(flush_dcache_icache_phys)
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#endif // !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
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|
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/*
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||||
* This is called when a page has been modified by the kernel.
|
||||
* It just marks the page as not i-cache clean. We do the i-cache
|
||||
* flush later when the page is given to a user process, if necessary.
|
||||
*/
|
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void flush_dcache_page(struct page *page)
|
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{
|
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if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
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return;
|
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/* avoid an atomic op if possible */
|
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if (test_bit(PG_dcache_clean, &page->flags))
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clear_bit(PG_dcache_clean, &page->flags);
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}
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EXPORT_SYMBOL(flush_dcache_page);
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static void flush_dcache_icache_hugepage(struct page *page)
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{
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int i;
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void *start;
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BUG_ON(!PageCompound(page));
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for (i = 0; i < compound_nr(page); i++) {
|
||||
if (!PageHighMem(page)) {
|
||||
__flush_dcache_icache(page_address(page+i));
|
||||
} else {
|
||||
start = kmap_atomic(page+i);
|
||||
__flush_dcache_icache(start);
|
||||
kunmap_atomic(start);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void flush_dcache_icache_page(struct page *page)
|
||||
{
|
||||
|
||||
if (PageCompound(page))
|
||||
return flush_dcache_icache_hugepage(page);
|
||||
|
||||
#if defined(CONFIG_PPC_8xx) || defined(CONFIG_PPC64)
|
||||
/* On 8xx there is no need to kmap since highmem is not supported */
|
||||
__flush_dcache_icache(page_address(page));
|
||||
#else
|
||||
if (IS_ENABLED(CONFIG_BOOKE) || sizeof(phys_addr_t) > sizeof(void *)) {
|
||||
void *start = kmap_atomic(page);
|
||||
__flush_dcache_icache(start);
|
||||
kunmap_atomic(start);
|
||||
} else {
|
||||
unsigned long addr = page_to_pfn(page) << PAGE_SHIFT;
|
||||
|
||||
if (flush_coherent_icache(addr))
|
||||
return;
|
||||
flush_dcache_icache_phys(addr);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
EXPORT_SYMBOL(flush_dcache_icache_page);
|
||||
|
||||
/**
|
||||
* __flush_dcache_icache(): Flush a particular page from the data cache to RAM.
|
||||
* Note: this is necessary because the instruction cache does *not*
|
||||
* snoop from the data cache.
|
||||
*
|
||||
* @page: the address of the page to flush
|
||||
*/
|
||||
void __flush_dcache_icache(void *p)
|
||||
{
|
||||
unsigned long addr = (unsigned long)p;
|
||||
|
||||
if (flush_coherent_icache(addr))
|
||||
return;
|
||||
|
||||
clean_dcache_range(addr, addr + PAGE_SIZE);
|
||||
|
||||
/*
|
||||
* We don't flush the icache on 44x. Those have a virtual icache and we
|
||||
* don't have access to the virtual address here (it's not the page
|
||||
* vaddr but where it's mapped in user space). The flushing of the
|
||||
* icache on these is handled elsewhere, when a change in the address
|
||||
* space occurs, before returning to user space.
|
||||
*/
|
||||
|
||||
if (mmu_has_feature(MMU_FTR_TYPE_44x))
|
||||
return;
|
||||
|
||||
invalidate_icache_range(addr, addr + PAGE_SIZE);
|
||||
}
|
||||
|
||||
void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
|
||||
{
|
||||
clear_page(page);
|
||||
|
||||
/*
|
||||
* We shouldn't have to do this, but some versions of glibc
|
||||
* require it (ld.so assumes zero filled pages are icache clean)
|
||||
* - Anton
|
||||
*/
|
||||
flush_dcache_page(pg);
|
||||
}
|
||||
EXPORT_SYMBOL(clear_user_page);
|
||||
|
||||
void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
|
||||
struct page *pg)
|
||||
{
|
||||
copy_page(vto, vfrom);
|
||||
|
||||
/*
|
||||
* We should be able to use the following optimisation, however
|
||||
* there are two problems.
|
||||
* Firstly a bug in some versions of binutils meant PLT sections
|
||||
* were not marked executable.
|
||||
* Secondly the first word in the GOT section is blrl, used
|
||||
* to establish the GOT address. Until recently the GOT was
|
||||
* not marked executable.
|
||||
* - Anton
|
||||
*/
|
||||
#if 0
|
||||
if (!vma->vm_file && ((vma->vm_flags & VM_EXEC) == 0))
|
||||
return;
|
||||
#endif
|
||||
|
||||
flush_dcache_page(pg);
|
||||
}
|
||||
|
||||
void flush_icache_user_page(struct vm_area_struct *vma, struct page *page,
|
||||
unsigned long addr, int len)
|
||||
{
|
||||
unsigned long maddr;
|
||||
|
||||
maddr = (unsigned long) kmap(page) + (addr & ~PAGE_MASK);
|
||||
flush_icache_range(maddr, maddr + len);
|
||||
kunmap(page);
|
||||
}
|
||||
|
||||
/*
|
||||
* System memory should not be in /proc/iomem but various tools expect it
|
||||
* (eg kdump).
|
||||
|
||||
Loading…
Reference in New Issue
Block a user