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ARC: breakout timer include code into separate header ...
... which allows for use in drivers/clocksource later Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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@ -20,7 +20,6 @@
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#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
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#define ARC_REG_SLC_BCR 0xce
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#define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
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#define ARC_REG_TIMERS_BCR 0x75
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#define ARC_REG_AP_BCR 0x76
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#define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
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#define ARC_REG_XY_MEM_BCR 0x79
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@ -208,13 +207,7 @@ struct bcr_fp_arcv2 {
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#endif
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};
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struct bcr_timer {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
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#else
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unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
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#endif
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};
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#include <soc/arc/timers.h>
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struct bcr_bpu_arcompact {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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@ -38,22 +38,10 @@
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <asm/irq.h>
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#include <asm/arcregs.h>
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#include <soc/arc/timers.h>
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#include <soc/arc/mcip.h>
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/* Timer related Aux registers */
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#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
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#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
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#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
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#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
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#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
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#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
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#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
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#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
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#define ARC_TIMER_MAX 0xFFFFFFFF
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static unsigned long arc_timer_freq;
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@ -218,7 +206,7 @@ static int __init arc_cs_setup_timer1(struct device_node *node)
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if (ret)
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return ret;
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write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
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write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
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write_aux_reg(ARC_REG_TIMER1_CNT, 0);
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write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
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@ -296,7 +284,7 @@ static int arc_timer_starting_cpu(unsigned int cpu)
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evt->cpumask = cpumask_of(smp_processor_id());
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clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMER_MAX);
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clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
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enable_percpu_irq(arc_timer_irq, 0);
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return 0;
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}
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38
include/soc/arc/timers.h
Normal file
38
include/soc/arc/timers.h
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@ -0,0 +1,38 @@
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/*
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* Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __SOC_ARC_TIMERS_H
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#define __SOC_ARC_TIMERS_H
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#include <soc/arc/aux.h>
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/* Timer related Aux registers */
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#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
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#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
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#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
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#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
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#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
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#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
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/* CTRL reg bits */
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#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
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#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
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#define ARC_TIMERN_MAX 0xFFFFFFFF
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#define ARC_REG_TIMERS_BCR 0x75
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struct bcr_timer {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
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#else
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unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
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#endif
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};
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#endif
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