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Xtensa fixes for v4.20-rc5
- Fix kernel exception on userspace access to a currently disabled coprocessor. - Fix coprocessor data saving/restoring in configurations with multiple coprocessors. - Fix ptrace access to coprocessor data on configurations with multiple coprocessors with high alignment requirements. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAlv+9BMTHGpjbXZia2Jj QGdtYWlsLmNvbQAKCRBR+cyR+D+gRDhoEACGPL70EorwnapQZKN1QOTUuvxrw/u6 AQc+Vgi7KWuYYD+otPAhHNTuPdzai6bdrlR9xsyLABgWgFWsVXP9lLCa9frvwXwH A0024o+9Gf6KoZfGJ0dOkcd3BwAuRJa32n49Euqyyjb2Qj5Da6fY8js8iT1/tJER cSMfAyLS97GJy4fOwXY7xVrafsEEw45ehjQ6DtUGHX6s9zxfdwkfsFf2QpH65oTC FHofKcLdz+BAUQe+vdD2VEJjl8YYswdaYau+620dnsI05B8m7m0Gof3aY4ZmmAq3 fSQxisSfiE1BUlTdlMlnel+S0J1EPv1qDxA+k4/TqV8extB2BlZ2cq0BLE6YUJ6B LnZdS7xNrB1+YxM/ckRs4hxfqGrjVtUDg3peBx8b5Aq9TOSNWA0/qbNVI89V+Dzp L9aEZgmZGwn1YTFCUJO5unb8QNYvoSOKxwfRlcrYfmF44/UNaiqBaoz3eSsrYEbG baQidK/wdnGTTLUhB/KlpZDkFyXZ20c9vN/O7HEpo+rhO1NP726Cn9rU+bSS+rRE ezYF5+8WxfsUuGxuXhHq2QiDWLJxeqN+NUf8z/dwBYT0UgAOcH7X/zN/oNIxeD5R eplI5DLWZuo2uPq5ALmMWsTlaSClaP1tlJXmn9pHkT3KPRoC+ndkh0hEBFKUS/f7 9zDrKipT5+Temg== =XEua -----END PGP SIGNATURE----- Merge tag 'xtensa-20181128' of git://github.com/jcmvbkbc/linux-xtensa Pull Xtensa fixes from Max Filippov: - fix kernel exception on userspace access to a currently disabled coprocessor - fix coprocessor data saving/restoring in configurations with multiple coprocessors - fix ptrace access to coprocessor data on configurations with multiple coprocessors with high alignment requirements * tag 'xtensa-20181128' of git://github.com/jcmvbkbc/linux-xtensa: xtensa: fix coprocessor part of ptrace_{get,set}xregs xtensa: fix coprocessor context offset definitions xtensa: enable coprocessors that are being flushed
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b26b2b24b1
@ -94,14 +94,14 @@ int main(void)
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DEFINE(THREAD_SP, offsetof (struct task_struct, thread.sp));
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DEFINE(THREAD_CPENABLE, offsetof (struct thread_info, cpenable));
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#if XTENSA_HAVE_COPROCESSORS
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DEFINE(THREAD_XTREGS_CP0, offsetof (struct thread_info, xtregs_cp));
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DEFINE(THREAD_XTREGS_CP1, offsetof (struct thread_info, xtregs_cp));
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DEFINE(THREAD_XTREGS_CP2, offsetof (struct thread_info, xtregs_cp));
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DEFINE(THREAD_XTREGS_CP3, offsetof (struct thread_info, xtregs_cp));
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DEFINE(THREAD_XTREGS_CP4, offsetof (struct thread_info, xtregs_cp));
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DEFINE(THREAD_XTREGS_CP5, offsetof (struct thread_info, xtregs_cp));
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DEFINE(THREAD_XTREGS_CP6, offsetof (struct thread_info, xtregs_cp));
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DEFINE(THREAD_XTREGS_CP7, offsetof (struct thread_info, xtregs_cp));
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DEFINE(THREAD_XTREGS_CP0, offsetof(struct thread_info, xtregs_cp.cp0));
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DEFINE(THREAD_XTREGS_CP1, offsetof(struct thread_info, xtregs_cp.cp1));
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DEFINE(THREAD_XTREGS_CP2, offsetof(struct thread_info, xtregs_cp.cp2));
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DEFINE(THREAD_XTREGS_CP3, offsetof(struct thread_info, xtregs_cp.cp3));
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DEFINE(THREAD_XTREGS_CP4, offsetof(struct thread_info, xtregs_cp.cp4));
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DEFINE(THREAD_XTREGS_CP5, offsetof(struct thread_info, xtregs_cp.cp5));
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DEFINE(THREAD_XTREGS_CP6, offsetof(struct thread_info, xtregs_cp.cp6));
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DEFINE(THREAD_XTREGS_CP7, offsetof(struct thread_info, xtregs_cp.cp7));
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#endif
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DEFINE(THREAD_XTREGS_USER, offsetof (struct thread_info, xtregs_user));
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DEFINE(XTREGS_USER_SIZE, sizeof(xtregs_user_t));
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@ -94,18 +94,21 @@ void coprocessor_release_all(struct thread_info *ti)
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void coprocessor_flush_all(struct thread_info *ti)
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{
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unsigned long cpenable;
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unsigned long cpenable, old_cpenable;
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int i;
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preempt_disable();
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RSR_CPENABLE(old_cpenable);
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cpenable = ti->cpenable;
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WSR_CPENABLE(cpenable);
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for (i = 0; i < XCHAL_CP_MAX; i++) {
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if ((cpenable & 1) != 0 && coprocessor_owner[i] == ti)
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coprocessor_flush(ti, i);
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cpenable >>= 1;
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}
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WSR_CPENABLE(old_cpenable);
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preempt_enable();
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}
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@ -127,12 +127,37 @@ static int ptrace_setregs(struct task_struct *child, void __user *uregs)
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}
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#if XTENSA_HAVE_COPROCESSORS
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#define CP_OFFSETS(cp) \
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{ \
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.elf_xtregs_offset = offsetof(elf_xtregs_t, cp), \
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.ti_offset = offsetof(struct thread_info, xtregs_cp.cp), \
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.sz = sizeof(xtregs_ ## cp ## _t), \
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}
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static const struct {
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size_t elf_xtregs_offset;
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size_t ti_offset;
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size_t sz;
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} cp_offsets[] = {
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CP_OFFSETS(cp0),
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CP_OFFSETS(cp1),
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CP_OFFSETS(cp2),
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CP_OFFSETS(cp3),
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CP_OFFSETS(cp4),
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CP_OFFSETS(cp5),
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CP_OFFSETS(cp6),
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CP_OFFSETS(cp7),
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};
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#endif
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static int ptrace_getxregs(struct task_struct *child, void __user *uregs)
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{
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struct pt_regs *regs = task_pt_regs(child);
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struct thread_info *ti = task_thread_info(child);
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elf_xtregs_t __user *xtregs = uregs;
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int ret = 0;
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int i __maybe_unused;
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if (!access_ok(VERIFY_WRITE, uregs, sizeof(elf_xtregs_t)))
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return -EIO;
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@ -140,8 +165,13 @@ static int ptrace_getxregs(struct task_struct *child, void __user *uregs)
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#if XTENSA_HAVE_COPROCESSORS
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/* Flush all coprocessor registers to memory. */
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coprocessor_flush_all(ti);
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ret |= __copy_to_user(&xtregs->cp0, &ti->xtregs_cp,
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sizeof(xtregs_coprocessor_t));
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for (i = 0; i < ARRAY_SIZE(cp_offsets); ++i)
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ret |= __copy_to_user((char __user *)xtregs +
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cp_offsets[i].elf_xtregs_offset,
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(const char *)ti +
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cp_offsets[i].ti_offset,
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cp_offsets[i].sz);
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#endif
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ret |= __copy_to_user(&xtregs->opt, ®s->xtregs_opt,
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sizeof(xtregs->opt));
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@ -157,6 +187,7 @@ static int ptrace_setxregs(struct task_struct *child, void __user *uregs)
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struct pt_regs *regs = task_pt_regs(child);
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elf_xtregs_t *xtregs = uregs;
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int ret = 0;
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int i __maybe_unused;
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if (!access_ok(VERIFY_READ, uregs, sizeof(elf_xtregs_t)))
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return -EFAULT;
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@ -166,8 +197,11 @@ static int ptrace_setxregs(struct task_struct *child, void __user *uregs)
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coprocessor_flush_all(ti);
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coprocessor_release_all(ti);
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ret |= __copy_from_user(&ti->xtregs_cp, &xtregs->cp0,
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sizeof(xtregs_coprocessor_t));
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for (i = 0; i < ARRAY_SIZE(cp_offsets); ++i)
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ret |= __copy_from_user((char *)ti + cp_offsets[i].ti_offset,
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(const char __user *)xtregs +
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cp_offsets[i].elf_xtregs_offset,
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cp_offsets[i].sz);
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#endif
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ret |= __copy_from_user(®s->xtregs_opt, &xtregs->opt,
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sizeof(xtregs->opt));
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