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interconnect changes for 6.8

Browse Source 
This pull request contains the interconnect changes for the 6.8-rc1 merge
 window. These are just driver changes with the following highlights:
 
 Driver changes:
 - New interconnect driver for the SM8650 platform.
 - New interconnect driver for the SM6115 platform.
 - New interconnect driver for the X1E80100 (Snapdragon X Elite) platform.
 - Add compatible string for the BWMONv4 instance on the QCM2290 platform.
 - Complete the platform drivers conversion to the .remove_new callback
   returning void (mostly iMX, Exynos and the rest of Qcom drivers).
 
 Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Merge tag 'icc-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next

Georgi writes:

interconnect changes for 6.8

This pull request contains the interconnect changes for the 6.8-rc1 merge
window. These are just driver changes with the following highlights:

Driver changes:
- New interconnect driver for the SM8650 platform.
- New interconnect driver for the SM6115 platform.
- New interconnect driver for the X1E80100 (Snapdragon X Elite) platform.
- Add compatible string for the BWMONv4 instance on the QCM2290 platform.
- Complete the platform drivers conversion to the .remove_new callback
  returning void (mostly iMX, Exynos and the rest of Qcom drivers).

Signed-off-by: Georgi Djakov <djakov@kernel.org>

* tag 'icc-6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
  interconnect: qcom: sm6115: Fix up includes
  dt-bindings: interconnect: qcom,msm8998-bwmon: Add QCM2290 bwmon instance
  dt-bindings: interconnect: qcom,msm8998-bwmon: Add SM6115 bwmon instance
  interconnect: qcom: Add SM6115 interconnect provider driver
  dt-bindings: interconnect: Add Qualcomm SM6115 NoC
  interconnect: qcom: Add X1E80100 interconnect provider driver
  dt-bindings: interconnect: Add Qualcomm X1E80100 SoC
  dt-bindings: interconnect: qcom-bwmon: document SM8650 BWMONs
  interconnect: qcom: introduce RPMh Network-On-Chip Interconnect on SM8650 SoC
  dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm SM8650 SoC
  interconnect: exynos: Convert to platform remove callback returning void
  interconnect: qcom/smd-rpm: Convert to platform remove callback returning void
  interconnect: qcom/osm-l3: Convert to platform remove callback returning void
  interconnect: qcom/msm8974: Convert to platform remove callback returning void
  interconnect: imx8mq: Convert to platform remove callback returning void
  interconnect: imx8mp: Convert to platform remove callback returning void
  interconnect: imx8mn: Convert to platform remove callback returning void
  interconnect: imx8mm: Convert to platform remove callback returning void
  interconnect: qcom: Make qnoc_remove return void
This commit is contained in:
Greg Kroah-Hartman 2023-12-23 13:48:17 +01:00
commit b2231e4875
30 changed files with 6660 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
View File

@ -25,13 +25,16 @@ properties:
- const: qcom,msm8998-bwmon # BWMON v4
- items:
- enum:
- qcom,qcm2290-cpu-bwmon
- qcom,sc7180-cpu-bwmon
- qcom,sc7280-cpu-bwmon
- qcom,sc8280xp-cpu-bwmon
- qcom,sdm845-cpu-bwmon
- qcom,sm6115-cpu-bwmon
- qcom,sm6350-llcc-bwmon
- qcom,sm8250-cpu-bwmon
- qcom,sm8550-cpu-bwmon
- qcom,sm8650-cpu-bwmon
- const: qcom,sdm845-bwmon # BWMON v4, unified register space
- items:
- enum:
@ -40,6 +43,7 @@ properties:
- qcom,sm6350-cpu-bwmon
- qcom,sm8250-llcc-bwmon
- qcom,sm8550-llcc-bwmon
- qcom,sm8650-llcc-bwmon
- const: qcom,sc7280-llcc-bwmon
- const: qcom,sc7280-llcc-bwmon # BWMON v5
- const: qcom,sdm845-llcc-bwmon # BWMON v5

152
Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml Normal file
View File

@ -0,0 +1,152 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm6115.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM6115 Network-On-Chip interconnect
maintainers:
- Konrad Dybcio <konradybcio@kernel.org>
description:
The Qualcomm SM6115 interconnect providers support adjusting the
bandwidth requirements between the various NoC fabrics.
properties:
compatible:
enum:
- qcom,sm6115-bimc
- qcom,sm6115-cnoc
- qcom,sm6115-snoc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
# Child node's properties
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
description:
The interconnect providers do not have a separate QoS register space,
but share parent's space.
$ref: qcom,rpm-common.yaml#
properties:
compatible:
enum:
- qcom,sm6115-clk-virt
- qcom,sm6115-mmrt-virt
- qcom,sm6115-mmnrt-virt
required:
- compatible
unevaluatedProperties: false
required:
- compatible
- reg
allOf:
- $ref: qcom,rpm-common.yaml#
- if:
properties:
compatible:
const: qcom,sm6115-cnoc
then:
properties:
clocks:
items:
- description: USB-NoC AXI clock
clock-names:
items:
- const: usb_axi
- if:
properties:
compatible:
const: qcom,sm6115-snoc
then:
properties:
clocks:
items:
- description: CPU-NoC AXI clock.
- description: UFS-NoC AXI clock.
- description: USB-NoC AXI clock.
- description: IPA clock.
clock-names:
items:
- const: cpu_axi
- const: ufs_axi
- const: usb_axi
- const: ipa
- if:
properties:
compatible:
enum:
- qcom,sm6115-bimc
- qcom,sm6115-clk-virt
- qcom,sm6115-mmrt-virt
- qcom,sm6115-mmnrt-virt
then:
properties:
clocks: false
clock-names: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
snoc: interconnect@1880000 {
compatible = "qcom,sm6115-snoc";
reg = <0x01880000 0x60200>;
clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
<&rpmcc RPM_SMD_IPA_CLK>;
clock-names = "cpu_axi",
"ufs_axi",
"usb_axi",
"ipa";
#interconnect-cells = <1>;
qup_virt: interconnect-clk {
compatible = "qcom,sm6115-clk-virt";
#interconnect-cells = <1>;
};
mmnrt_virt: interconnect-mmnrt {
compatible = "qcom,sm6115-mmnrt-virt";
#interconnect-cells = <1>;
};
mmrt_virt: interconnect-mmrt {
compatible = "qcom,sm6115-mmrt-virt";
#interconnect-cells = <1>;
};
};
cnoc: interconnect@1900000 {
compatible = "qcom,sm6115-cnoc";
reg = <0x01900000 0x8200>;
#interconnect-cells = <1>;
};

136
Documentation/devicetree/bindings/interconnect/qcom,sm8650-rpmh.yaml Normal file
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@ -0,0 +1,136 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650
maintainers:
- Abel Vesa <abel.vesa@linaro.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
properties:
compatible:
enum:
- qcom,sm8650-aggre1-noc
- qcom,sm8650-aggre2-noc
- qcom,sm8650-clk-virt
- qcom,sm8650-cnoc-main
- qcom,sm8650-config-noc
- qcom,sm8650-gem-noc
- qcom,sm8650-lpass-ag-noc
- qcom,sm8650-lpass-lpiaon-noc
- qcom,sm8650-lpass-lpicx-noc
- qcom,sm8650-mc-virt
- qcom,sm8650-mmss-noc
- qcom,sm8650-nsp-noc
- qcom,sm8650-pcie-anoc
- qcom,sm8650-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-clk-virt
- qcom,sm8650-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-pcie-anoc
then:
properties:
clocks:
items:
- description: aggre-NOC PCIe AXI clock
- description: cfg-NOC PCIe a-NOC AHB clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- description: aggre USB3 PRIM AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-aggre2-noc
then:
properties:
clocks:
items:
- description: RPMH CC IPA clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-aggre1-noc
- qcom,sm8650-aggre2-noc
- qcom,sm8650-pcie-anoc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
clk_virt: interconnect-0 {
compatible = "qcom,sm8650-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8650-aggre1-noc";
reg = <0x016e0000 0x14400>;
#interconnect-cells = <2>;
clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

83
Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml Normal file
View File

@ -0,0 +1,83 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,x1e80100-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on X1E80100
maintainers:
- Rajendra Nayak <quic_rjendra@quicinc.com>
- Abel Vesa <abel.vesa@linaro.org>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also:: include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
properties:
compatible:
enum:
- qcom,x1e80100-aggre1-noc
- qcom,x1e80100-aggre2-noc
- qcom,x1e80100-clk-virt
- qcom,x1e80100-cnoc-cfg
- qcom,x1e80100-cnoc-main
- qcom,x1e80100-gem-noc
- qcom,x1e80100-lpass-ag-noc
- qcom,x1e80100-lpass-lpiaon-noc
- qcom,x1e80100-lpass-lpicx-noc
- qcom,x1e80100-mc-virt
- qcom,x1e80100-mmss-noc
- qcom,x1e80100-nsp-noc
- qcom,x1e80100-pcie-center-anoc
- qcom,x1e80100-pcie-north-anoc
- qcom,x1e80100-pcie-south-anoc
- qcom,x1e80100-system-noc
- qcom,x1e80100-usb-center-anoc
- qcom,x1e80100-usb-north-anoc
- qcom,x1e80100-usb-south-anoc
reg:
maxItems: 1
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,x1e80100-clk-virt
- qcom,x1e80100-mc-virt
then:
properties:
reg: false
else:
required:
- reg
unevaluatedProperties: false
examples:
- |
clk_virt: interconnect-0 {
compatible = "qcom,x1e80100-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,x1e80100-aggre1-noc";
reg = <0x016e0000 0x14400>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};

9
drivers/interconnect/imx/imx8mm.c
View File

@ -86,16 +86,9 @@ static int imx8mm_icc_probe(struct platform_device *pdev)
return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL);
}
static int imx8mm_icc_remove(struct platform_device *pdev)
{
imx_icc_unregister(pdev);
return 0;
}
static struct platform_driver imx8mm_icc_driver = {
.probe = imx8mm_icc_probe,
.remove = imx8mm_icc_remove,
.remove_new = imx_icc_unregister,
.driver = {
.name = "imx8mm-interconnect",
},

9
drivers/interconnect/imx/imx8mn.c
View File

@ -75,16 +75,9 @@ static int imx8mn_icc_probe(struct platform_device *pdev)
return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL);
}
static int imx8mn_icc_remove(struct platform_device *pdev)
{
imx_icc_unregister(pdev);
return 0;
}
static struct platform_driver imx8mn_icc_driver = {
.probe = imx8mn_icc_probe,
.remove = imx8mn_icc_remove,
.remove_new = imx_icc_unregister,
.driver = {
.name = "imx8mn-interconnect",
},

9
drivers/interconnect/imx/imx8mp.c
View File

@ -239,16 +239,9 @@ static int imx8mp_icc_probe(struct platform_device *pdev)
return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), noc_setting_nodes);
}
static int imx8mp_icc_remove(struct platform_device *pdev)
{
imx_icc_unregister(pdev);
return 0;
}
static struct platform_driver imx8mp_icc_driver = {
.probe = imx8mp_icc_probe,
.remove = imx8mp_icc_remove,
.remove_new = imx_icc_unregister,
.driver = {
.name = "imx8mp-interconnect",
},

9
drivers/interconnect/imx/imx8mq.c
View File

@ -85,16 +85,9 @@ static int imx8mq_icc_probe(struct platform_device *pdev)
return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL);
}
static int imx8mq_icc_remove(struct platform_device *pdev)
{
imx_icc_unregister(pdev);
return 0;
}
static struct platform_driver imx8mq_icc_driver = {
.probe = imx8mq_icc_probe,
.remove = imx8mq_icc_remove,
.remove_new = imx_icc_unregister,
.driver = {
.name = "imx8mq-interconnect",
.sync_state = icc_sync_state,

27
drivers/interconnect/qcom/Kconfig
View File

@ -191,6 +191,15 @@ config INTERCONNECT_QCOM_SDX75
This is a driver for the Qualcomm Network-on-Chip on sdx75-based
platforms.
config INTERCONNECT_QCOM_SM6115
tristate "Qualcomm SM6115 interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
help
This is a driver for the Qualcomm Network-on-Chip on sm6115-based
platforms.
config INTERCONNECT_QCOM_SM6350
tristate "Qualcomm SM6350 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
@ -245,5 +254,23 @@ config INTERCONNECT_QCOM_SM8550
This is a driver for the Qualcomm Network-on-Chip on SM8550-based
platforms.
config INTERCONNECT_QCOM_SM8650
tristate "Qualcomm SM8650 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on SM8650-based
platforms.
config INTERCONNECT_QCOM_X1E80100
tristate "Qualcomm X1E80100 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on X1E80100-based
platforms.
config INTERCONNECT_QCOM_SMD_RPM
tristate

6
drivers/interconnect/qcom/Makefile
View File

@ -24,12 +24,15 @@ qnoc-sdm845-objs := sdm845.o
qnoc-sdx55-objs := sdx55.o
qnoc-sdx65-objs := sdx65.o
qnoc-sdx75-objs := sdx75.o
qnoc-sm6115-objs := sm6115.o
qnoc-sm6350-objs := sm6350.o
qnoc-sm8150-objs := sm8150.o
qnoc-sm8250-objs := sm8250.o
qnoc-sm8350-objs := sm8350.o
qnoc-sm8450-objs := sm8450.o
qnoc-sm8550-objs := sm8550.o
qnoc-sm8650-objs := sm8650.o
qnoc-x1e80100-objs := x1e80100.o
icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
@ -53,10 +56,13 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM6115) += qnoc-sm6115.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8450) += qnoc-sm8450.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8550) += qnoc-sm8550.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8650) += qnoc-sm8650.o
obj-$(CONFIG_INTERCONNECT_QCOM_X1E80100) += qnoc-x1e80100.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o

4
drivers/interconnect/qcom/icc-rpm.c
View File

@ -627,14 +627,12 @@ err_disable_unprepare_clk:
}
EXPORT_SYMBOL(qnoc_probe);
int qnoc_remove(struct platform_device *pdev)
void qnoc_remove(struct platform_device *pdev)
{
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
icc_provider_deregister(&qp->provider);
icc_nodes_remove(&qp->provider);
clk_disable_unprepare(qp->bus_clk);
return 0;
}
EXPORT_SYMBOL(qnoc_remove);

2
drivers/interconnect/qcom/icc-rpm.h
View File

@ -161,7 +161,7 @@ extern const struct rpm_clk_resource aggre1_branch_clk;
extern const struct rpm_clk_resource aggre2_branch_clk;
int qnoc_probe(struct platform_device *pdev);
int qnoc_remove(struct platform_device *pdev);
void qnoc_remove(struct platform_device *pdev);
bool qcom_icc_rpm_smd_available(void);
int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);

2
drivers/interconnect/qcom/msm8916.c
View File

@ -1344,7 +1344,7 @@ MODULE_DEVICE_TABLE(of, msm8916_noc_of_match);
static struct platform_driver msm8916_noc_driver = {
.probe = qnoc_probe,
.remove = qnoc_remove,
.remove_new = qnoc_remove,
.driver = {
.name = "qnoc-msm8916",
.of_match_table = msm8916_noc_of_match,

2
drivers/interconnect/qcom/msm8939.c
View File

@ -1421,7 +1421,7 @@ MODULE_DEVICE_TABLE(of, msm8939_noc_of_match);
static struct platform_driver msm8939_noc_driver = {
.probe = qnoc_probe,
.remove = qnoc_remove,
.remove_new = qnoc_remove,
.driver = {
.name = "qnoc-msm8939",
.of_match_table = msm8939_noc_of_match,

6
drivers/interconnect/qcom/msm8974.c
View File

@ -740,15 +740,13 @@ err_remove_nodes:
return ret;
}
static int msm8974_icc_remove(struct platform_device *pdev)
static void msm8974_icc_remove(struct platform_device *pdev)
{
struct msm8974_icc_provider *qp = platform_get_drvdata(pdev);
icc_provider_deregister(&qp->provider);
icc_nodes_remove(&qp->provider);
clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
return 0;
}
static const struct of_device_id msm8974_noc_of_match[] = {
@ -764,7 +762,7 @@ MODULE_DEVICE_TABLE(of, msm8974_noc_of_match);
static struct platform_driver msm8974_noc_driver = {
.probe = msm8974_icc_probe,
.remove = msm8974_icc_remove,
.remove_new = msm8974_icc_remove,
.driver = {
.name = "qnoc-msm8974",
.of_match_table = msm8974_noc_of_match,

2
drivers/interconnect/qcom/msm8996.c
View File

@ -2108,7 +2108,7 @@ MODULE_DEVICE_TABLE(of, qnoc_of_match);
static struct platform_driver qnoc_driver = {
.probe = qnoc_probe,
.remove = qnoc_remove,
.remove_new = qnoc_remove,
.driver = {
.name = "qnoc-msm8996",
.of_match_table = qnoc_of_match,

6
drivers/interconnect/qcom/osm-l3.c
View File

@ -148,14 +148,12 @@ static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
return 0;
}
static int qcom_osm_l3_remove(struct platform_device *pdev)
static void qcom_osm_l3_remove(struct platform_device *pdev)
{
struct qcom_osm_l3_icc_provider *qp = platform_get_drvdata(pdev);
icc_provider_deregister(&qp->provider);
icc_nodes_remove(&qp->provider);
return 0;
}
static int qcom_osm_l3_probe(struct platform_device *pdev)
@ -292,7 +290,7 @@ MODULE_DEVICE_TABLE(of, osm_l3_of_match);
static struct platform_driver osm_l3_driver = {
.probe = qcom_osm_l3_probe,
.remove = qcom_osm_l3_remove,
.remove_new = qcom_osm_l3_remove,
.driver = {
.name = "osm-l3",
.of_match_table = osm_l3_of_match,

2
drivers/interconnect/qcom/qcm2290.c
View File

@ -1367,7 +1367,7 @@ MODULE_DEVICE_TABLE(of, qcm2290_noc_of_match);
static struct platform_driver qcm2290_noc_driver = {
.probe = qnoc_probe,
.remove = qnoc_remove,
.remove_new = qnoc_remove,
.driver = {
.name = "qnoc-qcm2290",
.of_match_table = qcm2290_noc_of_match,

2
drivers/interconnect/qcom/qcs404.c
View File

@ -1083,7 +1083,7 @@ MODULE_DEVICE_TABLE(of, qcs404_noc_of_match);
static struct platform_driver qcs404_noc_driver = {
.probe = qnoc_probe,
.remove = qnoc_remove,
.remove_new = qnoc_remove,
.driver = {
.name = "qnoc-qcs404",
.of_match_table = qcs404_noc_of_match,

2
drivers/interconnect/qcom/sdm660.c
View File

@ -1714,7 +1714,7 @@ MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);
static struct platform_driver sdm660_noc_driver = {
.probe = qnoc_probe,
.remove = qnoc_remove,
.remove_new = qnoc_remove,
.driver = {
.name = "qnoc-sdm660",
.of_match_table = sdm660_noc_of_match,

1423
drivers/interconnect/qcom/sm6115.c Normal file
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File diff suppressed because it is too large Load Diff

1674
drivers/interconnect/qcom/sm8650.c Normal file
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File diff suppressed because it is too large Load Diff

143
drivers/interconnect/qcom/sm8650.h Normal file
View File

@ -0,0 +1,143 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SM8650 interconnect IDs
*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8650_H
#define SM8650_MASTER_A1NOC_SNOC 0
#define SM8650_MASTER_A2NOC_SNOC 1
#define SM8650_MASTER_ANOC_PCIE_GEM_NOC 2
#define SM8650_MASTER_APPSS_PROC 3
#define SM8650_MASTER_CAMNOC_HF 4
#define SM8650_MASTER_CAMNOC_ICP 5
#define SM8650_MASTER_CAMNOC_SF 6
#define SM8650_MASTER_CDSP_HCP 7
#define SM8650_MASTER_CDSP_PROC 8
#define SM8650_MASTER_CNOC_CFG 9
#define SM8650_MASTER_CNOC_MNOC_CFG 10
#define SM8650_MASTER_COMPUTE_NOC 11
#define SM8650_MASTER_CRYPTO 12
#define SM8650_MASTER_GEM_NOC_CNOC 13
#define SM8650_MASTER_GEM_NOC_PCIE_SNOC 14
#define SM8650_MASTER_GFX3D 15
#define SM8650_MASTER_GIC 16
#define SM8650_MASTER_GPU_TCU 17
#define SM8650_MASTER_IPA 18
#define SM8650_MASTER_LLCC 19
#define SM8650_MASTER_LPASS_GEM_NOC 20
#define SM8650_MASTER_LPASS_LPINOC 21
#define SM8650_MASTER_LPASS_PROC 22
#define SM8650_MASTER_LPIAON_NOC 23
#define SM8650_MASTER_MDP 24
#define SM8650_MASTER_MNOC_HF_MEM_NOC 25
#define SM8650_MASTER_MNOC_SF_MEM_NOC 26
#define SM8650_MASTER_MSS_PROC 27
#define SM8650_MASTER_PCIE_0 28
#define SM8650_MASTER_PCIE_1 29
#define SM8650_MASTER_PCIE_ANOC_CFG 30
#define SM8650_MASTER_QDSS_BAM 31
#define SM8650_MASTER_QDSS_ETR 32
#define SM8650_MASTER_QDSS_ETR_1 33
#define SM8650_MASTER_QSPI_0 34
#define SM8650_MASTER_QUP_1 35
#define SM8650_MASTER_QUP_2 36
#define SM8650_MASTER_QUP_3 37
#define SM8650_MASTER_QUP_CORE_0 38
#define SM8650_MASTER_QUP_CORE_1 39
#define SM8650_MASTER_QUP_CORE_2 40
#define SM8650_MASTER_SDCC_2 41
#define SM8650_MASTER_SDCC_4 42
#define SM8650_MASTER_SNOC_SF_MEM_NOC 43
#define SM8650_MASTER_SP 44
#define SM8650_MASTER_SYS_TCU 45
#define SM8650_MASTER_UBWC_P 46
#define SM8650_MASTER_UBWC_P_TCU 47
#define SM8650_MASTER_UFS_MEM 48
#define SM8650_MASTER_USB3_0 49
#define SM8650_MASTER_VIDEO 50
#define SM8650_MASTER_VIDEO_CV_PROC 51
#define SM8650_MASTER_VIDEO_PROC 52
#define SM8650_MASTER_VIDEO_V_PROC 53
#define SM8650_SLAVE_A1NOC_SNOC 54
#define SM8650_SLAVE_A2NOC_SNOC 55
#define SM8650_SLAVE_AHB2PHY_NORTH 56
#define SM8650_SLAVE_AHB2PHY_SOUTH 57
#define SM8650_SLAVE_ANOC_PCIE_GEM_NOC 58
#define SM8650_SLAVE_AOSS 59
#define SM8650_SLAVE_APPSS 60
#define SM8650_SLAVE_CAMERA_CFG 61
#define SM8650_SLAVE_CDSP_MEM_NOC 62
#define SM8650_SLAVE_CLK_CTL 63
#define SM8650_SLAVE_CNOC_CFG 64
#define SM8650_SLAVE_CNOC_MNOC_CFG 65
#define SM8650_SLAVE_CNOC_MSS 66
#define SM8650_SLAVE_CPR_HMX 67
#define SM8650_SLAVE_CPR_NSPCX 68
#define SM8650_SLAVE_CRYPTO_0_CFG 69
#define SM8650_SLAVE_CX_RDPM 70
#define SM8650_SLAVE_DDRSS_CFG 71
#define SM8650_SLAVE_DISPLAY_CFG 72
#define SM8650_SLAVE_EBI1 73
#define SM8650_SLAVE_GEM_NOC_CNOC 74
#define SM8650_SLAVE_GFX3D_CFG 75
#define SM8650_SLAVE_I2C 76
#define SM8650_SLAVE_I3C_IBI0_CFG 77
#define SM8650_SLAVE_I3C_IBI1_CFG 78
#define SM8650_SLAVE_IMEM 79
#define SM8650_SLAVE_IMEM_CFG 80
#define SM8650_SLAVE_IPA_CFG 81
#define SM8650_SLAVE_IPC_ROUTER_CFG 82
#define SM8650_SLAVE_LLCC 83
#define SM8650_SLAVE_LPASS_GEM_NOC 84
#define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC 85
#define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC 86
#define SM8650_SLAVE_MEM_NOC_PCIE_SNOC 87
#define SM8650_SLAVE_MNOC_HF_MEM_NOC 88
#define SM8650_SLAVE_MNOC_SF_MEM_NOC 89
#define SM8650_SLAVE_MX_2_RDPM 90
#define SM8650_SLAVE_MX_RDPM 91
#define SM8650_SLAVE_NSP_QTB_CFG 92
#define SM8650_SLAVE_PCIE_0 93
#define SM8650_SLAVE_PCIE_1 94
#define SM8650_SLAVE_PCIE_0_CFG 95
#define SM8650_SLAVE_PCIE_1_CFG 96
#define SM8650_SLAVE_PCIE_ANOC_CFG 97
#define SM8650_SLAVE_PCIE_RSCC 98
#define SM8650_SLAVE_PDM 99
#define SM8650_SLAVE_PRNG 100
#define SM8650_SLAVE_QDSS_CFG 101
#define SM8650_SLAVE_QDSS_STM 102
#define SM8650_SLAVE_QSPI_0 103
#define SM8650_SLAVE_QUP_1 104
#define SM8650_SLAVE_QUP_2 105
#define SM8650_SLAVE_QUP_3 106
#define SM8650_SLAVE_QUP_CORE_0 107
#define SM8650_SLAVE_QUP_CORE_1 108
#define SM8650_SLAVE_QUP_CORE_2 109
#define SM8650_SLAVE_RBCPR_CX_CFG 110
#define SM8650_SLAVE_RBCPR_MMCX_CFG 111
#define SM8650_SLAVE_RBCPR_MXA_CFG 112
#define SM8650_SLAVE_RBCPR_MXC_CFG 113
#define SM8650_SLAVE_SDCC_2 114
#define SM8650_SLAVE_SDCC_4 115
#define SM8650_SLAVE_SERVICE_CNOC 116
#define SM8650_SLAVE_SERVICE_CNOC_CFG 117
#define SM8650_SLAVE_SERVICE_MNOC 118
#define SM8650_SLAVE_SERVICE_PCIE_ANOC 119
#define SM8650_SLAVE_SNOC_GEM_NOC_SF 120
#define SM8650_SLAVE_SPSS_CFG 121
#define SM8650_SLAVE_TCSR 122
#define SM8650_SLAVE_TCU 123
#define SM8650_SLAVE_TLMM 124
#define SM8650_SLAVE_TME_CFG 125
#define SM8650_SLAVE_UFS_MEM_CFG 126
#define SM8650_SLAVE_USB3_0 127
#define SM8650_SLAVE_VENUS_CFG 128
#define SM8650_SLAVE_VSENSE_CTRL_CFG 129
#endif

6
drivers/interconnect/qcom/smd-rpm.c
View File

@ -63,11 +63,9 @@ int qcom_icc_rpm_set_bus_rate(const struct rpm_clk_resource *clk, int ctx, u32 r
}
EXPORT_SYMBOL_GPL(qcom_icc_rpm_set_bus_rate);
static int qcom_icc_rpm_smd_remove(struct platform_device *pdev)
static void qcom_icc_rpm_smd_remove(struct platform_device *pdev)
{
icc_smd_rpm = NULL;
return 0;
}
static int qcom_icc_rpm_smd_probe(struct platform_device *pdev)
@ -87,7 +85,7 @@ static struct platform_driver qcom_interconnect_rpm_smd_driver = {
.name = "icc_smd_rpm",
},
.probe = qcom_icc_rpm_smd_probe,
.remove = qcom_icc_rpm_smd_remove,
.remove_new = qcom_icc_rpm_smd_remove,
};
module_platform_driver(qcom_interconnect_rpm_smd_driver);
MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");

2328
drivers/interconnect/qcom/x1e80100.c Normal file
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File diff suppressed because it is too large Load Diff

192
drivers/interconnect/qcom/x1e80100.h Normal file
View File

@ -0,0 +1,192 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* X1E80100 interconnect IDs
*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_X1E80100_H
#define __DRIVERS_INTERCONNECT_QCOM_X1E80100_H
#define X1E80100_MASTER_A1NOC_SNOC 0
#define X1E80100_MASTER_A2NOC_SNOC 1
#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC 2
#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP 3
#define X1E80100_MASTER_APPSS_PROC 4
#define X1E80100_MASTER_CAMNOC_HF 5
#define X1E80100_MASTER_CAMNOC_ICP 6
#define X1E80100_MASTER_CAMNOC_SF 7
#define X1E80100_MASTER_CDSP_PROC 8
#define X1E80100_MASTER_CNOC_CFG 9
#define X1E80100_MASTER_CNOC_MNOC_CFG 10
#define X1E80100_MASTER_COMPUTE_NOC 11
#define X1E80100_MASTER_CRYPTO 12
#define X1E80100_MASTER_GEM_NOC_CNOC 13
#define X1E80100_MASTER_GEM_NOC_PCIE_SNOC 14
#define X1E80100_MASTER_GFX3D 15
#define X1E80100_MASTER_GPU_TCU 16
#define X1E80100_MASTER_IPA 17
#define X1E80100_MASTER_LLCC 18
#define X1E80100_MASTER_LLCC_DISP 19
#define X1E80100_MASTER_LPASS_GEM_NOC 20
#define X1E80100_MASTER_LPASS_LPINOC 21
#define X1E80100_MASTER_LPASS_PROC 22
#define X1E80100_MASTER_LPIAON_NOC 23
#define X1E80100_MASTER_MDP 24
#define X1E80100_MASTER_MDP_DISP 25
#define X1E80100_MASTER_MNOC_HF_MEM_NOC 26
#define X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP 27
#define X1E80100_MASTER_MNOC_SF_MEM_NOC 28
#define X1E80100_MASTER_PCIE_0 29
#define X1E80100_MASTER_PCIE_1 30
#define X1E80100_MASTER_QDSS_ETR 31
#define X1E80100_MASTER_QDSS_ETR_1 32
#define X1E80100_MASTER_QSPI_0 33
#define X1E80100_MASTER_QUP_0 34
#define X1E80100_MASTER_QUP_1 35
#define X1E80100_MASTER_QUP_2 36
#define X1E80100_MASTER_QUP_CORE_0 37
#define X1E80100_MASTER_QUP_CORE_1 38
#define X1E80100_MASTER_SDCC_2 39
#define X1E80100_MASTER_SDCC_4 40
#define X1E80100_MASTER_SNOC_SF_MEM_NOC 41
#define X1E80100_MASTER_SP 42
#define X1E80100_MASTER_SYS_TCU 43
#define X1E80100_MASTER_UFS_MEM 44
#define X1E80100_MASTER_USB3_0 45
#define X1E80100_MASTER_VIDEO 46
#define X1E80100_MASTER_VIDEO_CV_PROC 47
#define X1E80100_MASTER_VIDEO_V_PROC 48
#define X1E80100_SLAVE_A1NOC_SNOC 49
#define X1E80100_SLAVE_A2NOC_SNOC 50
#define X1E80100_SLAVE_AHB2PHY_NORTH 51
#define X1E80100_SLAVE_AHB2PHY_SOUTH 52
#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC 53
#define X1E80100_SLAVE_AOSS 54
#define X1E80100_SLAVE_APPSS 55
#define X1E80100_SLAVE_BOOT_IMEM 56
#define X1E80100_SLAVE_CAMERA_CFG 57
#define X1E80100_SLAVE_CDSP_MEM_NOC 58
#define X1E80100_SLAVE_CLK_CTL 59
#define X1E80100_SLAVE_CNOC_CFG 60
#define X1E80100_SLAVE_CNOC_MNOC_CFG 61
#define X1E80100_SLAVE_CRYPTO_0_CFG 62
#define X1E80100_SLAVE_DISPLAY_CFG 63
#define X1E80100_SLAVE_EBI1 64
#define X1E80100_SLAVE_EBI1_DISP 65
#define X1E80100_SLAVE_GEM_NOC_CNOC 66
#define X1E80100_SLAVE_GFX3D_CFG 67
#define X1E80100_SLAVE_IMEM 68
#define X1E80100_SLAVE_IMEM_CFG 69
#define X1E80100_SLAVE_IPC_ROUTER_CFG 70
#define X1E80100_SLAVE_LLCC 71
#define X1E80100_SLAVE_LLCC_DISP 72
#define X1E80100_SLAVE_LPASS_GEM_NOC 73
#define X1E80100_SLAVE_LPASS_QTB_CFG 74
#define X1E80100_SLAVE_LPIAON_NOC_LPASS_AG_NOC 75
#define X1E80100_SLAVE_LPICX_NOC_LPIAON_NOC 76
#define X1E80100_SLAVE_MEM_NOC_PCIE_SNOC 77
#define X1E80100_SLAVE_MNOC_HF_MEM_NOC 78
#define X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP 79
#define X1E80100_SLAVE_MNOC_SF_MEM_NOC 80
#define X1E80100_SLAVE_NSP_QTB_CFG 81
#define X1E80100_SLAVE_PCIE_0 82
#define X1E80100_SLAVE_PCIE_0_CFG 83
#define X1E80100_SLAVE_PCIE_1 84
#define X1E80100_SLAVE_PCIE_1_CFG 85
#define X1E80100_SLAVE_PDM 86
#define X1E80100_SLAVE_PRNG 87
#define X1E80100_SLAVE_QDSS_CFG 88
#define X1E80100_SLAVE_QDSS_STM 89
#define X1E80100_SLAVE_QSPI_0 90
#define X1E80100_SLAVE_QUP_1 91
#define X1E80100_SLAVE_QUP_2 92
#define X1E80100_SLAVE_QUP_CORE_0 93
#define X1E80100_SLAVE_QUP_CORE_1 94
#define X1E80100_SLAVE_QUP_CORE_2 95
#define X1E80100_SLAVE_SDCC_2 96
#define X1E80100_SLAVE_SDCC_4 97
#define X1E80100_SLAVE_SERVICE_MNOC 98
#define X1E80100_SLAVE_SNOC_GEM_NOC_SF 99
#define X1E80100_SLAVE_TCSR 100
#define X1E80100_SLAVE_TCU 101
#define X1E80100_SLAVE_TLMM 102
#define X1E80100_SLAVE_TME_CFG 103
#define X1E80100_SLAVE_UFS_MEM_CFG 104
#define X1E80100_SLAVE_USB3_0 105
#define X1E80100_SLAVE_VENUS_CFG 106
#define X1E80100_MASTER_DDR_PERF_MODE 107
#define X1E80100_MASTER_QUP_CORE_2 108
#define X1E80100_MASTER_PCIE_TCU 109
#define X1E80100_MASTER_GIC2 110
#define X1E80100_MASTER_AV1_ENC 111
#define X1E80100_MASTER_EVA 112
#define X1E80100_MASTER_PCIE_NORTH 113
#define X1E80100_MASTER_PCIE_SOUTH 114
#define X1E80100_MASTER_PCIE_3 115
#define X1E80100_MASTER_PCIE_4 116
#define X1E80100_MASTER_PCIE_5 117
#define X1E80100_MASTER_PCIE_2 118
#define X1E80100_MASTER_PCIE_6A 119
#define X1E80100_MASTER_PCIE_6B 120
#define X1E80100_MASTER_GIC1 121
#define X1E80100_MASTER_USB_NOC_SNOC 122
#define X1E80100_MASTER_AGGRE_USB_NORTH 123
#define X1E80100_MASTER_AGGRE_USB_SOUTH 124
#define X1E80100_MASTER_USB2 125
#define X1E80100_MASTER_USB3_MP 126
#define X1E80100_MASTER_USB3_1 127
#define X1E80100_MASTER_USB3_2 128
#define X1E80100_MASTER_USB4_0 129
#define X1E80100_MASTER_USB4_1 130
#define X1E80100_MASTER_USB4_2 131
#define X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE 132
#define X1E80100_MASTER_LLCC_PCIE 133
#define X1E80100_MASTER_PCIE_NORTH_PCIE 134
#define X1E80100_MASTER_PCIE_SOUTH_PCIE 135
#define X1E80100_MASTER_PCIE_3_PCIE 136
#define X1E80100_MASTER_PCIE_4_PCIE 137
#define X1E80100_MASTER_PCIE_5_PCIE 138
#define X1E80100_MASTER_PCIE_0_PCIE 139
#define X1E80100_MASTER_PCIE_1_PCIE 140
#define X1E80100_MASTER_PCIE_2_PCIE 141
#define X1E80100_MASTER_PCIE_6A_PCIE 142
#define X1E80100_MASTER_PCIE_6B_PCIE 143
#define X1E80100_SLAVE_AHB2PHY_2 144
#define X1E80100_SLAVE_AV1_ENC_CFG 145
#define X1E80100_SLAVE_PCIE_2_CFG 146
#define X1E80100_SLAVE_PCIE_3_CFG 147
#define X1E80100_SLAVE_PCIE_4_CFG 148
#define X1E80100_SLAVE_PCIE_5_CFG 149
#define X1E80100_SLAVE_PCIE_6A_CFG 150
#define X1E80100_SLAVE_PCIE_6B_CFG 151
#define X1E80100_SLAVE_PCIE_RSC_CFG 152
#define X1E80100_SLAVE_QUP_0 153
#define X1E80100_SLAVE_SMMUV3_CFG 154
#define X1E80100_SLAVE_USB2 155
#define X1E80100_SLAVE_USB3_1 156
#define X1E80100_SLAVE_USB3_2 157
#define X1E80100_SLAVE_USB3_MP 158
#define X1E80100_SLAVE_USB4_0 159
#define X1E80100_SLAVE_USB4_1 160
#define X1E80100_SLAVE_USB4_2 161
#define X1E80100_SLAVE_PCIE_2 162
#define X1E80100_SLAVE_PCIE_3 163
#define X1E80100_SLAVE_PCIE_4 164
#define X1E80100_SLAVE_PCIE_5 165
#define X1E80100_SLAVE_PCIE_6A 166
#define X1E80100_SLAVE_PCIE_6B 167
#define X1E80100_SLAVE_DDR_PERF_MODE 168
#define X1E80100_SLAVE_PCIE_NORTH 169
#define X1E80100_SLAVE_PCIE_SOUTH 170
#define X1E80100_SLAVE_USB_NOC_SNOC 171
#define X1E80100_SLAVE_AGGRE_USB_NORTH 172
#define X1E80100_SLAVE_AGGRE_USB_SOUTH 173
#define X1E80100_SLAVE_LLCC_PCIE 174
#define X1E80100_SLAVE_EBI1_PCIE 175
#define X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE 176
#define X1E80100_SLAVE_PCIE_NORTH_PCIE 177
#define X1E80100_SLAVE_PCIE_SOUTH_PCIE 178
#endif

6
drivers/interconnect/samsung/exynos.c
View File

@ -93,14 +93,12 @@ static struct icc_node *exynos_generic_icc_xlate(struct of_phandle_args *spec,
return priv->node;
}
static int exynos_generic_icc_remove(struct platform_device *pdev)
static void exynos_generic_icc_remove(struct platform_device *pdev)
{
struct exynos_icc_priv *priv = platform_get_drvdata(pdev);
icc_provider_deregister(&priv->provider);
icc_nodes_remove(&priv->provider);
return 0;
}
static int exynos_generic_icc_probe(struct platform_device *pdev)
@ -182,7 +180,7 @@ static struct platform_driver exynos_generic_icc_driver = {
.sync_state = icc_sync_state,
},
.probe = exynos_generic_icc_probe,
.remove = exynos_generic_icc_remove,
.remove_new = exynos_generic_icc_remove,
};
module_platform_driver(exynos_generic_icc_driver);

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include/dt-bindings/interconnect/qcom,sm6115.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H
/* BIMC */
#define MASTER_AMPSS_M0 0
#define MASTER_SNOC_BIMC_RT 1
#define MASTER_SNOC_BIMC_NRT 2
#define SNOC_BIMC_MAS 3
#define MASTER_GRAPHICS_3D 4
#define MASTER_TCU_0 5
#define SLAVE_EBI_CH0 6
#define BIMC_SNOC_SLV 7
/* CNOC */
#define SNOC_CNOC_MAS 0
#define MASTER_QDSS_DAP 1
#define SLAVE_AHB2PHY_USB 2
#define SLAVE_APSS_THROTTLE_CFG 3
#define SLAVE_BIMC_CFG 4
#define SLAVE_BOOT_ROM 5
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6
#define SLAVE_CAMERA_RT_THROTTLE_CFG 7
#define SLAVE_CAMERA_CFG 8
#define SLAVE_CLK_CTL 9
#define SLAVE_RBCPR_CX_CFG 10
#define SLAVE_RBCPR_MX_CFG 11
#define SLAVE_CRYPTO_0_CFG 12
#define SLAVE_DCC_CFG 13
#define SLAVE_DDR_PHY_CFG 14
#define SLAVE_DDR_SS_CFG 15
#define SLAVE_DISPLAY_CFG 16
#define SLAVE_DISPLAY_THROTTLE_CFG 17
#define SLAVE_GPU_CFG 18
#define SLAVE_GPU_THROTTLE_CFG 19
#define SLAVE_HWKM_CORE 20
#define SLAVE_IMEM_CFG 21
#define SLAVE_IPA_CFG 22
#define SLAVE_LPASS 23
#define SLAVE_MAPSS 24
#define SLAVE_MDSP_MPU_CFG 25
#define SLAVE_MESSAGE_RAM 26
#define SLAVE_CNOC_MSS 27
#define SLAVE_PDM 28
#define SLAVE_PIMEM_CFG 29
#define SLAVE_PKA_CORE 30
#define SLAVE_PMIC_ARB 31
#define SLAVE_QDSS_CFG 32
#define SLAVE_QM_CFG 33
#define SLAVE_QM_MPU_CFG 34
#define SLAVE_QPIC 35
#define SLAVE_QUP_0 36
#define SLAVE_RPM 37
#define SLAVE_SDCC_1 38
#define SLAVE_SDCC_2 39
#define SLAVE_SECURITY 40
#define SLAVE_SNOC_CFG 41
#define SLAVE_TCSR 42
#define SLAVE_TLMM 43
#define SLAVE_USB3 44
#define SLAVE_VENUS_CFG 45
#define SLAVE_VENUS_THROTTLE_CFG 46
#define SLAVE_VSENSE_CTRL_CFG 47
#define SLAVE_SERVICE_CNOC 48
/* SNOC */
#define MASTER_CRYPTO_CORE0 0
#define MASTER_SNOC_CFG 1
#define MASTER_TIC 2
#define MASTER_ANOC_SNOC 3
#define BIMC_SNOC_MAS 4
#define MASTER_PIMEM 5
#define MASTER_QDSS_BAM 6
#define MASTER_QPIC 7
#define MASTER_QUP_0 8
#define MASTER_IPA 9
#define MASTER_QDSS_ETR 10
#define MASTER_SDCC_1 11
#define MASTER_SDCC_2 12
#define MASTER_USB3 13
#define SLAVE_APPSS 14
#define SNOC_CNOC_SLV 15
#define SLAVE_OCIMEM 16
#define SLAVE_PIMEM 17
#define SNOC_BIMC_SLV 18
#define SLAVE_SERVICE_SNOC 19
#define SLAVE_QDSS_STM 20
#define SLAVE_TCU 21
#define SLAVE_ANOC_SNOC 22
/* CLK Virtual */
#define MASTER_QUP_CORE_0 0
#define SLAVE_QUP_CORE_0 1
/* MMRT Virtual */
#define MASTER_CAMNOC_HF 0
#define MASTER_MDP_PORT0 1
#define SLAVE_SNOC_BIMC_RT 2
/* MMNRT Virtual */
#define MASTER_CAMNOC_SF 0
#define MASTER_VIDEO_P0 1
#define MASTER_VIDEO_PROC 2
#define SLAVE_SNOC_BIMC_NRT 3
#endif

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include/dt-bindings/interconnect/qcom,sm8650-rpmh.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8650_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8650_H
#define MASTER_QSPI_0 0
#define MASTER_QUP_1 1
#define MASTER_QUP_3 2
#define MASTER_SDCC_4 3
#define MASTER_UFS_MEM 4
#define MASTER_USB3_0 5
#define SLAVE_A1NOC_SNOC 6
#define MASTER_QDSS_BAM 0
#define MASTER_QUP_2 1
#define MASTER_CRYPTO 2
#define MASTER_IPA 3
#define MASTER_SP 4
#define MASTER_QDSS_ETR 5
#define MASTER_QDSS_ETR_1 6
#define MASTER_SDCC_2 7
#define SLAVE_A2NOC_SNOC 8
#define MASTER_QUP_CORE_0 0
#define MASTER_QUP_CORE_1 1
#define MASTER_QUP_CORE_2 2
#define SLAVE_QUP_CORE_0 3
#define SLAVE_QUP_CORE_1 4
#define SLAVE_QUP_CORE_2 5
#define MASTER_CNOC_CFG 0
#define SLAVE_AHB2PHY_SOUTH 1
#define SLAVE_AHB2PHY_NORTH 2
#define SLAVE_CAMERA_CFG 3
#define SLAVE_CLK_CTL 4
#define SLAVE_RBCPR_CX_CFG 5
#define SLAVE_CPR_HMX 6
#define SLAVE_RBCPR_MMCX_CFG 7
#define SLAVE_RBCPR_MXA_CFG 8
#define SLAVE_RBCPR_MXC_CFG 9
#define SLAVE_CPR_NSPCX 10
#define SLAVE_CRYPTO_0_CFG 11
#define SLAVE_CX_RDPM 12
#define SLAVE_DISPLAY_CFG 13
#define SLAVE_GFX3D_CFG 14
#define SLAVE_I2C 15
#define SLAVE_I3C_IBI0_CFG 16
#define SLAVE_I3C_IBI1_CFG 17
#define SLAVE_IMEM_CFG 18
#define SLAVE_CNOC_MSS 19
#define SLAVE_MX_2_RDPM 20
#define SLAVE_MX_RDPM 21
#define SLAVE_PCIE_0_CFG 22
#define SLAVE_PCIE_1_CFG 23
#define SLAVE_PCIE_RSCC 24
#define SLAVE_PDM 25
#define SLAVE_PRNG 26
#define SLAVE_QDSS_CFG 27
#define SLAVE_QSPI_0 28
#define SLAVE_QUP_3 29
#define SLAVE_QUP_1 30
#define SLAVE_QUP_2 31
#define SLAVE_SDCC_2 32
#define SLAVE_SDCC_4 33
#define SLAVE_SPSS_CFG 34
#define SLAVE_TCSR 35
#define SLAVE_TLMM 36
#define SLAVE_UFS_MEM_CFG 37
#define SLAVE_USB3_0 38
#define SLAVE_VENUS_CFG 39
#define SLAVE_VSENSE_CTRL_CFG 40
#define SLAVE_CNOC_MNOC_CFG 41
#define SLAVE_NSP_QTB_CFG 42
#define SLAVE_PCIE_ANOC_CFG 43
#define SLAVE_SERVICE_CNOC_CFG 44
#define SLAVE_QDSS_STM 45
#define SLAVE_TCU 46
#define MASTER_GEM_NOC_CNOC 0
#define MASTER_GEM_NOC_PCIE_SNOC 1
#define SLAVE_AOSS 2
#define SLAVE_IPA_CFG 3
#define SLAVE_IPC_ROUTER_CFG 4
#define SLAVE_TME_CFG 5
#define SLAVE_APPSS 6
#define SLAVE_CNOC_CFG 7
#define SLAVE_DDRSS_CFG 8
#define SLAVE_IMEM 9
#define SLAVE_SERVICE_CNOC 10
#define SLAVE_PCIE_0 11
#define SLAVE_PCIE_1 12
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_UBWC_P_TCU 2
#define MASTER_APPSS_PROC 3
#define MASTER_GFX3D 4
#define MASTER_LPASS_GEM_NOC 5
#define MASTER_MSS_PROC 6
#define MASTER_MNOC_HF_MEM_NOC 7
#define MASTER_MNOC_SF_MEM_NOC 8
#define MASTER_COMPUTE_NOC 9
#define MASTER_ANOC_PCIE_GEM_NOC 10
#define MASTER_SNOC_SF_MEM_NOC 11
#define MASTER_UBWC_P 12
#define MASTER_GIC 13
#define SLAVE_GEM_NOC_CNOC 14
#define SLAVE_LLCC 15
#define SLAVE_MEM_NOC_PCIE_SNOC 16
#define MASTER_LPIAON_NOC 0
#define SLAVE_LPASS_GEM_NOC 1
#define MASTER_LPASS_LPINOC 0
#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1
#define MASTER_LPASS_PROC 0
#define SLAVE_LPICX_NOC_LPIAON_NOC 1
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
#define MASTER_CAMNOC_HF 0
#define MASTER_CAMNOC_ICP 1
#define MASTER_CAMNOC_SF 2
#define MASTER_MDP 3
#define MASTER_CDSP_HCP 4
#define MASTER_VIDEO 5
#define MASTER_VIDEO_CV_PROC 6
#define MASTER_VIDEO_PROC 7
#define MASTER_VIDEO_V_PROC 8
#define MASTER_CNOC_MNOC_CFG 9
#define SLAVE_MNOC_HF_MEM_NOC 10
#define SLAVE_MNOC_SF_MEM_NOC 11
#define SLAVE_SERVICE_MNOC 12
#define MASTER_CDSP_PROC 0
#define SLAVE_CDSP_MEM_NOC 1
#define MASTER_PCIE_ANOC_CFG 0
#define MASTER_PCIE_0 1
#define MASTER_PCIE_1 2
#define SLAVE_ANOC_PCIE_GEM_NOC 3
#define SLAVE_SERVICE_PCIE_ANOC 4
#define MASTER_A1NOC_SNOC 0
#define MASTER_A2NOC_SNOC 1
#define SLAVE_SNOC_GEM_NOC_SF 2
#endif

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_X1E80100_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_X1E80100_H
#define MASTER_QSPI_0 0
#define MASTER_QUP_1 1
#define MASTER_SDCC_4 2
#define MASTER_UFS_MEM 3
#define SLAVE_A1NOC_SNOC 4
#define MASTER_QUP_0 0
#define MASTER_QUP_2 1
#define MASTER_CRYPTO 2
#define MASTER_SP 3
#define MASTER_QDSS_ETR 4
#define MASTER_QDSS_ETR_1 5
#define MASTER_SDCC_2 6
#define SLAVE_A2NOC_SNOC 7
#define MASTER_DDR_PERF_MODE 0
#define MASTER_QUP_CORE_0 1
#define MASTER_QUP_CORE_1 2
#define MASTER_QUP_CORE_2 3
#define SLAVE_DDR_PERF_MODE 4
#define SLAVE_QUP_CORE_0 5
#define SLAVE_QUP_CORE_1 6
#define SLAVE_QUP_CORE_2 7
#define MASTER_CNOC_CFG 0
#define SLAVE_AHB2PHY_SOUTH 1
#define SLAVE_AHB2PHY_NORTH 2
#define SLAVE_AHB2PHY_2 3
#define SLAVE_AV1_ENC_CFG 4
#define SLAVE_CAMERA_CFG 5
#define SLAVE_CLK_CTL 6
#define SLAVE_CRYPTO_0_CFG 7
#define SLAVE_DISPLAY_CFG 8
#define SLAVE_GFX3D_CFG 9
#define SLAVE_IMEM_CFG 10
#define SLAVE_IPC_ROUTER_CFG 11
#define SLAVE_PCIE_0_CFG 12
#define SLAVE_PCIE_1_CFG 13
#define SLAVE_PCIE_2_CFG 14
#define SLAVE_PCIE_3_CFG 15
#define SLAVE_PCIE_4_CFG 16
#define SLAVE_PCIE_5_CFG 17
#define SLAVE_PCIE_6A_CFG 18
#define SLAVE_PCIE_6B_CFG 19
#define SLAVE_PCIE_RSC_CFG 20
#define SLAVE_PDM 21
#define SLAVE_PRNG 22
#define SLAVE_QDSS_CFG 23
#define SLAVE_QSPI_0 24
#define SLAVE_QUP_0 25
#define SLAVE_QUP_1 26
#define SLAVE_QUP_2 27
#define SLAVE_SDCC_2 28
#define SLAVE_SDCC_4 29
#define SLAVE_SMMUV3_CFG 30
#define SLAVE_TCSR 31
#define SLAVE_TLMM 32
#define SLAVE_UFS_MEM_CFG 33
#define SLAVE_USB2 34
#define SLAVE_USB3_0 35
#define SLAVE_USB3_1 36
#define SLAVE_USB3_2 37
#define SLAVE_USB3_MP 38
#define SLAVE_USB4_0 39
#define SLAVE_USB4_1 40
#define SLAVE_USB4_2 41
#define SLAVE_VENUS_CFG 42
#define SLAVE_LPASS_QTB_CFG 43
#define SLAVE_CNOC_MNOC_CFG 44
#define SLAVE_NSP_QTB_CFG 45
#define SLAVE_QDSS_STM 46
#define SLAVE_TCU 47
#define MASTER_GEM_NOC_CNOC 0
#define MASTER_GEM_NOC_PCIE_SNOC 1
#define SLAVE_AOSS 2
#define SLAVE_TME_CFG 3
#define SLAVE_APPSS 4
#define SLAVE_CNOC_CFG 5
#define SLAVE_BOOT_IMEM 6
#define SLAVE_IMEM 7
#define SLAVE_PCIE_0 8
#define SLAVE_PCIE_1 9
#define SLAVE_PCIE_2 10
#define SLAVE_PCIE_3 11
#define SLAVE_PCIE_4 12
#define SLAVE_PCIE_5 13
#define SLAVE_PCIE_6A 14
#define SLAVE_PCIE_6B 15
#define MASTER_GPU_TCU 0
#define MASTER_PCIE_TCU 1
#define MASTER_SYS_TCU 2
#define MASTER_APPSS_PROC 3
#define MASTER_GFX3D 4
#define MASTER_LPASS_GEM_NOC 5
#define MASTER_MNOC_HF_MEM_NOC 6
#define MASTER_MNOC_SF_MEM_NOC 7
#define MASTER_COMPUTE_NOC 8
#define MASTER_ANOC_PCIE_GEM_NOC 9
#define MASTER_SNOC_SF_MEM_NOC 10
#define MASTER_GIC2 11
#define SLAVE_GEM_NOC_CNOC 12
#define SLAVE_LLCC 13
#define SLAVE_MEM_NOC_PCIE_SNOC 14
#define MASTER_MNOC_HF_MEM_NOC_DISP 15
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16
#define SLAVE_LLCC_DISP 17
#define MASTER_ANOC_PCIE_GEM_NOC_PCIE 18
#define SLAVE_LLCC_PCIE 19
#define MASTER_LPIAON_NOC 0
#define SLAVE_LPASS_GEM_NOC 1
#define MASTER_LPASS_LPINOC 0
#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1
#define MASTER_LPASS_PROC 0
#define SLAVE_LPICX_NOC_LPIAON_NOC 1
#define MASTER_LLCC 0
#define SLAVE_EBI1 1
#define MASTER_LLCC_DISP 2
#define SLAVE_EBI1_DISP 3
#define MASTER_LLCC_PCIE 4
#define SLAVE_EBI1_PCIE 5
#define MASTER_AV1_ENC 0
#define MASTER_CAMNOC_HF 1
#define MASTER_CAMNOC_ICP 2
#define MASTER_CAMNOC_SF 3
#define MASTER_EVA 4
#define MASTER_MDP 5
#define MASTER_VIDEO 6
#define MASTER_VIDEO_CV_PROC 7
#define MASTER_VIDEO_V_PROC 8
#define MASTER_CNOC_MNOC_CFG 9
#define SLAVE_MNOC_HF_MEM_NOC 10
#define SLAVE_MNOC_SF_MEM_NOC 11
#define SLAVE_SERVICE_MNOC 12
#define MASTER_MDP_DISP 13
#define SLAVE_MNOC_HF_MEM_NOC_DISP 14
#define MASTER_CDSP_PROC 0
#define SLAVE_CDSP_MEM_NOC 1
#define MASTER_PCIE_NORTH 0
#define MASTER_PCIE_SOUTH 1
#define SLAVE_ANOC_PCIE_GEM_NOC 2
#define MASTER_PCIE_NORTH_PCIE 3
#define MASTER_PCIE_SOUTH_PCIE 4
#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE 5
#define MASTER_PCIE_3 0
#define MASTER_PCIE_4 1
#define MASTER_PCIE_5 2
#define SLAVE_PCIE_NORTH 3
#define MASTER_PCIE_3_PCIE 4
#define MASTER_PCIE_4_PCIE 5
#define MASTER_PCIE_5_PCIE 6
#define SLAVE_PCIE_NORTH_PCIE 7
#define MASTER_PCIE_0 0
#define MASTER_PCIE_1 1
#define MASTER_PCIE_2 2
#define MASTER_PCIE_6A 3
#define MASTER_PCIE_6B 4
#define SLAVE_PCIE_SOUTH 5
#define MASTER_PCIE_0_PCIE 6
#define MASTER_PCIE_1_PCIE 7
#define MASTER_PCIE_2_PCIE 8
#define MASTER_PCIE_6A_PCIE 9
#define MASTER_PCIE_6B_PCIE 10
#define SLAVE_PCIE_SOUTH_PCIE 11
#define MASTER_A1NOC_SNOC 0
#define MASTER_A2NOC_SNOC 1
#define MASTER_GIC1 2
#define MASTER_USB_NOC_SNOC 3
#define SLAVE_SNOC_GEM_NOC_SF 4
#define MASTER_AGGRE_USB_NORTH 0
#define MASTER_AGGRE_USB_SOUTH 1
#define SLAVE_USB_NOC_SNOC 2
#define MASTER_USB2 0
#define MASTER_USB3_MP 1
#define SLAVE_AGGRE_USB_NORTH 2
#define MASTER_USB3_0 0
#define MASTER_USB3_1 1
#define MASTER_USB3_2 2
#define MASTER_USB4_0 3
#define MASTER_USB4_1 4
#define MASTER_USB4_2 5
#define SLAVE_AGGRE_USB_SOUTH 6
#endif