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x86, cacheinfo: Unify AMD L3 cache index disable checking

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All F10h CPUs starting with model 8 resp. 9, stepping 1, support L3
cache index disable. Concentrate the family, model, stepping checking at
one place and enable the feature implicitly on upcoming Fam10h models.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <1271945222-5283-2-git-send-email-bp@amd64.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Borislav Petkov 2010-04-22 16:06:58 +02:00 committed by H. Peter Anvin
parent 6dad2a2964
commit b1ab1b4d9a
1 changed files with 11 additions and 8 deletions
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19
arch/x86/kernel/cpu/intel_cacheinfo.c
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@ -328,17 +328,21 @@ static unsigned int __cpuinit amd_calc_l3_indices(void)
static void __cpuinit
amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
{
if (boot_cpu_data.x86 != 0x10)
return;
if (index < 3)
return;
if (boot_cpu_data.x86 == 0x11)
/* see errata #382 and #388 */
if (boot_cpu_data.x86_model < 0x8)
return;
/* see errata #382 and #388 */
if ((boot_cpu_data.x86 == 0x10) &&
((boot_cpu_data.x86_model < 0x8) ||
(boot_cpu_data.x86_mask < 0x1)))
return;
if ((boot_cpu_data.x86_model == 0x8 ||
boot_cpu_data.x86_model == 0x9)
&&
boot_cpu_data.x86_mask < 0x1)
return;
this_leaf->can_disable = true;
this_leaf->l3_indices = amd_calc_l3_indices();
@ -443,8 +447,7 @@ __cpuinit cpuid4_cache_lookup_regs(int index,
if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
amd_cpuid4(index, &eax, &ebx, &ecx);
if (boot_cpu_data.x86 >= 0x10)
amd_check_l3_disable(index, this_leaf);
amd_check_l3_disable(index, this_leaf);
} else {
cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
}