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clk: divider: fix rate calculation for fractional rates
clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -24,7 +24,7 @@
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is adjustable. clk->rate = parent->rate / divisor
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* rate - rate is adjustable. clk->rate = DIV_ROUND_UP(parent->rate / divisor)
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* parent - fixed parent. No clk_set_parent support
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*/
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@ -115,7 +115,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
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return parent_rate;
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}
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return parent_rate / div;
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return DIV_ROUND_UP(parent_rate, div);
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}
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/*
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@ -185,7 +185,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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}
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parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
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MULT_ROUND_UP(rate, i));
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now = parent_rate / i;
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now = DIV_ROUND_UP(parent_rate, i);
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if (now <= rate && now > best) {
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bestdiv = i;
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best = now;
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@ -207,7 +207,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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int div;
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div = clk_divider_bestdiv(hw, rate, prate);
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return *prate / div;
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return DIV_ROUND_UP(*prate, div);
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}
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static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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@ -218,7 +218,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long flags = 0;
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u32 val;
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div = parent_rate / rate;
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div = DIV_ROUND_UP(parent_rate, rate);
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value = _get_val(divider, div);
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if (value > div_mask(divider))
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