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[NIU]: Support for Marvell PHY
From: Mirko Lindner <mlindner@marvell.com> This patch makes necessary changes in the Neptune driver to support the new Marvell PHY. It also adds support for the LED blinking on Neptune cards with Marvell PHY. All registers are using defines in the niu.h header file as is already done for the BCM8704 registers. [ Coding style, etc. cleanups -DaveM ] Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Mirko Lindner
David S. Miller
parent
fd0b45dfd1
commit
b0de8e402d
@ -801,22 +801,90 @@ static int bcm8704_init_user_dev3(struct niu *np)
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return 0;
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}
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static int xcvr_init_10g(struct niu *np)
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static int mrvl88x2011_act_led(struct niu *np, int val)
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{
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int err;
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err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
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MRVL88X2011_LED_8_TO_11_CTL);
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if (err < 0)
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return err;
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err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
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err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
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return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
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MRVL88X2011_LED_8_TO_11_CTL, err);
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}
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static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
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{
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int err;
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err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
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MRVL88X2011_LED_BLINK_CTL);
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if (err >= 0) {
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err &= ~MRVL88X2011_LED_BLKRATE_MASK;
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err |= (rate << 4);
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err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
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MRVL88X2011_LED_BLINK_CTL, err);
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}
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return err;
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}
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static int xcvr_init_10g_mrvl88x2011(struct niu *np)
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{
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int err;
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/* Set LED functions */
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err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
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if (err)
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return err;
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/* led activity */
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err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
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if (err)
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return err;
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err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
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MRVL88X2011_GENERAL_CTL);
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if (err < 0)
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return err;
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err |= MRVL88X2011_ENA_XFPREFCLK;
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err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
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MRVL88X2011_GENERAL_CTL, err);
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if (err < 0)
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return err;
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err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
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MRVL88X2011_PMA_PMD_CTL_1);
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if (err < 0)
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return err;
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if (np->link_config.loopback_mode == LOOPBACK_MAC)
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err |= MRVL88X2011_LOOPBACK;
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else
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err &= ~MRVL88X2011_LOOPBACK;
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err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
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MRVL88X2011_PMA_PMD_CTL_1, err);
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if (err < 0)
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return err;
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/* Enable PMD */
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return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
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MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
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}
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static int xcvr_init_10g_bcm8704(struct niu *np)
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{
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struct niu_link_config *lp = &np->link_config;
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u16 analog_stat0, tx_alarm_status;
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int err;
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u64 val;
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val = nr64_mac(XMAC_CONFIG);
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val &= ~XMAC_CONFIG_LED_POLARITY;
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val |= XMAC_CONFIG_FORCE_LED_ON;
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nw64_mac(XMAC_CONFIG, val);
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/* XXX shared resource, lock parent XXX */
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val = nr64(MIF_CONFIG);
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val |= MIF_CONFIG_INDIRECT_MODE;
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nw64(MIF_CONFIG, val);
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err = bcm8704_reset(np);
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if (err)
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@ -896,6 +964,38 @@ static int xcvr_init_10g(struct niu *np)
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return 0;
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}
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static int xcvr_init_10g(struct niu *np)
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{
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int phy_id, err;
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u64 val;
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val = nr64_mac(XMAC_CONFIG);
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val &= ~XMAC_CONFIG_LED_POLARITY;
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val |= XMAC_CONFIG_FORCE_LED_ON;
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nw64_mac(XMAC_CONFIG, val);
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/* XXX shared resource, lock parent XXX */
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val = nr64(MIF_CONFIG);
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val |= MIF_CONFIG_INDIRECT_MODE;
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nw64(MIF_CONFIG, val);
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phy_id = phy_decode(np->parent->port_phy, np->port);
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phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
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/* handle different phy types */
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switch (phy_id & NIU_PHY_ID_MASK) {
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case NIU_PHY_ID_MRVL88X2011:
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err = xcvr_init_10g_mrvl88x2011(np);
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break;
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default: /* bcom 8704 */
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err = xcvr_init_10g_bcm8704(np);
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break;
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}
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return 0;
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}
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static int mii_reset(struct niu *np)
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{
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int limit, err;
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@ -1082,19 +1182,68 @@ static int niu_link_status_common(struct niu *np, int link_up)
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return 0;
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}
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static int link_status_10g(struct niu *np, int *link_up_p)
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static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
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{
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unsigned long flags;
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int err, link_up;
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int err, link_up, pma_status, pcs_status;
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link_up = 0;
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spin_lock_irqsave(&np->lock, flags);
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err = -EINVAL;
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if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
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err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
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MRVL88X2011_10G_PMD_STATUS_2);
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if (err < 0)
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goto out;
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/* Check PMA/PMD Register: 1.0001.2 == 1 */
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err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
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MRVL88X2011_PMA_PMD_STATUS_1);
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if (err < 0)
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goto out;
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pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
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/* Check PMC Register : 3.0001.2 == 1: read twice */
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err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
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MRVL88X2011_PMA_PMD_STATUS_1);
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if (err < 0)
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goto out;
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err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
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MRVL88X2011_PMA_PMD_STATUS_1);
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if (err < 0)
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goto out;
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pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
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/* Check XGXS Register : 4.0018.[0-3,12] */
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err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
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MRVL88X2011_10G_XGXS_LANE_STAT);
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if (err < 0)
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goto out;
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if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
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PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
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PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
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0x800))
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link_up = (pma_status && pcs_status) ? 1 : 0;
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np->link_config.active_speed = SPEED_10000;
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np->link_config.active_duplex = DUPLEX_FULL;
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err = 0;
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out:
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mrvl88x2011_act_led(np, (link_up ?
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MRVL88X2011_LED_CTL_PCS_ACT :
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MRVL88X2011_LED_CTL_OFF));
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*link_up_p = link_up;
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return err;
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}
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static int link_status_10g_bcom(struct niu *np, int *link_up_p)
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{
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int err, link_up;
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link_up = 0;
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err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
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BCM8704_PMD_RCV_SIGDET);
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if (err < 0)
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@ -1134,9 +1283,37 @@ static int link_status_10g(struct niu *np, int *link_up_p)
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err = 0;
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out:
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*link_up_p = link_up;
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return err;
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}
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static int link_status_10g(struct niu *np, int *link_up_p)
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{
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unsigned long flags;
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int err = -EINVAL;
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spin_lock_irqsave(&np->lock, flags);
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if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
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int phy_id;
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phy_id = phy_decode(np->parent->port_phy, np->port);
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phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
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/* handle different phy types */
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switch (phy_id & NIU_PHY_ID_MASK) {
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case NIU_PHY_ID_MRVL88X2011:
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err = link_status_10g_mrvl(np, link_up_p);
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break;
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default: /* bcom 8704 */
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err = link_status_10g_bcom(np, link_up_p);
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break;
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}
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}
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spin_unlock_irqrestore(&np->lock, flags);
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*link_up_p = link_up;
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return err;
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}
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@ -6297,7 +6474,8 @@ static int __devinit phy_record(struct niu_parent *parent,
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if (dev_id_1 < 0 || dev_id_2 < 0)
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return 0;
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if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
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if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704)
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if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
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((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011))
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return 0;
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} else {
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if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
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@ -2538,6 +2538,39 @@ struct fcram_hash_ipv6 {
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#define NIU_PHY_ID_MASK 0xfffff0f0
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#define NIU_PHY_ID_BCM8704 0x00206030
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#define NIU_PHY_ID_BCM5464R 0x002060b0
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#define NIU_PHY_ID_MRVL88X2011 0x01410020
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/* MRVL88X2011 register addresses */
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#define MRVL88X2011_USER_DEV1_ADDR 1
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#define MRVL88X2011_USER_DEV2_ADDR 2
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#define MRVL88X2011_USER_DEV3_ADDR 3
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#define MRVL88X2011_USER_DEV4_ADDR 4
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#define MRVL88X2011_PMA_PMD_CTL_1 0x0000
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#define MRVL88X2011_PMA_PMD_STATUS_1 0x0001
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#define MRVL88X2011_10G_PMD_STATUS_2 0x0008
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#define MRVL88X2011_10G_PMD_TX_DIS 0x0009
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#define MRVL88X2011_10G_XGXS_LANE_STAT 0x0018
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#define MRVL88X2011_GENERAL_CTL 0x8300
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#define MRVL88X2011_LED_BLINK_CTL 0x8303
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#define MRVL88X2011_LED_8_TO_11_CTL 0x8306
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/* MRVL88X2011 register control */
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#define MRVL88X2011_ENA_XFPREFCLK 0x0001
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#define MRVL88X2011_ENA_PMDTX 0x0000
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#define MRVL88X2011_LOOPBACK 0x1
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#define MRVL88X2011_LED_ACT 0x1
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#define MRVL88X2011_LNK_STATUS_OK 0x4
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#define MRVL88X2011_LED_BLKRATE_MASK 0x70
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#define MRVL88X2011_LED_BLKRATE_034MS 0x0
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#define MRVL88X2011_LED_BLKRATE_067MS 0x1
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#define MRVL88X2011_LED_BLKRATE_134MS 0x2
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#define MRVL88X2011_LED_BLKRATE_269MS 0x3
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#define MRVL88X2011_LED_BLKRATE_538MS 0x4
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#define MRVL88X2011_LED_CTL_OFF 0x0
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#define MRVL88X2011_LED_CTL_PCS_ACT 0x5
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#define MRVL88X2011_LED_CTL_MASK 0x7
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#define MRVL88X2011_LED(n,v) ((v)<<((n)*4))
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#define MRVL88X2011_LED_STAT(n,v) ((v)>>((n)*4))
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#define BCM8704_PMA_PMD_DEV_ADDR 1
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#define BCM8704_PCS_DEV_ADDR 2
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