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net: txgbe: Reset hardware
Reset and initialize the hardware by configuring the MAC layer. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jiawen Wu
David S. Miller
parent
a34b3e6ed8
commit
b08012568e
@ -7,6 +7,21 @@
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#include "wx_type.h"
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#include "wx_hw.h"
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static void wx_intr_disable(struct wx_hw *wxhw, u64 qmask)
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{
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u32 mask;
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mask = (qmask & 0xFFFFFFFF);
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if (mask)
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wr32(wxhw, WX_PX_IMS(0), mask);
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if (wxhw->mac.type == wx_mac_sp) {
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mask = (qmask >> 32);
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if (mask)
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wr32(wxhw, WX_PX_IMS(1), mask);
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}
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}
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/* cmd_addr is used for some special command:
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* 1. to be sector address, when implemented erase sector command
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* 2. to be flash address when implemented read, write flash address
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@ -56,6 +71,151 @@ int wx_check_flash_load(struct wx_hw *hw, u32 check_bit)
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}
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EXPORT_SYMBOL(wx_check_flash_load);
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static void wx_disable_rx(struct wx_hw *wxhw)
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{
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u32 pfdtxgswc;
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u32 rxctrl;
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rxctrl = rd32(wxhw, WX_RDB_PB_CTL);
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if (rxctrl & WX_RDB_PB_CTL_RXEN) {
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pfdtxgswc = rd32(wxhw, WX_PSR_CTL);
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if (pfdtxgswc & WX_PSR_CTL_SW_EN) {
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pfdtxgswc &= ~WX_PSR_CTL_SW_EN;
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wr32(wxhw, WX_PSR_CTL, pfdtxgswc);
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wxhw->mac.set_lben = true;
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} else {
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wxhw->mac.set_lben = false;
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}
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rxctrl &= ~WX_RDB_PB_CTL_RXEN;
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wr32(wxhw, WX_RDB_PB_CTL, rxctrl);
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if (!(((wxhw->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) ||
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((wxhw->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) {
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/* disable mac receiver */
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wr32m(wxhw, WX_MAC_RX_CFG,
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WX_MAC_RX_CFG_RE, 0);
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}
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}
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}
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/**
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* wx_disable_pcie_master - Disable PCI-express master access
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* @wxhw: pointer to hardware structure
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*
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* Disables PCI-Express master access and verifies there are no pending
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* requests.
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**/
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static int wx_disable_pcie_master(struct wx_hw *wxhw)
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{
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int status = 0;
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u32 val;
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/* Always set this bit to ensure any future transactions are blocked */
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pci_clear_master(wxhw->pdev);
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/* Exit if master requests are blocked */
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if (!(rd32(wxhw, WX_PX_TRANSACTION_PENDING)))
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return 0;
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/* Poll for master request bit to clear */
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status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT,
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false, wxhw, WX_PX_TRANSACTION_PENDING);
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if (status < 0)
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wx_err(wxhw, "PCIe transaction pending bit did not clear.\n");
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return status;
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}
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/**
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* wx_stop_adapter - Generic stop Tx/Rx units
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* @wxhw: pointer to hardware structure
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*
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* Sets the adapter_stopped flag within wx_hw struct. Clears interrupts,
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* disables transmit and receive units. The adapter_stopped flag is used by
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* the shared code and drivers to determine if the adapter is in a stopped
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* state and should not touch the hardware.
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**/
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int wx_stop_adapter(struct wx_hw *wxhw)
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{
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u16 i;
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/* Set the adapter_stopped flag so other driver functions stop touching
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* the hardware
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*/
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wxhw->adapter_stopped = true;
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/* Disable the receive unit */
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wx_disable_rx(wxhw);
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/* Set interrupt mask to stop interrupts from being generated */
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wx_intr_disable(wxhw, WX_INTR_ALL);
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/* Clear any pending interrupts, flush previous writes */
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wr32(wxhw, WX_PX_MISC_IC, 0xffffffff);
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wr32(wxhw, WX_BME_CTL, 0x3);
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/* Disable the transmit unit. Each queue must be disabled. */
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for (i = 0; i < wxhw->mac.max_tx_queues; i++) {
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wr32m(wxhw, WX_PX_TR_CFG(i),
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WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE,
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WX_PX_TR_CFG_SWFLSH);
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}
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/* Disable the receive unit by stopping each queue */
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for (i = 0; i < wxhw->mac.max_rx_queues; i++) {
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wr32m(wxhw, WX_PX_RR_CFG(i),
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WX_PX_RR_CFG_RR_EN, 0);
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}
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/* flush all queues disables */
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WX_WRITE_FLUSH(wxhw);
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/* Prevent the PCI-E bus from hanging by disabling PCI-E master
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* access and verify no pending requests
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*/
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return wx_disable_pcie_master(wxhw);
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}
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EXPORT_SYMBOL(wx_stop_adapter);
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void wx_reset_misc(struct wx_hw *wxhw)
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{
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int i;
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/* receive packets that size > 2048 */
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wr32m(wxhw, WX_MAC_RX_CFG, WX_MAC_RX_CFG_JE, WX_MAC_RX_CFG_JE);
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/* clear counters on read */
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wr32m(wxhw, WX_MMC_CONTROL,
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WX_MMC_CONTROL_RSTONRD, WX_MMC_CONTROL_RSTONRD);
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wr32m(wxhw, WX_MAC_RX_FLOW_CTRL,
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WX_MAC_RX_FLOW_CTRL_RFE, WX_MAC_RX_FLOW_CTRL_RFE);
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wr32(wxhw, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
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wr32m(wxhw, WX_MIS_RST_ST,
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WX_MIS_RST_ST_RST_INIT, 0x1E00);
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/* errata 4: initialize mng flex tbl and wakeup flex tbl*/
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wr32(wxhw, WX_PSR_MNG_FLEX_SEL, 0);
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for (i = 0; i < 16; i++) {
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wr32(wxhw, WX_PSR_MNG_FLEX_DW_L(i), 0);
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wr32(wxhw, WX_PSR_MNG_FLEX_DW_H(i), 0);
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wr32(wxhw, WX_PSR_MNG_FLEX_MSK(i), 0);
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}
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wr32(wxhw, WX_PSR_LAN_FLEX_SEL, 0);
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for (i = 0; i < 16; i++) {
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wr32(wxhw, WX_PSR_LAN_FLEX_DW_L(i), 0);
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wr32(wxhw, WX_PSR_LAN_FLEX_DW_H(i), 0);
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wr32(wxhw, WX_PSR_LAN_FLEX_MSK(i), 0);
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}
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/* set pause frame dst mac addr */
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wr32(wxhw, WX_RDB_PFCMACDAL, 0xC2000001);
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wr32(wxhw, WX_RDB_PFCMACDAH, 0x0180);
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}
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EXPORT_SYMBOL(wx_reset_misc);
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int wx_sw_init(struct wx_hw *wxhw)
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{
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struct pci_dev *pdev = wxhw->pdev;
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@ -5,6 +5,8 @@
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#define _WX_HW_H_
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int wx_check_flash_load(struct wx_hw *hw, u32 check_bit);
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int wx_stop_adapter(struct wx_hw *wxhw);
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void wx_reset_misc(struct wx_hw *wxhw);
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int wx_sw_init(struct wx_hw *wxhw);
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#endif /* _WX_HW_H_ */
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@ -9,6 +9,20 @@
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#define PCI_VENDOR_ID_WANGXUN 0x8088
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#endif
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#define WX_NCSI_SUP 0x8000
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#define WX_NCSI_MASK 0x8000
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#define WX_WOL_SUP 0x4000
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#define WX_WOL_MASK 0x4000
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/**************** Global Registers ****************************/
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/* chip control Registers */
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#define WX_MIS_PWR 0x10000
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#define WX_MIS_RST 0x1000C
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#define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1)
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#define WX_MIS_RST_ST 0x10030
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#define WX_MIS_RST_ST_RST_INI_SHIFT 8
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#define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT)
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/* FMGR Registers */
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#define WX_SPI_CMD 0x10104
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#define WX_SPI_CMD_READ_DWORD 0x1
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@ -25,16 +39,120 @@
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#define WX_SPI_STATUS_FLASH_BYPASS BIT(31)
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#define WX_SPI_ILDR_STATUS 0x10120
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/* Sensors for PVT(Process Voltage Temperature) */
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#define WX_TS_EN 0x10304
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#define WX_TS_EN_ENA BIT(0)
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#define WX_TS_ALARM_THRE 0x1030C
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#define WX_TS_DALARM_THRE 0x10310
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#define WX_TS_INT_EN 0x10314
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#define WX_TS_INT_EN_DALARM_INT_EN BIT(1)
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#define WX_TS_INT_EN_ALARM_INT_EN BIT(0)
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#define WX_TS_ALARM_ST 0x10318
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#define WX_TS_ALARM_ST_DALARM BIT(1)
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#define WX_TS_ALARM_ST_ALARM BIT(0)
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/***************************** RDB registers *********************************/
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/* receive packet buffer */
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#define WX_RDB_PB_CTL 0x19000
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#define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */
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#define WX_RDB_PB_CTL_DISABLED BIT(0)
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/* statistic */
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#define WX_RDB_PFCMACDAL 0x19210
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#define WX_RDB_PFCMACDAH 0x19214
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/******************************* PSR Registers *******************************/
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/* psr control */
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#define WX_PSR_CTL 0x15000
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/* Header split receive */
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#define WX_PSR_CTL_SW_EN BIT(18)
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#define WX_PSR_CTL_RSC_ACK BIT(17)
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#define WX_PSR_CTL_RSC_DIS BIT(16)
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#define WX_PSR_CTL_PCSD BIT(13)
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#define WX_PSR_CTL_IPPCSE BIT(12)
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#define WX_PSR_CTL_BAM BIT(10)
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#define WX_PSR_CTL_UPE BIT(9)
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#define WX_PSR_CTL_MPE BIT(8)
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#define WX_PSR_CTL_MFE BIT(7)
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#define WX_PSR_CTL_MO_SHIFT 5
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#define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT)
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#define WX_PSR_CTL_TPE BIT(4)
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/* Management */
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#define WX_PSR_MNG_FLEX_SEL 0x1582C
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#define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16))
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#define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16))
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#define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16))
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#define WX_PSR_LAN_FLEX_SEL 0x15B8C
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#define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16))
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#define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16))
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#define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16))
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/************************************* ETH MAC *****************************/
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#define WX_MAC_RX_CFG 0x11004
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#define WX_MAC_RX_CFG_RE BIT(0)
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#define WX_MAC_RX_CFG_JE BIT(8)
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#define WX_MAC_PKT_FLT 0x11008
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#define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */
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#define WX_MAC_RX_FLOW_CTRL 0x11090
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#define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */
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#define WX_MMC_CONTROL 0x11800
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#define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */
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/********************************* BAR registers ***************************/
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/* Interrupt Registers */
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#define WX_BME_CTL 0x12020
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#define WX_PX_MISC_IC 0x100
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#define WX_PX_IMS(_i) (0x140 + (_i) * 4)
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#define WX_PX_TRANSACTION_PENDING 0x168
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/* transmit DMA Registers */
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#define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40))
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/* Transmit Config masks */
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#define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */
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#define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */
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#define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */
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#define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
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#define WX_PX_TR_CFG_THRE_SHIFT 8
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/* Receive DMA Registers */
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#define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40))
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/* PX_RR_CFG bit definitions */
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#define WX_PX_RR_CFG_RR_EN BIT(0)
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/* Number of 80 microseconds we wait for PCI Express master disable */
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#define WX_PCI_MASTER_DISABLE_TIMEOUT 80000
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/* Bus parameters */
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struct wx_bus_info {
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u8 func;
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u16 device;
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};
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struct wx_thermal_sensor_data {
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s16 temp;
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s16 alarm_thresh;
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s16 dalarm_thresh;
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};
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enum wx_mac_type {
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wx_mac_unknown = 0,
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wx_mac_sp,
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wx_mac_em
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};
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struct wx_mac_info {
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enum wx_mac_type type;
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bool set_lben;
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u32 max_tx_queues;
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u32 max_rx_queues;
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struct wx_thermal_sensor_data sensor;
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};
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struct wx_hw {
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u8 __iomem *hw_addr;
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struct pci_dev *pdev;
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struct wx_bus_info bus;
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struct wx_mac_info mac;
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u16 device_id;
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u16 vendor_id;
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u16 subsystem_device_id;
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@ -42,12 +160,40 @@ struct wx_hw {
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u8 revision_id;
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u16 oem_ssid;
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u16 oem_svid;
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bool adapter_stopped;
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};
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#define WX_INTR_ALL (~0ULL)
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/* register operations */
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#define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
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#define rd32(a, reg) readl((a)->hw_addr + (reg))
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static inline u32
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rd32m(struct wx_hw *wxhw, u32 reg, u32 mask)
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{
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u32 val;
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val = rd32(wxhw, reg);
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return val & mask;
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}
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static inline void
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wr32m(struct wx_hw *wxhw, u32 reg, u32 mask, u32 field)
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{
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u32 val;
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val = rd32(wxhw, reg);
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val = ((val & ~mask) | (field & mask));
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wr32(wxhw, reg, val);
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}
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/* On some domestic CPU platforms, sometimes IO is not synchronized with
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* flushing memory, here use readl() to flush PCI read and write.
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*/
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#define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR)
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#define wx_err(wxhw, fmt, arg...) \
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dev_err(&(wxhw)->pdev->dev, fmt, ##arg)
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@ -6,4 +6,5 @@
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obj-$(CONFIG_TXGBE) += txgbe.o
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txgbe-objs := txgbe_main.o
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txgbe-objs := txgbe_main.o \
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txgbe_hw.o
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@ -4,13 +4,14 @@
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#ifndef _TXGBE_H_
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#define _TXGBE_H_
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#include "txgbe_type.h"
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#define TXGBE_MAX_FDIR_INDICES 63
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#define TXGBE_MAX_RX_QUEUES (TXGBE_MAX_FDIR_INDICES + 1)
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#define TXGBE_MAX_TX_QUEUES (TXGBE_MAX_FDIR_INDICES + 1)
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#define TXGBE_SP_MAX_TX_QUEUES 128
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#define TXGBE_SP_MAX_RX_QUEUES 128
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/* board specific private data structure */
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struct txgbe_adapter {
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u8 __iomem *io_addr; /* Mainly for iounmap use */
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86
drivers/net/ethernet/wangxun/txgbe/txgbe_hw.c
Normal file
86
drivers/net/ethernet/wangxun/txgbe/txgbe_hw.c
Normal file
@ -0,0 +1,86 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
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#include <linux/string.h>
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#include <linux/iopoll.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include "../libwx/wx_type.h"
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#include "../libwx/wx_hw.h"
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#include "txgbe_type.h"
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#include "txgbe_hw.h"
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#include "txgbe.h"
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/**
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* txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
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* @hw: pointer to hardware structure
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*
|
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* Inits the thermal sensor thresholds according to the NVM map
|
||||
* and save off the threshold and location values into mac.thermal_sensor_data
|
||||
**/
|
||||
static void txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
|
||||
{
|
||||
struct wx_hw *wxhw = &hw->wxhw;
|
||||
struct wx_thermal_sensor_data *data = &wxhw->mac.sensor;
|
||||
|
||||
memset(data, 0, sizeof(struct wx_thermal_sensor_data));
|
||||
|
||||
/* Only support thermal sensors attached to SP physical port 0 */
|
||||
if (wxhw->bus.func)
|
||||
return;
|
||||
|
||||
wr32(wxhw, TXGBE_TS_CTL, TXGBE_TS_CTL_EVAL_MD);
|
||||
|
||||
wr32(wxhw, WX_TS_INT_EN,
|
||||
WX_TS_INT_EN_ALARM_INT_EN | WX_TS_INT_EN_DALARM_INT_EN);
|
||||
wr32(wxhw, WX_TS_EN, WX_TS_EN_ENA);
|
||||
|
||||
data->alarm_thresh = 100;
|
||||
wr32(wxhw, WX_TS_ALARM_THRE, 677);
|
||||
data->dalarm_thresh = 90;
|
||||
wr32(wxhw, WX_TS_DALARM_THRE, 614);
|
||||
}
|
||||
|
||||
static void txgbe_reset_misc(struct txgbe_hw *hw)
|
||||
{
|
||||
struct wx_hw *wxhw = &hw->wxhw;
|
||||
|
||||
wx_reset_misc(wxhw);
|
||||
txgbe_init_thermal_sensor_thresh(hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* txgbe_reset_hw - Perform hardware reset
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Resets the hardware by resetting the transmit and receive units, masks
|
||||
* and clears all interrupts, perform a PHY reset, and perform a link (MAC)
|
||||
* reset.
|
||||
**/
|
||||
int txgbe_reset_hw(struct txgbe_hw *hw)
|
||||
{
|
||||
struct wx_hw *wxhw = &hw->wxhw;
|
||||
u32 reset = 0;
|
||||
int status;
|
||||
|
||||
/* Call adapter stop to disable tx/rx and clear interrupts */
|
||||
status = wx_stop_adapter(wxhw);
|
||||
if (status != 0)
|
||||
return status;
|
||||
|
||||
reset = WX_MIS_RST_LAN_RST(wxhw->bus.func);
|
||||
wr32(wxhw, WX_MIS_RST, reset | rd32(wxhw, WX_MIS_RST));
|
||||
|
||||
WX_WRITE_FLUSH(wxhw);
|
||||
usleep_range(10, 100);
|
||||
|
||||
status = wx_check_flash_load(wxhw, TXGBE_SPI_ILDR_STATUS_LAN_SW_RST(wxhw->bus.func));
|
||||
if (status != 0)
|
||||
return status;
|
||||
|
||||
txgbe_reset_misc(hw);
|
||||
pci_set_master(wxhw->pdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
9
drivers/net/ethernet/wangxun/txgbe/txgbe_hw.h
Normal file
9
drivers/net/ethernet/wangxun/txgbe/txgbe_hw.h
Normal file
@ -0,0 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
|
||||
|
||||
#ifndef _TXGBE_HW_H_
|
||||
#define _TXGBE_HW_H_
|
||||
|
||||
int txgbe_reset_hw(struct txgbe_hw *hw);
|
||||
|
||||
#endif /* _TXGBE_HW_H_ */
|
||||
@ -11,6 +11,8 @@
|
||||
|
||||
#include "../libwx/wx_type.h"
|
||||
#include "../libwx/wx_hw.h"
|
||||
#include "txgbe_type.h"
|
||||
#include "txgbe_hw.h"
|
||||
#include "txgbe.h"
|
||||
|
||||
char txgbe_driver_name[] = "txgbe";
|
||||
@ -92,6 +94,19 @@ static int txgbe_sw_init(struct txgbe_adapter *adapter)
|
||||
return err;
|
||||
}
|
||||
|
||||
switch (wxhw->device_id) {
|
||||
case TXGBE_DEV_ID_SP1000:
|
||||
case TXGBE_DEV_ID_WX1820:
|
||||
wxhw->mac.type = wx_mac_sp;
|
||||
break;
|
||||
default:
|
||||
wxhw->mac.type = wx_mac_unknown;
|
||||
break;
|
||||
}
|
||||
|
||||
wxhw->mac.max_tx_queues = TXGBE_SP_MAX_TX_QUEUES;
|
||||
wxhw->mac.max_rx_queues = TXGBE_SP_MAX_RX_QUEUES;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -201,6 +216,12 @@ static int txgbe_probe(struct pci_dev *pdev,
|
||||
if (err)
|
||||
goto err_pci_release_regions;
|
||||
|
||||
err = txgbe_reset_hw(hw);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "HW Init failed: %d\n", err);
|
||||
goto err_pci_release_regions;
|
||||
}
|
||||
|
||||
netdev->features |= NETIF_F_HIGHDMA;
|
||||
|
||||
pci_set_drvdata(pdev, adapter);
|
||||
|
||||
@ -33,12 +33,6 @@
|
||||
#define TXGBE_ID_WX1820_MAC_SGMII 0x2060
|
||||
#define TXGBE_ID_MAC_SGMII 0x60
|
||||
|
||||
#define TXGBE_NCSI_SUP 0x8000
|
||||
#define TXGBE_NCSI_MASK 0x8000
|
||||
#define TXGBE_WOL_SUP 0x4000
|
||||
#define TXGBE_WOL_MASK 0x4000
|
||||
#define TXGBE_DEV_MASK 0xf0
|
||||
|
||||
/* Combined interface*/
|
||||
#define TXGBE_ID_SFI_XAUI 0x50
|
||||
|
||||
@ -50,6 +44,11 @@
|
||||
#define TXGBE_SPI_ILDR_STATUS 0x10120
|
||||
#define TXGBE_SPI_ILDR_STATUS_PERST BIT(0) /* PCIE_PERST is done */
|
||||
#define TXGBE_SPI_ILDR_STATUS_PWRRST BIT(1) /* Power on reset is done */
|
||||
#define TXGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i) BIT((_i) + 9) /* lan soft reset done */
|
||||
|
||||
/* Sensors for PVT(Process Voltage Temperature) */
|
||||
#define TXGBE_TS_CTL 0x10300
|
||||
#define TXGBE_TS_CTL_EVAL_MD BIT(31)
|
||||
|
||||
struct txgbe_hw {
|
||||
struct wx_hw wxhw;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user