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linux-can-next-for-5.11-20201214
-----BEGIN PGP SIGNATURE----- iQFHBAABCgAxFiEEK3kIWJt9yTYMP3ehqclaivrt76kFAl/XZ40THG1rbEBwZW5n dXRyb25peC5kZQAKCRCpyVqK+u3vqVH5CACZGHhJFZfFCosQVz0vWPdAlOFlaXX6 MnUL1/cNPUYrLCPUducvM7xGdziD7pp2xQS5hvM2Gt0xU6hT2QRM3g7yWLOvpJU0 ewwbWvP2KbaR/DW8deV16Y8kQvxHjcOBgJLkHuAprbohHe8Slvj+9JknvNEVoNna BP+zLTKuU0cC3uajcC5UfIffXUR9t7wl0Jmams0lE/toC62lO2qozMwsVo1BiXhS YmD0oY4/0f02m8bpTfOGSSRrifVa1fbgMv+Bbuiqokj9HEH/YXs8zeibSl4qNZ45 sbYrawCZd5KgafnpSAwnHdy3B6b6qKqLxQRa+DXgM4xzxsUOn2iFUXbb =ma2Z -----END PGP SIGNATURE----- Merge tag 'linux-can-next-for-5.11-20201214' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next Marc Kleine-Budde says: ==================== pull-request: can-next 2020-12-14 All 7 patches are by me and target the m_can driver. First there are 4 cleanup patches (fix link to doc, fix coding style, uniform variable name usage, mark function as static). Then the driver is converted to pm_runtime_resume_and_get(). The next patch lets the m_can class driver allocate the driver's private data, to get rid of one level of indirection. And the last patch consistently uses struct m_can_classdev as drvdata over all binding drivers. * tag 'linux-can-next-for-5.11-20201214' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next: can: m_can: use struct m_can_classdev as drvdata can: m_can: let m_can_class_allocate_dev() allocate driver specific private data can: m_can: m_can_clk_start(): make use of pm_runtime_resume_and_get() can: m_can: m_can_config_endisable(): mark as static can: m_can: use cdev as name for struct m_can_classdev uniformly can: m_can: convert indention to kernel coding style can: m_can: update link to M_CAN user manual ==================== Link: https://lore.kernel.org/r/20201214133145.442472-1-mkl@pengutronix.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
b024875607
@ -5,8 +5,7 @@
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// Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
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/* Bosch M_CAN user manual can be obtained from:
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* http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
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* mcan_users_manual_v302.pdf
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* https://github.com/linux-can/can-doc/tree/master/m_can
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*/
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#include <linux/interrupt.h>
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@ -40,7 +39,7 @@ enum m_can_reg {
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M_CAN_TOCV = 0x2c,
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M_CAN_ECR = 0x40,
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M_CAN_PSR = 0x44,
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/* TDCR Register only available for version >=3.1.x */
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/* TDCR Register only available for version >=3.1.x */
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M_CAN_TDCR = 0x48,
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M_CAN_IR = 0x50,
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M_CAN_IE = 0x54,
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@ -336,7 +335,7 @@ static u32 m_can_fifo_read(struct m_can_classdev *cdev,
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u32 fgi, unsigned int offset)
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{
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u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
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offset;
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offset;
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return cdev->ops->read_fifo(cdev, addr_offset);
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}
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@ -345,7 +344,7 @@ static void m_can_fifo_write(struct m_can_classdev *cdev,
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u32 fpi, unsigned int offset, u32 val)
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{
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u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
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offset;
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offset;
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cdev->ops->write_fifo(cdev, addr_offset, val);
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}
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@ -359,17 +358,17 @@ static inline void m_can_fifo_write_no_off(struct m_can_classdev *cdev,
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static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset)
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{
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u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
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offset;
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offset;
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return cdev->ops->read_fifo(cdev, addr_offset);
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}
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static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev)
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{
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return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF);
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return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF);
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}
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void m_can_config_endisable(struct m_can_classdev *cdev, bool enable)
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static void m_can_config_endisable(struct m_can_classdev *cdev, bool enable)
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{
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u32 cccr = m_can_read(cdev, M_CAN_CCCR);
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u32 timeout = 10;
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@ -613,18 +612,10 @@ static int __m_can_get_berr_counter(const struct net_device *dev,
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static int m_can_clk_start(struct m_can_classdev *cdev)
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{
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int err;
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if (cdev->pm_clock_support == 0)
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return 0;
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err = pm_runtime_get_sync(cdev->dev);
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if (err < 0) {
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pm_runtime_put_noidle(cdev->dev);
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return err;
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}
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return 0;
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return pm_runtime_resume_and_get(cdev->dev);
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}
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static void m_can_clk_stop(struct m_can_classdev *cdev)
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@ -922,14 +913,13 @@ static void m_can_echo_tx_event(struct net_device *dev)
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m_can_txefs = m_can_read(cdev, M_CAN_TXEFS);
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/* Get Tx Event fifo element count */
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txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
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>> TXEFS_EFFL_SHIFT;
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txe_count = (m_can_txefs & TXEFS_EFFL_MASK) >> TXEFS_EFFL_SHIFT;
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/* Get and process all sent elements */
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for (i = 0; i < txe_count; i++) {
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/* retrieve get index */
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fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
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>> TXEFS_EFGI_SHIFT;
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fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK) >>
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TXEFS_EFGI_SHIFT;
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/* get message marker */
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msg_mark = (m_can_txe_fifo_read(cdev, fgi, 4) &
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@ -1088,7 +1078,7 @@ static int m_can_set_bittiming(struct net_device *dev)
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* Transmitter Delay Compensation Section
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*/
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tdco = (cdev->can.clock.freq / 1000) *
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ssp / dbt->bitrate;
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ssp / dbt->bitrate;
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/* Max valid TDCO value is 127 */
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if (tdco > 127) {
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@ -1103,9 +1093,9 @@ static int m_can_set_bittiming(struct net_device *dev)
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}
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reg_btp |= (brp << DBTP_DBRP_SHIFT) |
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(sjw << DBTP_DSJW_SHIFT) |
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(tseg1 << DBTP_DTSEG1_SHIFT) |
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(tseg2 << DBTP_DTSEG2_SHIFT);
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(sjw << DBTP_DSJW_SHIFT) |
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(tseg1 << DBTP_DTSEG1_SHIFT) |
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(tseg2 << DBTP_DTSEG2_SHIFT);
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m_can_write(cdev, M_CAN_DBTP, reg_btp);
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}
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@ -1138,7 +1128,7 @@ static void m_can_chip_config(struct net_device *dev)
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if (cdev->version == 30) {
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/* only support one Tx Buffer currently */
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m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
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cdev->mcfg[MRAM_TXB].off);
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cdev->mcfg[MRAM_TXB].off);
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} else {
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/* TX FIFO is used for newer IP Core versions */
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m_can_write(cdev, M_CAN_TXBC,
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@ -1152,7 +1142,7 @@ static void m_can_chip_config(struct net_device *dev)
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/* TX Event FIFO */
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if (cdev->version == 30) {
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m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
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cdev->mcfg[MRAM_TXE].off);
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cdev->mcfg[MRAM_TXE].off);
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} else {
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/* Full TX Event FIFO is used */
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m_can_write(cdev, M_CAN_TXEFC,
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@ -1164,27 +1154,27 @@ static void m_can_chip_config(struct net_device *dev)
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/* rx fifo configuration, blocking mode, fifo size 1 */
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m_can_write(cdev, M_CAN_RXF0C,
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(cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) |
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cdev->mcfg[MRAM_RXF0].off);
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cdev->mcfg[MRAM_RXF0].off);
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m_can_write(cdev, M_CAN_RXF1C,
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(cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) |
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cdev->mcfg[MRAM_RXF1].off);
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cdev->mcfg[MRAM_RXF1].off);
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cccr = m_can_read(cdev, M_CAN_CCCR);
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test = m_can_read(cdev, M_CAN_TEST);
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test &= ~TEST_LBCK;
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if (cdev->version == 30) {
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/* Version 3.0.x */
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/* Version 3.0.x */
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cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR |
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(CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
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(CCCR_CME_MASK << CCCR_CME_SHIFT));
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(CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
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(CCCR_CME_MASK << CCCR_CME_SHIFT));
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if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
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cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
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} else {
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/* Version 3.1.x or 3.2.x */
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/* Version 3.1.x or 3.2.x */
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cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE |
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CCCR_NISO | CCCR_DAR);
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@ -1329,80 +1319,79 @@ static bool m_can_niso_supported(struct m_can_classdev *cdev)
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return !niso_timeout;
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}
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static int m_can_dev_setup(struct m_can_classdev *m_can_dev)
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static int m_can_dev_setup(struct m_can_classdev *cdev)
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{
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struct net_device *dev = m_can_dev->net;
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struct net_device *dev = cdev->net;
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int m_can_version;
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m_can_version = m_can_check_core_release(m_can_dev);
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m_can_version = m_can_check_core_release(cdev);
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/* return if unsupported version */
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if (!m_can_version) {
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dev_err(m_can_dev->dev, "Unsupported version number: %2d",
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dev_err(cdev->dev, "Unsupported version number: %2d",
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m_can_version);
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return -EINVAL;
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}
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if (!m_can_dev->is_peripheral)
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netif_napi_add(dev, &m_can_dev->napi,
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if (!cdev->is_peripheral)
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netif_napi_add(dev, &cdev->napi,
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m_can_poll, M_CAN_NAPI_WEIGHT);
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/* Shared properties of all M_CAN versions */
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m_can_dev->version = m_can_version;
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m_can_dev->can.do_set_mode = m_can_set_mode;
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m_can_dev->can.do_get_berr_counter = m_can_get_berr_counter;
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cdev->version = m_can_version;
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cdev->can.do_set_mode = m_can_set_mode;
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cdev->can.do_get_berr_counter = m_can_get_berr_counter;
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/* Set M_CAN supported operations */
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m_can_dev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
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CAN_CTRLMODE_LISTENONLY |
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CAN_CTRLMODE_BERR_REPORTING |
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CAN_CTRLMODE_FD |
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CAN_CTRLMODE_ONE_SHOT;
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cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
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CAN_CTRLMODE_LISTENONLY |
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CAN_CTRLMODE_BERR_REPORTING |
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CAN_CTRLMODE_FD |
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CAN_CTRLMODE_ONE_SHOT;
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/* Set properties depending on M_CAN version */
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switch (m_can_dev->version) {
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switch (cdev->version) {
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case 30:
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/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
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can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
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m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
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m_can_dev->bit_timing : &m_can_bittiming_const_30X;
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cdev->can.bittiming_const = cdev->bit_timing ?
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cdev->bit_timing : &m_can_bittiming_const_30X;
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m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
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m_can_dev->data_timing :
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&m_can_data_bittiming_const_30X;
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cdev->can.data_bittiming_const = cdev->data_timing ?
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cdev->data_timing :
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&m_can_data_bittiming_const_30X;
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break;
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case 31:
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/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
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can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
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m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
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m_can_dev->bit_timing : &m_can_bittiming_const_31X;
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cdev->can.bittiming_const = cdev->bit_timing ?
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cdev->bit_timing : &m_can_bittiming_const_31X;
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m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
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m_can_dev->data_timing :
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&m_can_data_bittiming_const_31X;
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cdev->can.data_bittiming_const = cdev->data_timing ?
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cdev->data_timing :
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&m_can_data_bittiming_const_31X;
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break;
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case 32:
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case 33:
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/* Support both MCAN version v3.2.x and v3.3.0 */
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m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
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m_can_dev->bit_timing : &m_can_bittiming_const_31X;
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cdev->can.bittiming_const = cdev->bit_timing ?
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cdev->bit_timing : &m_can_bittiming_const_31X;
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m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
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m_can_dev->data_timing :
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&m_can_data_bittiming_const_31X;
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cdev->can.data_bittiming_const = cdev->data_timing ?
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cdev->data_timing :
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&m_can_data_bittiming_const_31X;
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m_can_dev->can.ctrlmode_supported |=
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(m_can_niso_supported(m_can_dev)
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? CAN_CTRLMODE_FD_NON_ISO
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: 0);
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cdev->can.ctrlmode_supported |=
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(m_can_niso_supported(cdev) ?
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CAN_CTRLMODE_FD_NON_ISO : 0);
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break;
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default:
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dev_err(m_can_dev->dev, "Unsupported version number: %2d",
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m_can_dev->version);
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dev_err(cdev->dev, "Unsupported version number: %2d",
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cdev->version);
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return -EINVAL;
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}
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if (m_can_dev->ops->init)
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m_can_dev->ops->init(m_can_dev);
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if (cdev->ops->init)
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cdev->ops->init(cdev);
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return 0;
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}
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@ -1535,7 +1524,7 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
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/* get put index for frame */
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putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
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>> TXFQS_TFQPI_SHIFT);
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>> TXFQS_TFQPI_SHIFT);
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/* Write ID Field to FIFO Element */
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m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id);
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@ -1582,7 +1571,7 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
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static void m_can_tx_work_queue(struct work_struct *ws)
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{
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struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev,
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tx_work);
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tx_work);
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m_can_tx_handler(cdev);
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cdev->tx_skb = NULL;
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@ -1706,26 +1695,26 @@ static void m_can_of_parse_mram(struct m_can_classdev *cdev,
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cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0];
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cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1];
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cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off +
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cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
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cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
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cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2];
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cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off +
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cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
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cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
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cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
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(RXFC_FS_MASK >> RXFC_FS_SHIFT);
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(RXFC_FS_MASK >> RXFC_FS_SHIFT);
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cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off +
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cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
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cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
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cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
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(RXFC_FS_MASK >> RXFC_FS_SHIFT);
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(RXFC_FS_MASK >> RXFC_FS_SHIFT);
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cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off +
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cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
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cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
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cdev->mcfg[MRAM_RXB].num = mram_config_vals[5];
|
||||
cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off +
|
||||
cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
|
||||
cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
|
||||
cdev->mcfg[MRAM_TXE].num = mram_config_vals[6];
|
||||
cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off +
|
||||
cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
|
||||
cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
|
||||
cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] &
|
||||
(TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
|
||||
(TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
|
||||
|
||||
dev_dbg(cdev->dev,
|
||||
"sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
|
||||
@ -1754,15 +1743,15 @@ void m_can_init_ram(struct m_can_classdev *cdev)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(m_can_init_ram);
|
||||
|
||||
int m_can_class_get_clocks(struct m_can_classdev *m_can_dev)
|
||||
int m_can_class_get_clocks(struct m_can_classdev *cdev)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
m_can_dev->hclk = devm_clk_get(m_can_dev->dev, "hclk");
|
||||
m_can_dev->cclk = devm_clk_get(m_can_dev->dev, "cclk");
|
||||
cdev->hclk = devm_clk_get(cdev->dev, "hclk");
|
||||
cdev->cclk = devm_clk_get(cdev->dev, "cclk");
|
||||
|
||||
if (IS_ERR(m_can_dev->cclk)) {
|
||||
dev_err(m_can_dev->dev, "no clock found\n");
|
||||
if (IS_ERR(cdev->cclk)) {
|
||||
dev_err(cdev->dev, "no clock found\n");
|
||||
ret = -ENODEV;
|
||||
}
|
||||
|
||||
@ -1770,7 +1759,8 @@ int m_can_class_get_clocks(struct m_can_classdev *m_can_dev)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(m_can_class_get_clocks);
|
||||
|
||||
struct m_can_classdev *m_can_class_allocate_dev(struct device *dev)
|
||||
struct m_can_classdev *m_can_class_allocate_dev(struct device *dev,
|
||||
int sizeof_priv)
|
||||
{
|
||||
struct m_can_classdev *class_dev = NULL;
|
||||
u32 mram_config_vals[MRAM_CFG_LEN];
|
||||
@ -1793,7 +1783,7 @@ struct m_can_classdev *m_can_class_allocate_dev(struct device *dev)
|
||||
tx_fifo_size = mram_config_vals[7];
|
||||
|
||||
/* allocate the m_can device */
|
||||
net_dev = alloc_candev(sizeof(*class_dev), tx_fifo_size);
|
||||
net_dev = alloc_candev(sizeof_priv, tx_fifo_size);
|
||||
if (!net_dev) {
|
||||
dev_err(dev, "Failed to allocate CAN device");
|
||||
goto out;
|
||||
@ -1821,56 +1811,56 @@ void m_can_class_free_dev(struct net_device *net)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(m_can_class_free_dev);
|
||||
|
||||
int m_can_class_register(struct m_can_classdev *m_can_dev)
|
||||
int m_can_class_register(struct m_can_classdev *cdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (m_can_dev->pm_clock_support) {
|
||||
ret = m_can_clk_start(m_can_dev);
|
||||
if (cdev->pm_clock_support) {
|
||||
ret = m_can_clk_start(cdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = m_can_dev_setup(m_can_dev);
|
||||
ret = m_can_dev_setup(cdev);
|
||||
if (ret)
|
||||
goto clk_disable;
|
||||
|
||||
ret = register_m_can_dev(m_can_dev->net);
|
||||
ret = register_m_can_dev(cdev->net);
|
||||
if (ret) {
|
||||
dev_err(m_can_dev->dev, "registering %s failed (err=%d)\n",
|
||||
m_can_dev->net->name, ret);
|
||||
dev_err(cdev->dev, "registering %s failed (err=%d)\n",
|
||||
cdev->net->name, ret);
|
||||
goto clk_disable;
|
||||
}
|
||||
|
||||
devm_can_led_init(m_can_dev->net);
|
||||
devm_can_led_init(cdev->net);
|
||||
|
||||
of_can_transceiver(m_can_dev->net);
|
||||
of_can_transceiver(cdev->net);
|
||||
|
||||
dev_info(m_can_dev->dev, "%s device registered (irq=%d, version=%d)\n",
|
||||
KBUILD_MODNAME, m_can_dev->net->irq, m_can_dev->version);
|
||||
dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n",
|
||||
KBUILD_MODNAME, cdev->net->irq, cdev->version);
|
||||
|
||||
/* Probe finished
|
||||
* Stop clocks. They will be reactivated once the M_CAN device is opened
|
||||
*/
|
||||
clk_disable:
|
||||
m_can_clk_stop(m_can_dev);
|
||||
m_can_clk_stop(cdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(m_can_class_register);
|
||||
|
||||
void m_can_class_unregister(struct m_can_classdev *m_can_dev)
|
||||
void m_can_class_unregister(struct m_can_classdev *cdev)
|
||||
{
|
||||
unregister_candev(m_can_dev->net);
|
||||
unregister_candev(cdev->net);
|
||||
|
||||
m_can_clk_stop(m_can_dev);
|
||||
m_can_clk_stop(cdev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(m_can_class_unregister);
|
||||
|
||||
int m_can_class_suspend(struct device *dev)
|
||||
{
|
||||
struct net_device *ndev = dev_get_drvdata(dev);
|
||||
struct m_can_classdev *cdev = netdev_priv(ndev);
|
||||
struct m_can_classdev *cdev = dev_get_drvdata(dev);
|
||||
struct net_device *ndev = cdev->net;
|
||||
|
||||
if (netif_running(ndev)) {
|
||||
netif_stop_queue(ndev);
|
||||
@ -1889,8 +1879,8 @@ EXPORT_SYMBOL_GPL(m_can_class_suspend);
|
||||
|
||||
int m_can_class_resume(struct device *dev)
|
||||
{
|
||||
struct net_device *ndev = dev_get_drvdata(dev);
|
||||
struct m_can_classdev *cdev = netdev_priv(ndev);
|
||||
struct m_can_classdev *cdev = dev_get_drvdata(dev);
|
||||
struct net_device *ndev = cdev->net;
|
||||
|
||||
pinctrl_pm_select_default_state(dev);
|
||||
|
||||
|
||||
@ -86,8 +86,6 @@ struct m_can_classdev {
|
||||
|
||||
struct m_can_ops *ops;
|
||||
|
||||
void *device_data;
|
||||
|
||||
int version;
|
||||
u32 irqstatus;
|
||||
|
||||
@ -97,13 +95,12 @@ struct m_can_classdev {
|
||||
struct mram_cfg mcfg[MRAM_CFG_NUM];
|
||||
};
|
||||
|
||||
struct m_can_classdev *m_can_class_allocate_dev(struct device *dev);
|
||||
struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv);
|
||||
void m_can_class_free_dev(struct net_device *net);
|
||||
int m_can_class_register(struct m_can_classdev *cdev);
|
||||
void m_can_class_unregister(struct m_can_classdev *cdev);
|
||||
int m_can_class_get_clocks(struct m_can_classdev *cdev);
|
||||
void m_can_init_ram(struct m_can_classdev *priv);
|
||||
void m_can_config_endisable(struct m_can_classdev *priv, bool enable);
|
||||
|
||||
int m_can_class_suspend(struct device *dev);
|
||||
int m_can_class_resume(struct device *dev);
|
||||
|
||||
@ -22,26 +22,33 @@
|
||||
#define CTL_CSR_INT_CTL_OFFSET 0x508
|
||||
|
||||
struct m_can_pci_priv {
|
||||
struct m_can_classdev cdev;
|
||||
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
static inline struct m_can_pci_priv *cdev_to_priv(struct m_can_classdev *cdev)
|
||||
{
|
||||
return container_of(cdev, struct m_can_pci_priv, cdev);
|
||||
}
|
||||
|
||||
static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
|
||||
{
|
||||
struct m_can_pci_priv *priv = cdev->device_data;
|
||||
struct m_can_pci_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
return readl(priv->base + reg);
|
||||
}
|
||||
|
||||
static u32 iomap_read_fifo(struct m_can_classdev *cdev, int offset)
|
||||
{
|
||||
struct m_can_pci_priv *priv = cdev->device_data;
|
||||
struct m_can_pci_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
return readl(priv->base + offset);
|
||||
}
|
||||
|
||||
static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
{
|
||||
struct m_can_pci_priv *priv = cdev->device_data;
|
||||
struct m_can_pci_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
writel(val, priv->base + reg);
|
||||
|
||||
@ -50,7 +57,7 @@ static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
|
||||
static int iomap_write_fifo(struct m_can_classdev *cdev, int offset, int val)
|
||||
{
|
||||
struct m_can_pci_priv *priv = cdev->device_data;
|
||||
struct m_can_pci_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
writel(val, priv->base + offset);
|
||||
|
||||
@ -89,28 +96,26 @@ static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
priv = devm_kzalloc(&pci->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
mcan_class = m_can_class_allocate_dev(&pci->dev);
|
||||
mcan_class = m_can_class_allocate_dev(&pci->dev,
|
||||
sizeof(struct m_can_pci_priv));
|
||||
if (!mcan_class)
|
||||
return -ENOMEM;
|
||||
|
||||
priv = cdev_to_priv(mcan_class);
|
||||
|
||||
priv->base = base;
|
||||
|
||||
ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_ALL_TYPES);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
mcan_class->device_data = priv;
|
||||
mcan_class->dev = &pci->dev;
|
||||
mcan_class->net->irq = pci_irq_vector(pci, 0);
|
||||
mcan_class->pm_clock_support = 1;
|
||||
mcan_class->can.clock.freq = id->driver_data;
|
||||
mcan_class->ops = &m_can_pci_ops;
|
||||
|
||||
pci_set_drvdata(pci, mcan_class->net);
|
||||
pci_set_drvdata(pci, mcan_class);
|
||||
|
||||
ret = m_can_class_register(mcan_class);
|
||||
if (ret)
|
||||
@ -133,9 +138,8 @@ err:
|
||||
|
||||
static void m_can_pci_remove(struct pci_dev *pci)
|
||||
{
|
||||
struct net_device *dev = pci_get_drvdata(pci);
|
||||
struct m_can_classdev *mcan_class = netdev_priv(dev);
|
||||
struct m_can_pci_priv *priv = mcan_class->device_data;
|
||||
struct m_can_classdev *mcan_class = pci_get_drvdata(pci);
|
||||
struct m_can_pci_priv *priv = cdev_to_priv(mcan_class);
|
||||
|
||||
pm_runtime_forbid(&pci->dev);
|
||||
pm_runtime_get_noresume(&pci->dev);
|
||||
|
||||
@ -10,27 +10,34 @@
|
||||
#include "m_can.h"
|
||||
|
||||
struct m_can_plat_priv {
|
||||
struct m_can_classdev cdev;
|
||||
|
||||
void __iomem *base;
|
||||
void __iomem *mram_base;
|
||||
};
|
||||
|
||||
static inline struct m_can_plat_priv *cdev_to_priv(struct m_can_classdev *cdev)
|
||||
{
|
||||
return container_of(cdev, struct m_can_plat_priv, cdev);
|
||||
}
|
||||
|
||||
static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
|
||||
{
|
||||
struct m_can_plat_priv *priv = cdev->device_data;
|
||||
struct m_can_plat_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
return readl(priv->base + reg);
|
||||
}
|
||||
|
||||
static u32 iomap_read_fifo(struct m_can_classdev *cdev, int offset)
|
||||
{
|
||||
struct m_can_plat_priv *priv = cdev->device_data;
|
||||
struct m_can_plat_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
return readl(priv->mram_base + offset);
|
||||
}
|
||||
|
||||
static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
{
|
||||
struct m_can_plat_priv *priv = cdev->device_data;
|
||||
struct m_can_plat_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
writel(val, priv->base + reg);
|
||||
|
||||
@ -39,7 +46,7 @@ static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
|
||||
static int iomap_write_fifo(struct m_can_classdev *cdev, int offset, int val)
|
||||
{
|
||||
struct m_can_plat_priv *priv = cdev->device_data;
|
||||
struct m_can_plat_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
writel(val, priv->mram_base + offset);
|
||||
|
||||
@ -62,17 +69,12 @@ static int m_can_plat_probe(struct platform_device *pdev)
|
||||
void __iomem *mram_addr;
|
||||
int irq, ret = 0;
|
||||
|
||||
mcan_class = m_can_class_allocate_dev(&pdev->dev);
|
||||
mcan_class = m_can_class_allocate_dev(&pdev->dev,
|
||||
sizeof(struct m_can_plat_priv));
|
||||
if (!mcan_class)
|
||||
return -ENOMEM;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
ret = -ENOMEM;
|
||||
goto probe_fail;
|
||||
}
|
||||
|
||||
mcan_class->device_data = priv;
|
||||
priv = cdev_to_priv(mcan_class);
|
||||
|
||||
ret = m_can_class_get_clocks(mcan_class);
|
||||
if (ret)
|
||||
@ -111,7 +113,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
|
||||
|
||||
mcan_class->is_peripheral = false;
|
||||
|
||||
platform_set_drvdata(pdev, mcan_class->net);
|
||||
platform_set_drvdata(pdev, mcan_class);
|
||||
|
||||
m_can_init_ram(mcan_class);
|
||||
|
||||
@ -141,8 +143,8 @@ static __maybe_unused int m_can_resume(struct device *dev)
|
||||
|
||||
static int m_can_plat_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct net_device *dev = platform_get_drvdata(pdev);
|
||||
struct m_can_classdev *mcan_class = netdev_priv(dev);
|
||||
struct m_can_plat_priv *priv = platform_get_drvdata(pdev);
|
||||
struct m_can_classdev *mcan_class = &priv->cdev;
|
||||
|
||||
m_can_class_unregister(mcan_class);
|
||||
|
||||
@ -153,8 +155,8 @@ static int m_can_plat_remove(struct platform_device *pdev)
|
||||
|
||||
static int __maybe_unused m_can_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct net_device *ndev = dev_get_drvdata(dev);
|
||||
struct m_can_classdev *mcan_class = netdev_priv(ndev);
|
||||
struct m_can_plat_priv *priv = dev_get_drvdata(dev);
|
||||
struct m_can_classdev *mcan_class = &priv->cdev;
|
||||
|
||||
clk_disable_unprepare(mcan_class->cclk);
|
||||
clk_disable_unprepare(mcan_class->hclk);
|
||||
@ -164,8 +166,8 @@ static int __maybe_unused m_can_runtime_suspend(struct device *dev)
|
||||
|
||||
static int __maybe_unused m_can_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct net_device *ndev = dev_get_drvdata(dev);
|
||||
struct m_can_classdev *mcan_class = netdev_priv(ndev);
|
||||
struct m_can_plat_priv *priv = dev_get_drvdata(dev);
|
||||
struct m_can_classdev *mcan_class = &priv->cdev;
|
||||
int err;
|
||||
|
||||
err = clk_prepare_enable(mcan_class->hclk);
|
||||
|
||||
@ -114,17 +114,23 @@
|
||||
#define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29))
|
||||
|
||||
struct tcan4x5x_priv {
|
||||
struct m_can_classdev cdev;
|
||||
|
||||
struct regmap *regmap;
|
||||
struct spi_device *spi;
|
||||
|
||||
struct m_can_classdev *mcan_dev;
|
||||
|
||||
struct gpio_desc *reset_gpio;
|
||||
struct gpio_desc *device_wake_gpio;
|
||||
struct gpio_desc *device_state_gpio;
|
||||
struct regulator *power;
|
||||
};
|
||||
|
||||
static inline struct tcan4x5x_priv *cdev_to_priv(struct m_can_classdev *cdev)
|
||||
{
|
||||
return container_of(cdev, struct tcan4x5x_priv, cdev);
|
||||
|
||||
}
|
||||
|
||||
static struct can_bittiming_const tcan4x5x_bittiming_const = {
|
||||
.name = DEVICE_NAME,
|
||||
.tseg1_min = 2,
|
||||
@ -253,7 +259,7 @@ static struct regmap_bus tcan4x5x_bus = {
|
||||
|
||||
static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg)
|
||||
{
|
||||
struct tcan4x5x_priv *priv = cdev->device_data;
|
||||
struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
|
||||
u32 val;
|
||||
|
||||
regmap_read(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, &val);
|
||||
@ -263,7 +269,7 @@ static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg)
|
||||
|
||||
static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset)
|
||||
{
|
||||
struct tcan4x5x_priv *priv = cdev->device_data;
|
||||
struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
|
||||
u32 val;
|
||||
|
||||
regmap_read(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, &val);
|
||||
@ -273,7 +279,7 @@ static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset)
|
||||
|
||||
static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
{
|
||||
struct tcan4x5x_priv *priv = cdev->device_data;
|
||||
struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
return regmap_write(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, val);
|
||||
}
|
||||
@ -281,7 +287,7 @@ static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val)
|
||||
static int tcan4x5x_write_fifo(struct m_can_classdev *cdev,
|
||||
int addr_offset, int val)
|
||||
{
|
||||
struct tcan4x5x_priv *priv = cdev->device_data;
|
||||
struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
return regmap_write(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val);
|
||||
}
|
||||
@ -300,7 +306,7 @@ static int tcan4x5x_power_enable(struct regulator *reg, int enable)
|
||||
static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev,
|
||||
int reg, int val)
|
||||
{
|
||||
struct tcan4x5x_priv *priv = cdev->device_data;
|
||||
struct tcan4x5x_priv *priv = cdev_to_priv(cdev);
|
||||
|
||||
return regmap_write(priv->regmap, reg, val);
|
||||
}
|
||||
@ -330,7 +336,7 @@ static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev)
|
||||
|
||||
static int tcan4x5x_init(struct m_can_classdev *cdev)
|
||||
{
|
||||
struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
|
||||
struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
|
||||
int ret;
|
||||
|
||||
tcan4x5x_check_wake(tcan4x5x);
|
||||
@ -357,7 +363,7 @@ static int tcan4x5x_init(struct m_can_classdev *cdev)
|
||||
|
||||
static int tcan4x5x_disable_wake(struct m_can_classdev *cdev)
|
||||
{
|
||||
struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
|
||||
struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
|
||||
|
||||
return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
|
||||
TCAN4X5X_DISABLE_WAKE_MSK, 0x00);
|
||||
@ -365,7 +371,7 @@ static int tcan4x5x_disable_wake(struct m_can_classdev *cdev)
|
||||
|
||||
static int tcan4x5x_disable_state(struct m_can_classdev *cdev)
|
||||
{
|
||||
struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
|
||||
struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
|
||||
|
||||
return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
|
||||
TCAN4X5X_DISABLE_INH_MSK, 0x01);
|
||||
@ -373,7 +379,7 @@ static int tcan4x5x_disable_state(struct m_can_classdev *cdev)
|
||||
|
||||
static int tcan4x5x_get_gpios(struct m_can_classdev *cdev)
|
||||
{
|
||||
struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
|
||||
struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev);
|
||||
int ret;
|
||||
|
||||
tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake",
|
||||
@ -427,15 +433,12 @@ static int tcan4x5x_can_probe(struct spi_device *spi)
|
||||
struct m_can_classdev *mcan_class;
|
||||
int freq, ret;
|
||||
|
||||
mcan_class = m_can_class_allocate_dev(&spi->dev);
|
||||
mcan_class = m_can_class_allocate_dev(&spi->dev,
|
||||
sizeof(struct tcan4x5x_priv));
|
||||
if (!mcan_class)
|
||||
return -ENOMEM;
|
||||
|
||||
priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
ret = -ENOMEM;
|
||||
goto out_m_can_class_free_dev;
|
||||
}
|
||||
priv = cdev_to_priv(mcan_class);
|
||||
|
||||
priv->power = devm_regulator_get_optional(&spi->dev, "vsup");
|
||||
if (PTR_ERR(priv->power) == -EPROBE_DEFER) {
|
||||
@ -445,8 +448,6 @@ static int tcan4x5x_can_probe(struct spi_device *spi)
|
||||
priv->power = NULL;
|
||||
}
|
||||
|
||||
mcan_class->device_data = priv;
|
||||
|
||||
m_can_class_get_clocks(mcan_class);
|
||||
if (IS_ERR(mcan_class->cclk)) {
|
||||
dev_err(&spi->dev, "no CAN clock source defined\n");
|
||||
@ -462,7 +463,6 @@ static int tcan4x5x_can_probe(struct spi_device *spi)
|
||||
}
|
||||
|
||||
priv->spi = spi;
|
||||
priv->mcan_dev = mcan_class;
|
||||
|
||||
mcan_class->pm_clock_support = 0;
|
||||
mcan_class->can.clock.freq = freq;
|
||||
@ -518,11 +518,11 @@ static int tcan4x5x_can_remove(struct spi_device *spi)
|
||||
{
|
||||
struct tcan4x5x_priv *priv = spi_get_drvdata(spi);
|
||||
|
||||
m_can_class_unregister(priv->mcan_dev);
|
||||
m_can_class_unregister(&priv->cdev);
|
||||
|
||||
tcan4x5x_power_enable(priv->power, 0);
|
||||
|
||||
m_can_class_free_dev(priv->mcan_dev->net);
|
||||
m_can_class_free_dev(priv->cdev.net);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user