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x86/mce/amd: Factor out logging mechanism

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Refactor the code here to setup struct mce and call mce_log() to log
the error. We're going to reuse this in a later patch as part of the
deferred error interrupt enablement.

No functional change is introduced.

Suggested-by: Borislav Petkov <bp@alien8.de>
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1430913538-1415-2-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Aravind Gopalakrishnan 2015-05-06 06:58:53 -05:00 committed by Borislav Petkov
parent 5ebe6afaf0
commit afdf344e08
1 changed files with 23 additions and 10 deletions
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33
arch/x86/kernel/cpu/mcheck/mce_amd.c
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@ -264,6 +264,27 @@ init:
}
}
static void __log_error(unsigned int bank, bool threshold_err, u64 misc)
{
struct mce m;
u64 status;
rdmsrl(MSR_IA32_MCx_STATUS(bank), status);
if (!(status & MCI_STATUS_VAL))
return;
mce_setup(&m);
m.status = status;
m.bank = bank;
if (threshold_err)
m.misc = misc;
mce_log(&m);
wrmsrl(MSR_IA32_MCx_STATUS(bank), 0);
}
/*
* APIC Interrupt Handler
*/
@ -273,12 +294,12 @@ init:
* the interrupt goes off when error_count reaches threshold_limit.
* the handler will simply log mcelog w/ software defined bank number.
*/
static void amd_threshold_interrupt(void)
{
u32 low = 0, high = 0, address = 0;
int cpu = smp_processor_id();
unsigned int bank, block;
struct mce m;
/* assume first bank caused it */
for (bank = 0; bank < mca_cfg.banks; ++bank) {
@ -321,15 +342,7 @@ static void amd_threshold_interrupt(void)
return;
log:
mce_setup(&m);
rdmsrl(MSR_IA32_MCx_STATUS(bank), m.status);
if (!(m.status & MCI_STATUS_VAL))
return;
m.misc = ((u64)high << 32) | low;
m.bank = bank;
mce_log(&m);
wrmsrl(MSR_IA32_MCx_STATUS(bank), 0);
__log_error(bank, true, ((u64)high << 32) | low);
}
/*