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arm64: tegra: Enable OPE on various platforms

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Enable OPE module usage on various Jetson platforms. This can be plugged
into an audio path using ALSA mixer controls. Add audio-graph-port binding
to use OPE device with generic audio-graph based sound card.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Sameer Pujar 2022-06-06 20:28:57 +05:30 committed by Thierry Reding
parent 4b6a1b7cbd
commit afcb41e30c
6 changed files with 340 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
View File

@ -915,6 +915,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
xbar_ope1_in_port: port@70 {
reg = <0x70>;
xbar_ope1_in_ep: endpoint {
remote-endpoint = <&ope1_cif_in_ep>;
};
};
port@71 {
reg = <0x71>;
xbar_ope1_out_ep: endpoint {
remote-endpoint = <&ope1_cif_out_ep>;
};
};
};
admaif@290f000 {
@ -1911,6 +1927,31 @@
};
};
processing-engine@2908000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
ope1_cif_in_ep: endpoint {
remote-endpoint = <&xbar_ope1_in_ep>;
};
};
ope1_out_port: port@1 {
reg = <0x1>;
ope1_cif_out_ep: endpoint {
remote-endpoint = <&xbar_ope1_out_ep>;
};
};
};
};
amixer@290bb00 {
status = "okay";
@ -2552,6 +2593,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
<&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@ -2571,6 +2613,7 @@
<&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
<&ope1_out_port>,
/* I/O */
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,

43
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
View File

@ -868,6 +868,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
xbar_ope1_in_port: port@70 {
reg = <0x70>;
xbar_ope1_in_ep: endpoint {
remote-endpoint = <&ope1_cif_in_ep>;
};
};
port@71 {
reg = <0x71>;
xbar_ope1_out_ep: endpoint {
remote-endpoint = <&ope1_cif_out_ep>;
};
};
};
admaif@290f000 {
@ -1710,6 +1726,31 @@
};
};
processing-engine@2908000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
ope1_cif_in_ep: endpoint {
remote-endpoint = <&xbar_ope1_in_ep>;
};
};
ope1_out_port: port@1 {
reg = <0x1>;
ope1_cif_out_ep: endpoint {
remote-endpoint = <&xbar_ope1_out_ep>;
};
};
};
};
amixer@290bb00 {
status = "okay";
@ -2273,6 +2314,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
<&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@ -2291,6 +2333,7 @@
<&mixer_out4_port>, <&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
<&ope1_out_port>,
/* BE I/O Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;

43
arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
View File

@ -878,6 +878,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
xbar_ope1_in_port: port@70 {
reg = <0x70>;
xbar_ope1_in_ep: endpoint {
remote-endpoint = <&ope1_cif_in_ep>;
};
};
port@71 {
reg = <0x71>;
xbar_ope1_out_ep: endpoint {
remote-endpoint = <&ope1_cif_out_ep>;
};
};
};
admaif@290f000 {
@ -1770,6 +1786,31 @@
};
};
processing-engine@2908000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
ope1_cif_in_ep: endpoint {
remote-endpoint = <&xbar_ope1_in_ep>;
};
};
ope1_out_port: port@1 {
reg = <0x1>;
ope1_cif_out_ep: endpoint {
remote-endpoint = <&xbar_ope1_out_ep>;
};
};
};
};
amixer@290bb00 {
status = "okay";
@ -2323,6 +2364,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
<&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@ -2342,6 +2384,7 @@
<&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
<&ope1_out_port>,
/* BE I/O Ports */
<&i2s3_port>, <&i2s5_port>,
<&dmic1_port>, <&dmic2_port>, <&dmic4_port>,

84
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
View File

@ -682,6 +682,56 @@
};
};
processing-engine@702d8000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
ope1_cif_in_ep: endpoint {
remote-endpoint = <&xbar_ope1_in_ep>;
};
};
ope1_out_port: port@1 {
reg = <0x1>;
ope1_cif_out_ep: endpoint {
remote-endpoint = <&xbar_ope1_out_ep>;
};
};
};
};
processing-engine@702d8400 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
ope2_cif_in_ep: endpoint {
remote-endpoint = <&xbar_ope2_in_ep>;
};
};
ope2_out_port: port@1 {
reg = <0x1>;
ope2_cif_out_ep: endpoint {
remote-endpoint = <&xbar_ope2_out_ep>;
};
};
};
};
amixer@702dbb00 {
status = "okay";
@ -1251,6 +1301,38 @@
remote-endpoint = <&mixer_out5_ep>;
};
};
xbar_ope1_in_port: port@41 {
reg = <0x41>;
xbar_ope1_in_ep: endpoint {
remote-endpoint = <&ope1_cif_in_ep>;
};
};
port@42 {
reg = <0x42>;
xbar_ope1_out_ep: endpoint {
remote-endpoint = <&ope1_cif_out_ep>;
};
};
xbar_ope2_in_port: port@43 {
reg = <0x43>;
xbar_ope2_in_ep: endpoint {
remote-endpoint = <&ope2_cif_in_ep>;
};
};
port@44 {
reg = <0x44>;
xbar_ope2_out_ep: endpoint {
remote-endpoint = <&ope2_cif_out_ep>;
};
};
};
};
};
@ -1281,6 +1363,7 @@
<&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
<&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
<&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
<&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@ -1293,6 +1376,7 @@
<&mixer_out1_port>, <&mixer_out2_port>,
<&mixer_out3_port>, <&mixer_out4_port>,
<&mixer_out5_port>,
<&ope1_out_port>, <&ope2_out_port>,
/* I/O DAP Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;

84
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
View File

@ -1074,6 +1074,56 @@
};
};
processing-engine@702d8000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
ope1_cif_in_ep: endpoint {
remote-endpoint = <&xbar_ope1_in_ep>;
};
};
ope1_out_port: port@1 {
reg = <0x1>;
ope1_cif_out_ep: endpoint {
remote-endpoint = <&xbar_ope1_out_ep>;
};
};
};
};
processing-engine@702d8400 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
ope2_cif_in_ep: endpoint {
remote-endpoint = <&xbar_ope2_in_ep>;
};
};
ope2_out_port: port@1 {
reg = <0x1>;
ope2_cif_out_ep: endpoint {
remote-endpoint = <&xbar_ope2_out_ep>;
};
};
};
};
amixer@702dbb00 {
status = "okay";
@ -1611,6 +1661,38 @@
remote-endpoint = <&mixer_out5_ep>;
};
};
xbar_ope1_in_port: port@41 {
reg = <0x41>;
xbar_ope1_in_ep: endpoint {
remote-endpoint = <&ope1_cif_in_ep>;
};
};
port@42 {
reg = <0x42>;
xbar_ope1_out_ep: endpoint {
remote-endpoint = <&ope1_cif_out_ep>;
};
};
xbar_ope2_in_port: port@43 {
reg = <0x43>;
xbar_ope2_in_ep: endpoint {
remote-endpoint = <&ope2_cif_in_ep>;
};
};
port@44 {
reg = <0x44>;
xbar_ope2_out_ep: endpoint {
remote-endpoint = <&ope2_cif_out_ep>;
};
};
};
};
};
@ -1884,6 +1966,7 @@
<&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
<&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
<&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
<&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@ -1896,6 +1979,7 @@
<&mixer_out1_port>, <&mixer_out2_port>,
<&mixer_out3_port>, <&mixer_out4_port>,
<&mixer_out5_port>,
<&ope1_out_port>, <&ope2_out_port>,
/* I/O DAP Ports */
<&i2s3_port>, <&i2s4_port>,
<&dmic1_port>, <&dmic2_port>;

43
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
View File

@ -867,6 +867,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
xbar_ope1_in_port: port@70 {
reg = <0x70>;
xbar_ope1_in_ep: endpoint {
remote-endpoint = <&ope1_cif_in_ep>;
};
};
port@71 {
reg = <0x71>;
xbar_ope1_out_ep: endpoint {
remote-endpoint = <&ope1_cif_out_ep>;
};
};
};
i2s@2901000 {
@ -1490,6 +1506,31 @@
};
};
processing-engine@2908000 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0x0>;
ope1_cif_in_ep: endpoint {
remote-endpoint = <&xbar_ope1_in_ep>;
};
};
ope1_out_port: port@1 {
reg = <0x1>;
ope1_cif_out_ep: endpoint {
remote-endpoint = <&xbar_ope1_out_ep>;
};
};
};
};
mvc@290a000 {
status = "okay";
@ -2044,6 +2085,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
<&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@ -2062,6 +2104,7 @@
<&mix_out4_port>, <&mix_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
<&ope1_out_port>,
/* BE I/O Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;