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riscv: Add tests for riscv module loading
Add test cases for the two main groups of relocations added: SUB and SET, along with uleb128. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20231101-module_relocations-v9-3-8dfa3483c400@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
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source "arch/riscv/kernel/tests/Kconfig.debug"
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@ -57,6 +57,7 @@ obj-y += stacktrace.o
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obj-y += cacheinfo.o
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obj-y += patch.o
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obj-y += probes/
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obj-y += tests/
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obj-$(CONFIG_MMU) += vdso.o vdso/
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obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o
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35
arch/riscv/kernel/tests/Kconfig.debug
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35
arch/riscv/kernel/tests/Kconfig.debug
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# SPDX-License-Identifier: GPL-2.0-only
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menu "arch/riscv/kernel Testing and Coverage"
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config AS_HAS_ULEB128
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def_bool $(as-instr,.reloc label$(comma) R_RISCV_SET_ULEB128$(comma) 127\n.reloc label$(comma) R_RISCV_SUB_ULEB128$(comma) 127\nlabel:\n.word 0)
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menuconfig RUNTIME_KERNEL_TESTING_MENU
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bool "arch/riscv/kernel runtime Testing"
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def_bool y
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help
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Enable riscv kernel runtime testing.
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if RUNTIME_KERNEL_TESTING_MENU
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config RISCV_MODULE_LINKING_KUNIT
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bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS
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depends on KUNIT
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default KUNIT_ALL_TESTS
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help
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Enable this option to test riscv module linking at boot. This will
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enable a module called "test_module_linking".
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KUnit tests run during boot and output the results to the debug log
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in TAP format (http://testanything.org/). Only useful for kernel devs
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running the KUnit test harness, and not intended for inclusion into a
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production build.
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For more information on KUnit and unit tests in general please refer
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to the KUnit documentation in Documentation/dev-tools/kunit/.
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If unsure, say N.
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endif # RUNTIME_TESTING_MENU
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endmenu # "arch/riscv/kernel runtime Testing"
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1
arch/riscv/kernel/tests/Makefile
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1
arch/riscv/kernel/tests/Makefile
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obj-$(CONFIG_RISCV_MODULE_LINKING_KUNIT) += module_test/
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15
arch/riscv/kernel/tests/module_test/Makefile
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15
arch/riscv/kernel/tests/module_test/Makefile
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obj-m += test_module_linking.o
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test_sub := test_sub6.o test_sub8.o test_sub16.o test_sub32.o test_sub64.o
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test_set := test_set6.o test_set8.o test_set16.o test_set32.o
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test_module_linking-objs += $(test_sub)
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test_module_linking-objs += $(test_set)
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ifeq ($(CONFIG_AS_HAS_ULEB128),y)
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test_module_linking-objs += test_uleb128.o
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endif
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test_module_linking-objs += test_module_linking_main.o
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@ -0,0 +1,88 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Rivos Inc.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <kunit/test.h>
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Test module linking");
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extern int test_set32(void);
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extern int test_set16(void);
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extern int test_set8(void);
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extern int test_set6(void);
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extern long test_sub64(void);
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extern int test_sub32(void);
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extern int test_sub16(void);
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extern int test_sub8(void);
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extern int test_sub6(void);
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#ifdef CONFIG_AS_HAS_ULEB128
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extern int test_uleb_basic(void);
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extern int test_uleb_large(void);
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#endif
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#define CHECK_EQ(lhs, rhs) KUNIT_ASSERT_EQ(test, lhs, rhs)
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void run_test_set(struct kunit *test);
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void run_test_sub(struct kunit *test);
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void run_test_uleb(struct kunit *test);
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void run_test_set(struct kunit *test)
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{
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int val32 = test_set32();
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int val16 = test_set16();
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int val8 = test_set8();
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int val6 = test_set6();
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CHECK_EQ(val32, 0);
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CHECK_EQ(val16, 0);
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CHECK_EQ(val8, 0);
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CHECK_EQ(val6, 0);
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}
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void run_test_sub(struct kunit *test)
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{
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int val64 = test_sub64();
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int val32 = test_sub32();
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int val16 = test_sub16();
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int val8 = test_sub8();
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int val6 = test_sub6();
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CHECK_EQ(val64, 0);
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CHECK_EQ(val32, 0);
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CHECK_EQ(val16, 0);
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CHECK_EQ(val8, 0);
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CHECK_EQ(val6, 0);
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}
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#ifdef CONFIG_AS_HAS_ULEB128
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void run_test_uleb(struct kunit *test)
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{
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int val_uleb = test_uleb_basic();
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int val_uleb2 = test_uleb_large();
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CHECK_EQ(val_uleb, 0);
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CHECK_EQ(val_uleb2, 0);
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}
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#endif
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static struct kunit_case __refdata riscv_module_linking_test_cases[] = {
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KUNIT_CASE(run_test_set),
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KUNIT_CASE(run_test_sub),
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#ifdef CONFIG_AS_HAS_ULEB128
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KUNIT_CASE(run_test_uleb),
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#endif
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{}
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};
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static struct kunit_suite riscv_module_linking_test_suite = {
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.name = "riscv_checksum",
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.test_cases = riscv_module_linking_test_cases,
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};
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kunit_test_suites(&riscv_module_linking_test_suite);
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23
arch/riscv/kernel/tests/module_test/test_set16.S
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arch/riscv/kernel/tests/module_test/test_set16.S
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Rivos Inc.
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*/
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.text
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.global test_set16
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test_set16:
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lw a0, set16
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la t0, set16
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#ifdef CONFIG_32BIT
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slli t0, t0, 16
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srli t0, t0, 16
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#else
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slli t0, t0, 48
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srli t0, t0, 48
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#endif
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sub a0, a0, t0
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ret
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.data
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set16:
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.reloc set16, R_RISCV_SET16, set16
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.word 0
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20
arch/riscv/kernel/tests/module_test/test_set32.S
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arch/riscv/kernel/tests/module_test/test_set32.S
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Rivos Inc.
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*/
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.text
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.global test_set32
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test_set32:
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lw a0, set32
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la t0, set32
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#ifndef CONFIG_32BIT
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slli t0, t0, 32
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srli t0, t0, 32
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#endif
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sub a0, a0, t0
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ret
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.data
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set32:
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.reloc set32, R_RISCV_SET32, set32
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.word 0
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arch/riscv/kernel/tests/module_test/test_set6.S
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arch/riscv/kernel/tests/module_test/test_set6.S
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Rivos Inc.
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*/
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.text
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.global test_set6
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test_set6:
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lw a0, set6
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la t0, set6
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#ifdef CONFIG_32BIT
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slli t0, t0, 26
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srli t0, t0, 26
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#else
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slli t0, t0, 58
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srli t0, t0, 58
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#endif
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sub a0, a0, t0
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ret
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.data
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set6:
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.reloc set6, R_RISCV_SET6, set6
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.word 0
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arch/riscv/kernel/tests/module_test/test_set8.S
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arch/riscv/kernel/tests/module_test/test_set8.S
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Rivos Inc.
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*/
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.text
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.global test_set8
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test_set8:
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lw a0, set8
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la t0, set8
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#ifdef CONFIG_32BIT
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slli t0, t0, 24
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srli t0, t0, 24
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#else
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slli t0, t0, 56
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srli t0, t0, 56
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#endif
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sub a0, a0, t0
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ret
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.data
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set8:
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.reloc set8, R_RISCV_SET8, set8
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.word 0
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arch/riscv/kernel/tests/module_test/test_sub16.S
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arch/riscv/kernel/tests/module_test/test_sub16.S
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Rivos Inc.
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*/
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.text
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.global test_sub16
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test_sub16:
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lh a0, sub16
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addi a0, a0, -32
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ret
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first:
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.space 32
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second:
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.data
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sub16:
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.reloc sub16, R_RISCV_ADD16, second
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.reloc sub16, R_RISCV_SUB16, first
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.half 0
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arch/riscv/kernel/tests/module_test/test_sub32.S
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arch/riscv/kernel/tests/module_test/test_sub32.S
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Rivos Inc.
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*/
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.text
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.global test_sub32
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test_sub32:
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lw a0, sub32
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addi a0, a0, -32
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ret
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first:
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.space 32
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second:
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.data
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sub32:
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.reloc sub32, R_RISCV_ADD32, second
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.reloc sub32, R_RISCV_SUB32, first
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.word 0
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arch/riscv/kernel/tests/module_test/test_sub6.S
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arch/riscv/kernel/tests/module_test/test_sub6.S
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Rivos Inc.
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*/
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.text
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.global test_sub6
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test_sub6:
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lb a0, sub6
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addi a0, a0, -32
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ret
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first:
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.space 32
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second:
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.data
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sub6:
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.reloc sub6, R_RISCV_SET6, second
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.reloc sub6, R_RISCV_SUB6, first
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.byte 0
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arch/riscv/kernel/tests/module_test/test_sub64.S
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arch/riscv/kernel/tests/module_test/test_sub64.S
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Rivos Inc.
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*/
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.text
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.global test_sub64
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test_sub64:
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#ifdef CONFIG_32BIT
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lw a0, sub64
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#else
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ld a0, sub64
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#endif
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addi a0, a0, -32
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ret
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first:
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.space 32
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second:
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.data
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sub64:
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.reloc sub64, R_RISCV_ADD64, second
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.reloc sub64, R_RISCV_SUB64, first
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.word 0
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.word 0
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arch/riscv/kernel/tests/module_test/test_sub8.S
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arch/riscv/kernel/tests/module_test/test_sub8.S
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Rivos Inc.
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*/
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.text
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.global test_sub8
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test_sub8:
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lb a0, sub8
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addi a0, a0, -32
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ret
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first:
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.space 32
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second:
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.data
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sub8:
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.reloc sub8, R_RISCV_ADD8, second
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.reloc sub8, R_RISCV_SUB8, first
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.byte 0
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arch/riscv/kernel/tests/module_test/test_uleb128.S
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arch/riscv/kernel/tests/module_test/test_uleb128.S
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Rivos Inc.
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*/
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.text
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.global test_uleb_basic
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test_uleb_basic:
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ld a0, second
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addi a0, a0, -127
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ret
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.global test_uleb_large
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test_uleb_large:
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ld a0, fourth
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addi a0, a0, -0x07e8
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ret
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.data
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first:
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.space 127
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second:
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.reloc second, R_RISCV_SET_ULEB128, second
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.reloc second, R_RISCV_SUB_ULEB128, first
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.dword 0
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third:
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.space 1000
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fourth:
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.reloc fourth, R_RISCV_SET_ULEB128, fourth
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.reloc fourth, R_RISCV_SUB_ULEB128, third
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.dword 0
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