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dt-bindings: clk: emev2: Convert to json-schema
Convert the Renesas EMMA Mobile EV2 System Management Unit (SMU) Device Tree binding documentation to json-schema. Drop the separate provider examples, as they mostly duplicate the global example. Drop the consumer example, as it doesn't belong here. Update the global example to match reality. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/526e1a412145a0fcc5a43dcf6de5c580301017cb.1620119350.git.geert+renesas@glider.be Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Geert Uytterhoeven
Rob Herring
parent
4d92239b65
commit
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Device tree Clock bindings for Renesas EMMA Mobile EV2
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This binding uses the common clock binding.
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* SMU
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System Management Unit described in user's manual R19UH0037EJ1000_SMU.
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This is not a clock provider, but clocks under SMU depend on it.
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Required properties:
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- compatible: Should be "renesas,emev2-smu"
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- reg: Address and Size of SMU registers
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* SMU_CLKDIV
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Function block with an input mux and a divider, which corresponds to
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"Serial clock generator" in fig."Clock System Overview" of the manual,
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and "xxx frequency division setting register" (XXXCLKDIV) registers.
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This makes internal (neither input nor output) clock that is provided
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to input of xxxGCLK block.
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Required properties:
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- compatible: Should be "renesas,emev2-smu-clkdiv"
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- reg: Byte offset from SMU base and Bit position in the register
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- clocks: Parent clocks. Input clocks as described in clock-bindings.txt
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- #clock-cells: Should be <0>
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* SMU_GCLK
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Clock gating node shown as "Clock stop processing block" in the
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fig."Clock System Overview" of the manual.
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Registers are "xxx clock gate control register" (XXXGCLKCTRL).
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Required properties:
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- compatible: Should be "renesas,emev2-smu-gclk"
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- reg: Byte offset from SMU base and Bit position in the register
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- clocks: Input clock as described in clock-bindings.txt
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- #clock-cells: Should be <0>
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Example of provider:
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usia_u0_sclkdiv: usia_u0_sclkdiv {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x610 0>;
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clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
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#clock-cells = <0>;
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};
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usia_u0_sclk: usia_u0_sclk {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x4a0 1>;
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clocks = <&usia_u0_sclkdiv>;
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#clock-cells = <0>;
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};
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Example of consumer:
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serial@e1020000 {
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compatible = "renesas,em-uart";
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reg = <0xe1020000 0x38>;
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interrupts = <0 8 0>;
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clocks = <&usia_u0_sclk>;
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clock-names = "sclk";
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};
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Example of clock-tree description:
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This describes a clock path in the clock tree
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c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
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smu@e0110000 {
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compatible = "renesas,emev2-smu";
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reg = <0xe0110000 0x10000>;
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#address-cells = <2>;
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#size-cells = <0>;
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c32ki: c32ki {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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pll3_fo: pll3_fo {
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compatible = "fixed-factor-clock";
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clocks = <&c32ki>;
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clock-div = <1>;
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clock-mult = <7000>;
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#clock-cells = <0>;
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};
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usia_u0_sclkdiv: usia_u0_sclkdiv {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x610 0>;
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clocks = <&pll3_fo>;
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#clock-cells = <0>;
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};
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usia_u0_sclk: usia_u0_sclk {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x4a0 1>;
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clocks = <&usia_u0_sclkdiv>;
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#clock-cells = <0>;
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};
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};
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140
Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml
Normal file
140
Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml
Normal file
@ -0,0 +1,140 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas EMMA Mobile EV2 System Management Unit
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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- Magnus Damm <magnus.damm@gmail.com>
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description: |
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The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
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This is not a clock provider, but clocks under SMU depend on it.
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properties:
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compatible:
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const: renesas,emev2-smu
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reg:
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maxItems: 1
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'#address-cells':
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const: 2
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'#size-cells':
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const: 0
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required:
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- compatible
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- reg
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- '#address-cells'
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- '#size-cells'
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patternProperties:
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".*sclkdiv@.*":
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type: object
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description: |
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Function block with an input mux and a divider, which corresponds to
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"Serial clock generator" in fig. "Clock System Overview" of the manual,
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and "xxx frequency division setting register" (XXXCLKDIV) registers.
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This makes internal (neither input nor output) clock that is provided
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to input of xxxGCLK block.
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properties:
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compatible:
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const: renesas,emev2-smu-clkdiv
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reg:
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maxItems: 1
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description:
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Byte offset from SMU base and Bit position in the register.
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clocks:
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minItems: 1
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maxItems: 4
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'#clock-cells':
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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".*sclk@.*":
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type: object
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description: |
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Clock gating node shown as "Clock stop processing block" in the
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fig. "Clock System Overview" of the manual.
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Registers are "xxx clock gate control register" (XXXGCLKCTRL).
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properties:
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compatible:
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const: renesas,emev2-smu-gclk
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reg:
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maxItems: 1
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description:
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Byte offset from SMU base and Bit position in the register.
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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additionalProperties: true
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examples:
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- |
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// Example of clock-tree description:
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//
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// This describes a clock path in the clock tree
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// c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
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clocks@e0110000 {
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compatible = "renesas,emev2-smu";
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reg = <0xe0110000 0x10000>;
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#address-cells = <2>;
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#size-cells = <0>;
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c32ki: c32ki {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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pll3_fo: pll3_fo {
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compatible = "fixed-factor-clock";
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clocks = <&c32ki>;
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clock-div = <1>;
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clock-mult = <7000>;
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#clock-cells = <0>;
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};
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usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
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compatible = "renesas,emev2-smu-clkdiv";
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reg = <0x610 0>;
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clocks = <&pll3_fo>;
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#clock-cells = <0>;
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};
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usia_u0_sclk: usia_u0_sclk@4a0,1 {
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compatible = "renesas,emev2-smu-gclk";
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reg = <0x4a0 1>;
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clocks = <&usia_u0_sclkdiv>;
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#clock-cells = <0>;
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};
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};
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