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csky: Optimize arch_sync_dma_for_cpu/device with dma_inv_range
DMA_FROM_DEVICE only need to read dma data of memory into CPU cache, so there is no need to clear cache before. Also clear + inv for DMA_FROM_DEVICE won't cause problem, because the memory range for dma won't be touched by software during dma working. Changes for V2: - Remove clr cache and ignore the DMA_TO_DEVICE in _for_cpu. - Change inv to wbinv cache with DMA_FROM_DEVICE in _for_device. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
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@ -24,6 +24,7 @@ void cache_wbinv_range(unsigned long start, unsigned long end);
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void cache_wbinv_all(void);
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void dma_wbinv_range(unsigned long start, unsigned long end);
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void dma_inv_range(unsigned long start, unsigned long end);
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void dma_wb_range(unsigned long start, unsigned long end);
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#endif
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@ -120,7 +120,12 @@ void dma_wbinv_range(unsigned long start, unsigned long end)
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cache_op_range(start, end, DATA_CACHE|CACHE_CLR|CACHE_INV, 1);
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}
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void dma_inv_range(unsigned long start, unsigned long end)
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{
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cache_op_range(start, end, DATA_CACHE|CACHE_CLR|CACHE_INV, 1);
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}
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void dma_wb_range(unsigned long start, unsigned long end)
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{
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cache_op_range(start, end, DATA_CACHE|CACHE_INV, 1);
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cache_op_range(start, end, DATA_CACHE|CACHE_CLR|CACHE_INV, 1);
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}
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@ -69,11 +69,20 @@ void dma_wbinv_range(unsigned long start, unsigned long end)
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sync_is();
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}
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void dma_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.iva %0\n"::"r"(i):"memory");
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sync_is();
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}
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void dma_wb_range(unsigned long start, unsigned long end)
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{
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unsigned long i = start & ~(L1_CACHE_BYTES - 1);
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for (; i < end; i += L1_CACHE_BYTES)
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asm volatile("dcache.civa %0\n"::"r"(i):"memory");
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asm volatile("dcache.cva %0\n"::"r"(i):"memory");
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sync_is();
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}
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@ -85,11 +85,10 @@ void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
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{
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switch (dir) {
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case DMA_TO_DEVICE:
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cache_op(paddr, size, dma_wb_range);
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break;
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return;
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case DMA_FROM_DEVICE:
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case DMA_BIDIRECTIONAL:
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cache_op(paddr, size, dma_wbinv_range);
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cache_op(paddr, size, dma_inv_range);
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break;
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default:
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BUG();
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