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arm64: docs: cpu-feature-registers: Document ID_AA64PFR1_EL1
Commit d71be2b6c0
("arm64: cpufeature: Detect SSBS and advertise
to userspace") exposes ID_AA64PFR1_EL1 to userspace, but didn't
update the documentation to match.
Add it.
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
parent
7db3e57e6a
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@ -168,8 +168,15 @@ infrastructure:
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+------------------------------+---------+---------+
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3) MIDR_EL1 - Main ID Register
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3) ID_AA64PFR1_EL1 - Processor Feature Register 1
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| SSBS | [7-4] | y |
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+------------------------------+---------+---------+
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4) MIDR_EL1 - Main ID Register
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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@ -188,7 +195,7 @@ infrastructure:
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as available on the CPU where it is fetched and is not a system
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wide safe value.
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4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
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5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
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+------------------------------+---------+---------+
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| Name | bits | visible |
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@ -210,7 +217,7 @@ infrastructure:
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| DPB | [3-0] | y |
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+------------------------------+---------+---------+
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5) ID_AA64MMFR2_EL1 - Memory model feature register 2
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6) ID_AA64MMFR2_EL1 - Memory model feature register 2
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+------------------------------+---------+---------+
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| Name | bits | visible |
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@ -218,7 +225,7 @@ infrastructure:
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| AT | [35-32] | y |
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+------------------------------+---------+---------+
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6) ID_AA64ZFR0_EL1 - SVE feature ID register 0
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7) ID_AA64ZFR0_EL1 - SVE feature ID register 0
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+------------------------------+---------+---------+
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| Name | bits | visible |
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