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drm/i915: Assign a new pll from the crtc check function, v2.
It saves another loop over all crtc's in the state, and computing clock is more of a per crtc thing. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Tested-by(IVB): Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -11719,11 +11719,12 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc_state *pipe_config =
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to_intel_crtc_state(crtc_state);
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struct drm_atomic_state *state = crtc_state->state;
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int idx = crtc->base.id;
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int ret, idx = crtc->base.id;
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bool mode_changed = needs_modeset(crtc_state);
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if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
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@ -11735,6 +11736,15 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
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"[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
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idx, crtc->state->active, intel_crtc->active);
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if (mode_changed && crtc_state->enable &&
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dev_priv->display.crtc_compute_clock &&
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!WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
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ret = dev_priv->display.crtc_compute_clock(intel_crtc,
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pipe_config);
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if (ret)
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return ret;
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}
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return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
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}
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@ -12789,53 +12799,37 @@ static void update_scanline_offset(struct intel_crtc *crtc)
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crtc->scanline_offset = 1;
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}
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static int intel_modeset_setup_plls(struct drm_atomic_state *state)
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static void intel_modeset_clear_plls(struct drm_atomic_state *state)
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{
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struct drm_device *dev = state->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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unsigned clear_pipes = 0;
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struct intel_shared_dpll_config *shared_dpll = NULL;
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struct intel_crtc *intel_crtc;
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struct intel_crtc_state *intel_crtc_state;
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struct drm_crtc *crtc;
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struct drm_crtc_state *crtc_state;
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int ret = 0;
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int i;
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if (!dev_priv->display.crtc_compute_clock)
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return 0;
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return;
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for_each_crtc_in_state(state, crtc, crtc_state, i) {
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int dpll;
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intel_crtc = to_intel_crtc(crtc);
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intel_crtc_state = to_intel_crtc_state(crtc_state);
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dpll = intel_crtc_state->shared_dpll;
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if (needs_modeset(crtc_state)) {
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clear_pipes |= 1 << intel_crtc->pipe;
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intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
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}
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}
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if (clear_pipes) {
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struct intel_shared_dpll_config *shared_dpll =
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intel_atomic_get_shared_dpll_state(state);
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for (i = 0; i < dev_priv->num_shared_dpll; i++)
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shared_dpll[i].crtc_mask &= ~clear_pipes;
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}
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for_each_crtc_in_state(state, crtc, crtc_state, i) {
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if (!needs_modeset(crtc_state) || !crtc_state->enable)
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if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
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continue;
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intel_crtc = to_intel_crtc(crtc);
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intel_crtc_state = to_intel_crtc_state(crtc_state);
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intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
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ret = dev_priv->display.crtc_compute_clock(intel_crtc,
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intel_crtc_state);
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if (ret)
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return ret;
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if (!shared_dpll)
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shared_dpll = intel_atomic_get_shared_dpll_state(state);
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shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
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}
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return ret;
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}
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/*
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@ -12931,14 +12925,12 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
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return ret;
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}
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ret = intel_modeset_setup_plls(state);
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if (ret)
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return ret;
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intel_modeset_clear_plls(state);
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if (IS_HASWELL(dev))
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ret = haswell_mode_set_planes_workaround(state);
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return haswell_mode_set_planes_workaround(state);
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return ret;
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return 0;
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}
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static int
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