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clk: renesas: rcar-gen4: Add support for FRQCRC1

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R-Car V4H and V4M have a second Frequency Control Register C.
Add support for this by treating bit field offsets beyond 31 as
referring to the second register.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f64d5573a92a18505619ff0ff808d50cfc2bde55.1706194617.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2024-01-25 16:34:35 +01:00
parent 775e7c4d36
commit ad3393fefd
1 changed files with 8 additions and 2 deletions
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10
drivers/clk/renesas/rcar-gen4-cpg.c
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@ -179,7 +179,8 @@ static struct clk * __init cpg_pll_clk_register(const char *name,
*/
#define CPG_FRQCRB 0x00000804
#define CPG_FRQCRB_KICK BIT(31)
#define CPG_FRQCRC 0x00000808
#define CPG_FRQCRC0 0x00000808
#define CPG_FRQCRC1 0x000008e0
struct cpg_z_clk {
struct clk_hw hw;
@ -304,7 +305,12 @@ static struct clk * __init cpg_z_clk_register(const char *name,
init.parent_names = &parent_name;
init.num_parents = 1;
zclk->reg = reg + CPG_FRQCRC;
if (offset < 32) {
zclk->reg = reg + CPG_FRQCRC0;
} else {
zclk->reg = reg + CPG_FRQCRC1;
offset -= 32;
}
zclk->kick_reg = reg + CPG_FRQCRB;
zclk->hw.init = &init;
zclk->mask = GENMASK(offset + 4, offset);