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Merge branch 'for-upstream/juno-dts' of git://linux-arm.org/linux-ld into next/dt
Merge "Documentation: bindings: Add DT bindings for ARM Juno boards" from Liviu Dudau: * 'for-upstream/juno-dts' of git://linux-arm.org/linux-ld: Documentation: bindings: Add DT bindings for ARM Juno boards. arm64: Add DT support for Juno r1 board. arm64: Juno: Add GICv2m support in device tree. arm64: Juno: Add memory mapped timer node arm64: Juno: Split juno.dts into juno-base.dtsi and juno.dts. arm64: Juno: Fix the GIC node address label and the frequency of FAXI clock.
This commit is contained in:
Arnd Bergmann
commit
ad01f311af
@ -157,3 +157,69 @@ Example:
|
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|
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};
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||||
};
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ARM Versatile Express Boards
|
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-----------------------------
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For details on the device tree bindings for ARM Versatile Express boards
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please consult the vexpress.txt file in the same directory as this file.
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|
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ARM Juno Boards
|
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----------------
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The Juno boards are targeting development for AArch64 systems. The first
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iteration, Juno r0, is a vehicle for evaluating big.LITTLE on AArch64,
|
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with the second iteration, Juno r1, mainly aimed at development of PCIe
|
||||
based systems. Juno r1 also has support for AXI masters placed on the TLX
|
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connectors to join the coherency domain.
|
||||
|
||||
Juno boards are described in a similar way to ARM Versatile Express boards,
|
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with the motherboard part of the hardware being described in a separate file
|
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to highlight the fact that is part of the support infrastructure for the SoC.
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Juno device tree bindings also share the Versatile Express bindings as
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described under the RS1 memory mapping.
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|
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Required properties (in root node):
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compatible = "arm,juno"; /* For Juno r0 board */
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compatible = "arm,juno-r1"; /* For Juno r1 board */
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Required nodes:
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The description for the board must include:
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- a "psci" node describing the boot method used for the secondary CPUs.
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A detailed description of the bindings used for "psci" nodes is present
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in the psci.txt file.
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- a "cpus" node describing the available cores and their associated
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"enable-method"s. For more details see cpus.txt file.
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Example:
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/dts-v1/;
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/ {
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model = "ARM Juno development board (r0)";
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compatible = "arm,juno", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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A57_0: cpu@0 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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};
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.....
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A53_0: cpu@100 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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};
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|
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.....
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||||
};
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|
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};
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@ -1,5 +1,5 @@
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dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
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always := $(dtb-y)
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154
arch/arm64/boot/dts/arm/juno-base.dtsi
Normal file
154
arch/arm64/boot/dts/arm/juno-base.dtsi
Normal file
@ -0,0 +1,154 @@
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/*
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* Devices shared by all Juno boards
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*/
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memtimer: timer@2a810000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x2a810000 0x0 0x10000>;
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clock-frequency = <50000000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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frame@2a830000 {
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frame-number = <1>;
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interrupts = <0 60 4>;
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reg = <0x0 0x2a830000 0x0 0x10000>;
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};
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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reg = <0x0 0x2c010000 0 0x1000>,
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<0x0 0x2c02f000 0 0x2000>,
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<0x0 0x2c04f000 0 0x2000>,
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<0x0 0x2c06f000 0 0x2000>;
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#address-cells = <2>;
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#interrupt-cells = <3>;
|
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#size-cells = <2>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
|
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ranges = <0 0 0 0x2c1c0000 0 0x40000>;
|
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v2m_0: v2m@0 {
|
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compatible = "arm,gic-v2m-frame";
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msi-controller;
|
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reg = <0 0 0 0x1000>;
|
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};
|
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};
|
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|
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timer {
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compatible = "arm,armv8-timer";
|
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
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};
|
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|
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/include/ "juno-clocks.dtsi"
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|
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dma@7ff00000 {
|
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0x7ff00000 0 0x1000>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_faxiclk>;
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clock-names = "apb_pclk";
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};
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soc_uart0: uart@7ff80000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x7ff80000 0x0 0x1000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
|
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clock-names = "uartclk", "apb_pclk";
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};
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|
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i2c@7ffa0000 {
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compatible = "snps,designware-i2c";
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reg = <0x0 0x7ffa0000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
|
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i2c-sda-hold-time-ns = <500>;
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clocks = <&soc_smc50mhz>;
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|
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dvi0: dvi-transmitter@70 {
|
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compatible = "nxp,tda998x";
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reg = <0x70>;
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};
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dvi1: dvi-transmitter@71 {
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compatible = "nxp,tda998x";
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reg = <0x71>;
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};
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};
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|
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ohci@7ffb0000 {
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compatible = "generic-ohci";
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reg = <0x0 0x7ffb0000 0x0 0x10000>;
|
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_usb48mhz>;
|
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};
|
||||
|
||||
ehci@7ffc0000 {
|
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compatible = "generic-ehci";
|
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reg = <0x0 0x7ffc0000 0x0 0x10000>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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||||
clocks = <&soc_usb48mhz>;
|
||||
};
|
||||
|
||||
memory-controller@7ffd0000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0 0x7ffd0000 0 0x1000>;
|
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
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device_type = "memory";
|
||||
/* last 16MB of the first memory area is reserved for secure world use by firmware */
|
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reg = <0x00000000 0x80000000 0x0 0x7f000000>,
|
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<0x00000008 0x80000000 0x1 0x80000000>;
|
||||
};
|
||||
|
||||
smb {
|
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compatible = "simple-bus";
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#address-cells = <2>;
|
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#size-cells = <1>;
|
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ranges = <0 0 0 0x08000000 0x04000000>,
|
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<1 0 0 0x14000000 0x04000000>,
|
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<2 0 0 0x18000000 0x04000000>,
|
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<3 0 0 0x1c000000 0x04000000>,
|
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<4 0 0 0x0c000000 0x04000000>,
|
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<5 0 0 0x10000000 0x04000000>;
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|
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#interrupt-cells = <1>;
|
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interrupt-map-mask = <0 0 15>;
|
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interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
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/include/ "juno-motherboard.dtsi"
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};
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@ -36,9 +36,9 @@
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clock-output-names = "apb_pclk";
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};
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soc_faxiclk: refclk533mhz {
|
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soc_faxiclk: refclk400mhz {
|
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compatible = "fixed-clock";
|
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#clock-cells = <0>;
|
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clock-frequency = <533000000>;
|
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clock-frequency = <400000000>;
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clock-output-names = "faxi_clk";
|
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};
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116
arch/arm64/boot/dts/arm/juno-r1.dts
Normal file
116
arch/arm64/boot/dts/arm/juno-r1.dts
Normal file
@ -0,0 +1,116 @@
|
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/*
|
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* ARM Ltd. Juno Platform
|
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*
|
||||
* Copyright (c) 2015 ARM Ltd.
|
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*
|
||||
* This file is licensed under a dual GPLv2 or BSD license.
|
||||
*/
|
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|
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/dts-v1/;
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|
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#include <dt-bindings/interrupt-controller/arm-gic.h>
|
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|
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/ {
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model = "ARM Juno development board (r1)";
|
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compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
|
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interrupt-parent = <&gic>;
|
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#address-cells = <2>;
|
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#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
serial0 = &soc_uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
};
|
||||
|
||||
A57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x0 0x1>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A57_L2>;
|
||||
};
|
||||
|
||||
A53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x102>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x0 0x103>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
};
|
||||
|
||||
A57_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
|
||||
A53_L2: l2-cache1 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&A57_0>,
|
||||
<&A57_1>,
|
||||
<&A53_0>,
|
||||
<&A53_1>,
|
||||
<&A53_2>,
|
||||
<&A53_3>;
|
||||
};
|
||||
|
||||
#include "juno-base.dtsi"
|
||||
|
||||
};
|
||||
|
||||
&memtimer {
|
||||
status = "okay";
|
||||
};
|
||||
@ -91,33 +91,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
/* last 16MB of the first memory area is reserved for secure world use by firmware */
|
||||
reg = <0x00000000 0x80000000 0x0 0x7f000000>,
|
||||
<0x00000008 0x80000000 0x1 0x80000000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,gic-400", "arm,cortex-a15-gic";
|
||||
reg = <0x0 0x2c010000 0 0x1000>,
|
||||
<0x0 0x2c02f000 0 0x2000>,
|
||||
<0x0 0x2c04f000 0 0x2000>,
|
||||
<0x0 0x2c06f000 0 0x2000>;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@ -134,105 +107,5 @@
|
||||
<&A53_3>;
|
||||
};
|
||||
|
||||
/include/ "juno-clocks.dtsi"
|
||||
|
||||
dma@7ff00000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0x7ff00000 0 0x1000>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_faxiclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
soc_uart0: uart@7ff80000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x0 0x7ff80000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
i2c@7ffa0000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x7ffa0000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <400000>;
|
||||
i2c-sda-hold-time-ns = <500>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
|
||||
dvi0: dvi-transmitter@70 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x70>;
|
||||
};
|
||||
|
||||
dvi1: dvi-transmitter@71 {
|
||||
compatible = "nxp,tda998x";
|
||||
reg = <0x71>;
|
||||
};
|
||||
};
|
||||
|
||||
ohci@7ffb0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0x7ffb0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_usb48mhz>;
|
||||
};
|
||||
|
||||
ehci@7ffc0000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0x7ffc0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_usb48mhz>;
|
||||
};
|
||||
|
||||
memory-controller@7ffd0000 {
|
||||
compatible = "arm,pl354", "arm,primecell";
|
||||
reg = <0 0x7ffd0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
smb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 15>;
|
||||
interrupt-map = <0 0 0 &gic 0 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic 0 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic 0 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic 0 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic 0 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic 0 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic 0 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic 0 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic 0 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic 0 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic 0 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic 0 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
/include/ "juno-motherboard.dtsi"
|
||||
};
|
||||
#include "juno-base.dtsi"
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user