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PCI: tegra: Use lower-case hex consistently for register definitions

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Most of the register definitions use lowercase hexadecimal values, with a
few exceptions using uppercase.  Convert the latter to be more in line with
the former.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Thierry Reding 2016-07-25 16:02:05 -05:00 committed by Bjorn Helgaas
parent af8c34ce6a
commit acb341e96f
1 changed files with 11 additions and 11 deletions
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22
drivers/pci/host/pci-tegra.c
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@ -183,26 +183,26 @@
#define AFI_PEXBIAS_CTRL_0 0x168 #define AFI_PEXBIAS_CTRL_0 0x168
#define RP_VEND_XP 0x00000F00 #define RP_VEND_XP 0x00000f00
#define RP_VEND_XP_DL_UP (1 << 30) #define RP_VEND_XP_DL_UP (1 << 30)
#define RP_PRIV_MISC 0x00000FE0 #define RP_PRIV_MISC 0x00000fe0
#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)
#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)
#define RP_LINK_CONTROL_STATUS 0x00000090 #define RP_LINK_CONTROL_STATUS 0x00000090
#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
#define PADS_CTL_SEL 0x0000009C #define PADS_CTL_SEL 0x0000009c
#define PADS_CTL 0x000000A0 #define PADS_CTL 0x000000a0
#define PADS_CTL_IDDQ_1L (1 << 0) #define PADS_CTL_IDDQ_1L (1 << 0)
#define PADS_CTL_TX_DATA_EN_1L (1 << 6) #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
#define PADS_CTL_RX_DATA_EN_1L (1 << 10) #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
#define PADS_PLL_CTL_TEGRA20 0x000000B8 #define PADS_PLL_CTL_TEGRA20 0x000000b8
#define PADS_PLL_CTL_TEGRA30 0x000000B4 #define PADS_PLL_CTL_TEGRA30 0x000000b4
#define PADS_PLL_CTL_RST_B4SM (1 << 1) #define PADS_PLL_CTL_RST_B4SM (1 << 1)
#define PADS_PLL_CTL_LOCKDET (1 << 8) #define PADS_PLL_CTL_LOCKDET (1 << 8)
#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
@ -214,9 +214,9 @@
#define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
#define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22) #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22)
#define PADS_REFCLK_CFG0 0x000000C8 #define PADS_REFCLK_CFG0 0x000000c8
#define PADS_REFCLK_CFG1 0x000000CC #define PADS_REFCLK_CFG1 0x000000cc
#define PADS_REFCLK_BIAS 0x000000D0 #define PADS_REFCLK_BIAS 0x000000d0
/* /*
* Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit