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intel_idle: add Grand Ridge SoC support
Add Intel Grand Ridge SoC C-states, which are C1, C1E, and C6S. The Grand Ridge SoC is built with modules, each module includes 4 cores (Crestmont microarchitecture). There is one L2 cache per module, shared between the 4 cores. There is no core C6 state, but there is C6S state, which has module scope: when all 4 cores request C6S, the entire module (4 cores + L2 cache) enters the low power state. Package C6 is not supported by Grand Ridge SoC. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -1271,6 +1271,35 @@ static struct cpuidle_state snr_cstates[] __initdata = {
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.enter = NULL }
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};
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static struct cpuidle_state grr_cstates[] __initdata = {
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{
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.name = "C1",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C1E",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
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.exit_latency = 2,
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.target_residency = 10,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.name = "C6S",
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.desc = "MWAIT 0x22",
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.flags = MWAIT2flg(0x22) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 140,
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.target_residency = 500,
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.enter = &intel_idle,
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.enter_s2idle = intel_idle_s2idle, },
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{
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.enter = NULL }
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};
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static const struct idle_cpu idle_cpu_nehalem __initconst = {
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.state_table = nehalem_cstates,
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.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
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@ -1420,6 +1449,12 @@ static const struct idle_cpu idle_cpu_snr __initconst = {
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.use_acpi = true,
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};
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static const struct idle_cpu idle_cpu_grr __initconst = {
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.state_table = grr_cstates,
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.disable_promotion_to_c1e = true,
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.use_acpi = true,
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};
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static const struct x86_cpu_id intel_idle_ids[] __initconst = {
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X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &idle_cpu_nhx),
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X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &idle_cpu_nehalem),
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@ -1466,6 +1501,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &idle_cpu_bxt),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &idle_cpu_dnv),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &idle_cpu_snr),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_CRESTMONT, &idle_cpu_grr),
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{}
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};
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