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drm-fixes for 6.3-rc6
Mostly i915 fixes: dp mst for compression/dsc, perf ioctl uaf, ctx rpm accounting, gt reset vs huc loading. And a few individual driver fixes: ivpu dma fence&suspend, panfrost mmap, nouveau color depth -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEb4nG6jLu8Y5XI+PfTA9ye/CYqnEFAmQu+F4ACgkQTA9ye/CY qnFKQQ//dnQbe15pnOtoIdgen5+OC8kRe+N3g+CbMY7Yo7YTq3PIRgwlnInOjysl H1pFtGn8VOBUzqerPLUWRv0AKi/iLmjUZJ8QSAbW1sMwJZUQJ4KLoAafc8yO/weH jRcxU+0soctBqJ4G2sT2EAeXMgtk9dICUScC0CpxSwmGkHD8bF/U6Xln4O2xb4HS hI47AjeWcev/A2Fa2PsU3DtbGLqy37IrPPs0gMPlqjLQ84MN9+Op0OEK5fAfozq7 mX3zya7eLGE8jCYQDgbZ2ePuSh+HeF4e09l3Ax4bFVDp8ZtFM0kpgezSGQ2lTNdV yFNoEbgpYG92Lf40NiTJ/7RgqH731AXAdTkFLjvl+62OCmC3OEaBjIiwaZed9Gf2 Ec/diNhz0IEf7Ud9d2Q5z9/7Zk14zp/RwDlUlFx+RZBM3GLJ1zK3hj6InTK72YAF umHfXtXidiak1KB/Rx3GIb9Ii/EqmRgjPoW4oWY1+mtsGvNufLC7HoYIzHdYuzjH mip1j/RAJ6hwnI4EzkTFq9xFVVdqGOi7zIB6Vu4TzCjZt8JLOgIRLMbHi7YYwq0v Vc0D+FVE0I6EfOiP48kT2pnpzOdcVMdPHaNkAqPYjponeQm1bSISfbOVBA7+9YpW OtQA96K4yL22WebAyQkuOns1tD8DUEC6ofDxsg4pUPlOpQyAgSw= =kCTh -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2023-04-06' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Daniel Vetter: "Mostly i915 fixes: dp mst for compression/dsc, perf ioctl uaf, ctx rpm accounting, gt reset vs huc loading. And a few individual driver fixes: ivpu dma fence&suspend, panfrost mmap, nouveau color depth" * tag 'drm-fixes-2023-04-06' of git://anongit.freedesktop.org/drm/drm: accel/ivpu: Fix S3 system suspend when not idle accel/ivpu: Add dma fence to command buffers only drm/i915: Fix context runtime accounting drm/i915: fix race condition UAF in i915_perf_add_config_ioctl drm/i915: Use compressed bpp when calculating m/n value for DP MST DSC drm/i915/huc: Cancel HuC delayed load timer on reset. drm/i915/ttm: fix sparse warning drm/panfrost: Fix the panfrost_mmu_map_fault_addr() error path drm/nouveau/disp: Support more modes by checking with lower bpc
This commit is contained in:
commit
ac6c043391
@ -461,26 +461,22 @@ ivpu_job_prepare_bos_for_submit(struct drm_file *file, struct ivpu_job *job, u32
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job->cmd_buf_vpu_addr = bo->vpu_addr + commands_offset;
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ret = drm_gem_lock_reservations((struct drm_gem_object **)job->bos, buf_count,
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&acquire_ctx);
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ret = drm_gem_lock_reservations((struct drm_gem_object **)job->bos, 1, &acquire_ctx);
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if (ret) {
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ivpu_warn(vdev, "Failed to lock reservations: %d\n", ret);
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return ret;
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}
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for (i = 0; i < buf_count; i++) {
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ret = dma_resv_reserve_fences(job->bos[i]->base.resv, 1);
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if (ret) {
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ivpu_warn(vdev, "Failed to reserve fences: %d\n", ret);
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goto unlock_reservations;
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}
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ret = dma_resv_reserve_fences(bo->base.resv, 1);
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if (ret) {
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ivpu_warn(vdev, "Failed to reserve fences: %d\n", ret);
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goto unlock_reservations;
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}
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for (i = 0; i < buf_count; i++)
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dma_resv_add_fence(job->bos[i]->base.resv, job->done_fence, DMA_RESV_USAGE_WRITE);
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dma_resv_add_fence(bo->base.resv, job->done_fence, DMA_RESV_USAGE_WRITE);
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unlock_reservations:
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drm_gem_unlock_reservations((struct drm_gem_object **)job->bos, buf_count, &acquire_ctx);
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drm_gem_unlock_reservations((struct drm_gem_object **)job->bos, 1, &acquire_ctx);
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wmb(); /* Flush write combining buffers */
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@ -140,32 +140,28 @@ int ivpu_pm_suspend_cb(struct device *dev)
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{
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struct drm_device *drm = dev_get_drvdata(dev);
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struct ivpu_device *vdev = to_ivpu_device(drm);
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int ret;
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unsigned long timeout;
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ivpu_dbg(vdev, PM, "Suspend..\n");
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ret = ivpu_suspend(vdev);
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if (ret && vdev->pm->suspend_reschedule_counter) {
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ivpu_dbg(vdev, PM, "Failed to enter idle, rescheduling suspend, retries left %d\n",
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vdev->pm->suspend_reschedule_counter);
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pm_schedule_suspend(dev, vdev->timeout.reschedule_suspend);
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vdev->pm->suspend_reschedule_counter--;
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return -EBUSY;
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} else if (!vdev->pm->suspend_reschedule_counter) {
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ivpu_warn(vdev, "Failed to enter idle, force suspend\n");
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ivpu_pm_prepare_cold_boot(vdev);
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} else {
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ivpu_pm_prepare_warm_boot(vdev);
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timeout = jiffies + msecs_to_jiffies(vdev->timeout.tdr);
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while (!ivpu_hw_is_idle(vdev)) {
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cond_resched();
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if (time_after_eq(jiffies, timeout)) {
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ivpu_err(vdev, "Failed to enter idle on system suspend\n");
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return -EBUSY;
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}
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}
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vdev->pm->suspend_reschedule_counter = PM_RESCHEDULE_LIMIT;
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ivpu_suspend(vdev);
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ivpu_pm_prepare_warm_boot(vdev);
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pci_save_state(to_pci_dev(dev));
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pci_set_power_state(to_pci_dev(dev), PCI_D3hot);
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ivpu_dbg(vdev, PM, "Suspend done.\n");
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return ret;
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return 0;
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}
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int ivpu_pm_resume_cb(struct device *dev)
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@ -232,7 +232,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
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return slots;
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}
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intel_link_compute_m_n(crtc_state->pipe_bpp,
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intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
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crtc_state->lane_count,
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adjusted_mode->crtc_clock,
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crtc_state->port_clock,
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@ -1067,11 +1067,12 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
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.interruptible = true,
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.no_wait_gpu = true, /* should be idle already */
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};
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int err;
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GEM_BUG_ON(!bo->ttm || !(bo->ttm->page_flags & TTM_TT_FLAG_SWAPPED));
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ret = ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
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if (ret) {
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err = ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
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if (err) {
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dma_resv_unlock(bo->base.resv);
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return VM_FAULT_SIGBUS;
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}
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@ -2018,6 +2018,8 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
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* inspecting the queue to see if we need to resumbit.
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*/
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if (*prev != *execlists->active) { /* elide lite-restores */
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struct intel_context *prev_ce = NULL, *active_ce = NULL;
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/*
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* Note the inherent discrepancy between the HW runtime,
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* recorded as part of the context switch, and the CPU
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@ -2029,9 +2031,15 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
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* and correct overselves later when updating from HW.
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*/
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if (*prev)
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lrc_runtime_stop((*prev)->context);
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prev_ce = (*prev)->context;
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if (*execlists->active)
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lrc_runtime_start((*execlists->active)->context);
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active_ce = (*execlists->active)->context;
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if (prev_ce != active_ce) {
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if (prev_ce)
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lrc_runtime_stop(prev_ce);
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if (active_ce)
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lrc_runtime_start(active_ce);
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}
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new_timeslice(execlists);
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}
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@ -235,6 +235,13 @@ static void delayed_huc_load_fini(struct intel_huc *huc)
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i915_sw_fence_fini(&huc->delayed_load.fence);
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}
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int intel_huc_sanitize(struct intel_huc *huc)
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{
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delayed_huc_load_complete(huc);
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intel_uc_fw_sanitize(&huc->fw);
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return 0;
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}
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static bool vcs_supported(struct intel_gt *gt)
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{
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intel_engine_mask_t mask = gt->info.engine_mask;
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@ -41,6 +41,7 @@ struct intel_huc {
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} delayed_load;
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};
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int intel_huc_sanitize(struct intel_huc *huc);
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void intel_huc_init_early(struct intel_huc *huc);
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int intel_huc_init(struct intel_huc *huc);
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void intel_huc_fini(struct intel_huc *huc);
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@ -54,12 +55,6 @@ bool intel_huc_is_authenticated(struct intel_huc *huc);
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void intel_huc_register_gsc_notifier(struct intel_huc *huc, struct bus_type *bus);
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void intel_huc_unregister_gsc_notifier(struct intel_huc *huc, struct bus_type *bus);
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static inline int intel_huc_sanitize(struct intel_huc *huc)
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{
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intel_uc_fw_sanitize(&huc->fw);
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return 0;
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}
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static inline bool intel_huc_is_supported(struct intel_huc *huc)
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{
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return intel_uc_fw_is_supported(&huc->fw);
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@ -4638,13 +4638,13 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
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err = oa_config->id;
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goto sysfs_err;
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}
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mutex_unlock(&perf->metrics_lock);
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id = oa_config->id;
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drm_dbg(&perf->i915->drm,
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"Added config %s id=%i\n", oa_config->uuid, oa_config->id);
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mutex_unlock(&perf->metrics_lock);
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return oa_config->id;
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return id;
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sysfs_err:
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mutex_unlock(&perf->metrics_lock);
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@ -363,6 +363,35 @@ nv50_outp_atomic_check_view(struct drm_encoder *encoder,
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return 0;
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}
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static void
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nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state)
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{
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struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_display_mode *mode = &asyh->state.adjusted_mode;
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unsigned int max_rate, mode_rate;
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switch (nv_encoder->dcb->type) {
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case DCB_OUTPUT_DP:
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max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
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/* we don't support more than 10 anyway */
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asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
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/* reduce the bpc until it works out */
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while (asyh->or.bpc > 6) {
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mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
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if (mode_rate <= max_rate)
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break;
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asyh->or.bpc -= 2;
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}
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break;
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default:
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break;
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}
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}
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static int
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nv50_outp_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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@ -381,6 +410,9 @@ nv50_outp_atomic_check(struct drm_encoder *encoder,
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if (crtc_state->mode_changed || crtc_state->connectors_changed)
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asyh->or.bpc = connector->display_info.bpc;
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/* We might have to reduce the bpc */
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nv50_outp_atomic_fix_depth(encoder, crtc_state);
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return 0;
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}
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@ -263,8 +263,6 @@ nouveau_dp_irq(struct work_struct *work)
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}
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/* TODO:
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* - Use the minimum possible BPC here, once we add support for the max bpc
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* property.
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* - Validate against the DP caps advertised by the GPU (we don't check these
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* yet)
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*/
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@ -276,7 +274,11 @@ nv50_dp_mode_valid(struct drm_connector *connector,
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{
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const unsigned int min_clock = 25000;
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unsigned int max_rate, mode_rate, ds_max_dotclock, clock = mode->clock;
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const u8 bpp = connector->display_info.bpc * 3;
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/* Check with the minmum bpc always, so we can advertise better modes.
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* In particlar not doing this causes modes to be dropped on HDR
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* displays as we might check with a bpc of 16 even.
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*/
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const u8 bpp = 6 * 3;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE && !outp->caps.dp_interlace)
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return MODE_NO_INTERLACE;
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@ -504,6 +504,7 @@ static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as,
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if (IS_ERR(pages[i])) {
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mutex_unlock(&bo->base.pages_lock);
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ret = PTR_ERR(pages[i]);
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pages[i] = NULL;
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goto err_pages;
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}
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}
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