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ARC: irqflags - Interrupt enabling/disabling at in-core intc
ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels"
of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts.
CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2)
to globally enable (or disable) all IRQs at a level. Hence the
implementation of arch_local_irq_{save,restore,enable,disable}( )
The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence
the use of LR/SR instructions. Further, E1/E2 bits in there can only be
updated using the FLAG insn.
The intc supports 32 interrupts - and per IRQ enabling is controlled by
a bit in the AUX_IENABLE register, hence the implmentation of
arch_{,un}mask_irq( ) routines.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Vineet Gupta
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cfdbc2e16e
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114
arch/arc/include/asm/arcregs.h
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114
arch/arc/include/asm/arcregs.h
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_ARC_ARCREGS_H
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#define _ASM_ARC_ARCREGS_H
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#ifdef __KERNEL__
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/* status32 Bits Positions */
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#define STATUS_H_BIT 0 /* CPU Halted */
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#define STATUS_E1_BIT 1 /* Int 1 enable */
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#define STATUS_E2_BIT 2 /* Int 2 enable */
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#define STATUS_A1_BIT 3 /* Int 1 active */
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#define STATUS_A2_BIT 4 /* Int 2 active */
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#define STATUS_AE_BIT 5 /* Exception active */
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#define STATUS_DE_BIT 6 /* PC is in delay slot */
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#define STATUS_U_BIT 7 /* User/Kernel mode */
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#define STATUS_L_BIT 12 /* Loop inhibit */
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/* These masks correspond to the status word(STATUS_32) bits */
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#define STATUS_H_MASK (1<<STATUS_H_BIT)
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#define STATUS_E1_MASK (1<<STATUS_E1_BIT)
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#define STATUS_E2_MASK (1<<STATUS_E2_BIT)
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#define STATUS_A1_MASK (1<<STATUS_A1_BIT)
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#define STATUS_A2_MASK (1<<STATUS_A2_BIT)
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#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
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#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
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#define STATUS_U_MASK (1<<STATUS_U_BIT)
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#define STATUS_L_MASK (1<<STATUS_L_BIT)
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/* Auxiliary registers */
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#define AUX_IDENTITY 4
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#define AUX_INTR_VEC_BASE 0x25
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#define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
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#define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
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#define AUX_IRQ_LV12 0x43 /* interrupt level register */
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#define AUX_IENABLE 0x40c
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#define AUX_ITRIGGER 0x40d
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#define AUX_IPULSE 0x415
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#ifndef __ASSEMBLY__
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/*
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******************************************************************
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* Inline ASM macros to read/write AUX Regs
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* Essentially invocation of lr/sr insns from "C"
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*/
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#if 1
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#define read_aux_reg(reg) __builtin_arc_lr(reg)
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/* gcc builtin sr needs reg param to be long immediate */
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#define write_aux_reg(reg_immed, val) \
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__builtin_arc_sr((unsigned int)val, reg_immed)
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#else
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#define read_aux_reg(reg) \
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({ \
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unsigned int __ret; \
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__asm__ __volatile__( \
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" lr %0, [%1]" \
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: "=r"(__ret) \
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: "i"(reg)); \
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__ret; \
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})
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/*
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* Aux Reg address is specified as long immediate by caller
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* e.g.
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* write_aux_reg(0x69, some_val);
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* This generates tightest code.
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*/
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#define write_aux_reg(reg_imm, val) \
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({ \
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__asm__ __volatile__( \
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" sr %0, [%1] \n" \
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: \
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: "ir"(val), "i"(reg_imm)); \
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})
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/*
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* Aux Reg address is specified in a variable
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* * e.g.
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* reg_num = 0x69
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* write_aux_reg2(reg_num, some_val);
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* This has to generate glue code to load the reg num from
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* memory to a reg hence not recommended.
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*/
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#define write_aux_reg2(reg_in_var, val) \
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({ \
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unsigned int tmp; \
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\
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__asm__ __volatile__( \
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" ld %0, [%2] \n\t" \
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" sr %1, [%0] \n\t" \
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: "=&r"(tmp) \
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: "r"(val), "memory"(®_in_var)); \
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})
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#endif
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#endif /* __ASEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_ARC_ARCREGS_H */
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149
arch/arc/include/asm/irqflags.h
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149
arch/arc/include/asm/irqflags.h
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARC_IRQFLAGS_H
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#define __ASM_ARC_IRQFLAGS_H
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/* vineetg: March 2010 : local_irq_save( ) optimisation
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* -Remove explicit mov of current status32 into reg, that is not needed
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* -Use BIC insn instead of INVERTED + AND
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* -Conditionally disable interrupts (if they are not enabled, don't disable)
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*/
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#ifdef __KERNEL__
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#include <asm/arcregs.h>
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#ifndef __ASSEMBLY__
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/******************************************************************
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* IRQ Control Macros
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******************************************************************/
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/*
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* Save IRQ state and disable IRQs
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*/
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static inline long arch_local_irq_save(void)
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{
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unsigned long temp, flags;
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__asm__ __volatile__(
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" lr %1, [status32] \n"
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" bic %0, %1, %2 \n"
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" and.f 0, %1, %2 \n"
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" flag.nz %0 \n"
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: "=r"(temp), "=r"(flags)
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: "n"((STATUS_E1_MASK | STATUS_E2_MASK))
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: "cc");
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return flags;
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}
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/*
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* restore saved IRQ state
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*/
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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__asm__ __volatile__(
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" flag %0 \n"
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:
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: "r"(flags));
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}
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/*
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* Unconditionally Enable IRQs
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*/
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extern void arch_local_irq_enable(void);
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/*
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* Unconditionally Disable IRQs
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*/
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static inline void arch_local_irq_disable(void)
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{
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unsigned long temp;
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__asm__ __volatile__(
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" lr %0, [status32] \n"
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" and %0, %0, %1 \n"
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" flag %0 \n"
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: "=&r"(temp)
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: "n"(~(STATUS_E1_MASK | STATUS_E2_MASK)));
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}
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/*
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* save IRQ state
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*/
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static inline long arch_local_save_flags(void)
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{
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unsigned long temp;
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__asm__ __volatile__(
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" lr %0, [status32] \n"
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: "=&r"(temp));
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return temp;
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}
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/*
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* Query IRQ state
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*/
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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return !(flags & (STATUS_E1_MASK));
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}
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static inline int arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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static inline void arch_mask_irq(unsigned int irq)
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{
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unsigned int ienb;
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ienb = read_aux_reg(AUX_IENABLE);
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ienb &= ~(1 << irq);
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write_aux_reg(AUX_IENABLE, ienb);
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}
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static inline void arch_unmask_irq(unsigned int irq)
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{
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unsigned int ienb;
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ienb = read_aux_reg(AUX_IENABLE);
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ienb |= (1 << irq);
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write_aux_reg(AUX_IENABLE, ienb);
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}
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#else
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.macro IRQ_DISABLE scratch
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lr \scratch, [status32]
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bic \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
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flag \scratch
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.endm
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.macro IRQ_DISABLE_SAVE scratch, save
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lr \scratch, [status32]
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mov \save, \scratch /* Make a copy */
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bic \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
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flag \scratch
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.endm
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.macro IRQ_ENABLE scratch
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lr \scratch, [status32]
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or \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)
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flag \scratch
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* KERNEL */
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#endif
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32
arch/arc/kernel/irq.c
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32
arch/arc/kernel/irq.c
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@ -0,0 +1,32 @@
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/*
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* Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/irqflags.h>
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#include <asm/arcregs.h>
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void arch_local_irq_enable(void)
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{
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unsigned long flags;
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/*
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* ARC IDE Drivers tries to re-enable interrupts from hard-isr
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* context which is simply wrong
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*/
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if (in_irq()) {
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WARN_ONCE(1, "IRQ enabled from hard-isr");
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return;
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}
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flags = arch_local_save_flags();
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flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
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arch_local_irq_restore(flags);
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}
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EXPORT_SYMBOL(arch_local_irq_enable);
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