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ARM: dts: am335x-pocketbeagle: set default mux for gpio pins
These pins on the PocketBeagle P1 and P2 headers are connected to AM3358
balls with gpio lines, and these pins are not used for any other
peripherals by default. These GPIO lines are unclaimed and could be used
by userspace program through the gpiod ABI.
This patch adds a "default" state in the am33xx_pinmux node and sets the
mux for those pins to gpio (mode 7) and input enable.
The "pinctrl-single,bias-pullup" and "pinctrl-single,bias-pulldown"
pinconf properties are also set for each pin per the ball reset state in
section 4.2 of the datasheet [0].
This is the AM335x pin control register format in Table 9-60 [1]:
bit attribute value
----------------------------------
31-7 reserved 0 on reset
6 slew { 0: fast, 1: slow }
5 rx_active { 0: rx disable, 1: rx enabled }
4 pu_typesel { 0: pulldown select, 1: pullup select }
3 puden { 0: pud enable, 1: disabled }
2 mode 3 bits to selec mode 0 to 7
1 mode
0 mode
The values for the bias pinconf properties are derived as follows:
pinctrl-single,bias-pullup = <[input] [enabled] [disable] [mask]>;
pinctrl-single,bias-pullup = < 0x10 0x10 0x10 0x18 >;
2^5 2^4 2^3 2^2 2^1 2^0 |
0x20 0x10 0x08 0x04 0x02 0x01 |
--------------------------------------------------|
input x 1 0 x x x | 0x10
enabled x 1 0 x x x | 0x10
disabled x 0 0 x x x | 0x00
mask x 1 1 x x x | 0x18
pinctrl-single,bias-pulldown = <[input] [enabled] [disable] [mask]>;
pinctrl-single,bias-pulldown = < 0x0 0x0 0x10 0x18 >;
2^5 2^4 2^3 2^2 2^1 2^0 |
0x20 0x10 0x08 0x04 0x02 0x01 |
--------------------------------------------------|
input x 0 0 x x x | 0x00
enabled x 0 0 x x x | 0x00
disabled x 1 0 x x x | 0x10
mask x 1 1 x x x | 0x18
[0] http://www.ti.com/lit/ds/symlink/am3358.pdf
[1] https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Drew Fustini
Tony Lindgren
parent
e14d2c7663
commit
abe4e4675d
@ -204,6 +204,131 @@
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};
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&am33xx_pinmux {
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pinctrl-names = "default";
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pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio
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&P2_33_gpio &P2_22_gpio &P2_18_gpio &P2_10_gpio
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&P2_06_gpio &P2_04_gpio &P2_02_gpio &P2_08_gpio
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&P2_17_gpio >;
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/* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */
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P2_03_gpio: pinmux_P2_03_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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/* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */
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P1_34_gpio: pinmux_P1_34_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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/* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */
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P2_19_gpio: pinmux_P2_19_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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/* P2_24 (ZCZ ball T12) gpio1_12 0x830 PIN 12 */
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P2_24_gpio: pinmux_P2_24_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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/* P2_33 (ZCZ ball R12) gpio1_13 0x834 PIN 13 */
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P2_33_gpio: pinmux_P2_33_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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/* P2_22 (ZCZ ball V13) gpio1_14 0x838 PIN 14 */
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P2_22_gpio: pinmux_P2_22_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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/* P2_18 (ZCZ ball U13) gpio1_15 0x83c PIN 15 */
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P2_18_gpio: pinmux_P2_18_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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/* P2_10 (ZCZ ball R14) gpio1_20 0x850 PIN 20 */
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P2_10_gpio: pinmux_P2_10_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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/* P2_06 (ZCZ ball U16) gpio1_25 0x864 PIN 25 */
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P2_06_gpio: pinmux_P2_06_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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/* P2_04 (ZCZ ball T16) gpio1_26 0x868 PIN 26 */
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P2_04_gpio: pinmux_P2_04_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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/* P2_02 (ZCZ ball V17) gpio1_27 0x86c PIN 27 */
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P2_02_gpio: pinmux_P2_02_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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/* P2_08 (ZCZ ball U18) gpio1_28 0x878 PIN 30 */
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P2_08_gpio: pinmux_P2_08_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x00 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x00 0x00 0x10 0x18>;
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};
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/* P2_17 (ZCZ ball V12) gpio2_1 0x88c PIN 35 */
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P2_17_gpio: pinmux_P2_17_gpio {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7)
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>;
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pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
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pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
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};
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i2c2_pins: pinmux-i2c2-pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */
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