From abbd52fd6bb15211b578598d8f31d5bc6084f02e Mon Sep 17 00:00:00 2001 From: James Hogan Date: Wed, 22 Nov 2017 11:30:32 +0000 Subject: [PATCH] MIPS: XPA: Standardise readx/writex accessors Now that we are using assembler macros to implement XPA instructions on toolchains which don't support them, pass Cop0 register names to the __{readx,writex}_32bit_c0_register macros in $n format rather than register numbers. Also pass a register select which may be useful in future (for example for MemoryMapID field of WatchHi registers on I6500). This is to make them consistent with the normal Cop0 register access macros which they were originally based on. Signed-off-by: James Hogan Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17777/ --- arch/mips/include/asm/mipsregs.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index b1dedd5935a1..858752dac337 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1516,7 +1516,7 @@ _ASM_MACRO_2R_1S(mthc0, rt, rd, sel, #define _ASM_SET_XPA ".set\txpa\n\t" #endif -#define __readx_32bit_c0_register(source) \ +#define __readx_32bit_c0_register(source, sel) \ ({ \ unsigned int __res; \ \ @@ -1524,23 +1524,23 @@ _ASM_MACRO_2R_1S(mthc0, rt, rd, sel, " .set push \n" \ " .set mips32r2 \n" \ _ASM_SET_XPA \ - " mfhc0 %0, $%1 \n" \ + " mfhc0 %0, " #source ", %1 \n" \ " .set pop \n" \ : "=r" (__res) \ - : "i" (source)); \ + : "i" (sel)); \ __res; \ }) -#define __writex_32bit_c0_register(register, value) \ +#define __writex_32bit_c0_register(register, sel, value) \ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set mips32r2 \n" \ _ASM_SET_XPA \ - " mthc0 %z0, $%1 \n" \ + " mthc0 %z0, " #register ", %1 \n" \ " .set pop \n" \ : \ - : "Jr" (value), "i" (register)); \ + : "Jr" (value), "i" (sel)); \ } while (0) #define read_c0_index() __read_32bit_c0_register($0, 0) @@ -1552,14 +1552,14 @@ do { \ #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) -#define readx_c0_entrylo0() __readx_32bit_c0_register(2) -#define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val) +#define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0) +#define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val) #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) -#define readx_c0_entrylo1() __readx_32bit_c0_register(3) -#define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val) +#define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0) +#define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val) #define read_c0_conf() __read_32bit_c0_register($3, 0) #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)