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iwlwifi: pcie: copy TX functions to new transport
This is just a copy-paste in order to make changes tracking easier. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
Sara Sharon
Luca Coelho
parent
c65f4e03fc
commit
ab6c644539
@ -650,6 +650,12 @@ static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
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}
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}
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static inline void *iwl_pcie_get_tfd(struct iwl_trans_pcie *trans_pcie,
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struct iwl_txq *txq, int idx)
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{
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return txq->tfds + trans_pcie->tfd_size * idx;
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}
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static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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@ -759,6 +765,11 @@ int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
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void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
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bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans);
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void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq);
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int iwl_queue_space(const struct iwl_txq *q);
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int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_txq *txq, u8 hdr_len,
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struct iwl_cmd_meta *out_meta,
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struct iwl_device_cmd *dev_cmd, u16 tb1_len);
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/* transport gen 2 exported functions */
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int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
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@ -769,5 +780,7 @@ int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans,
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int cmd_id,
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unsigned int timeout);
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void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue);
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int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_device_cmd *dev_cmd, int txq_id);
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#endif /* __iwl_trans_int_pcie_h__ */
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@ -2920,7 +2920,7 @@ static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
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.send_cmd = iwl_trans_pcie_send_hcmd,
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.tx = iwl_trans_pcie_tx,
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.tx = iwl_trans_pcie_gen2_tx,
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.reclaim = iwl_trans_pcie_reclaim,
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.txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
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@ -53,6 +53,525 @@
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#include "iwl-csr.h"
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#include "iwl-io.h"
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#include "internal.h"
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#include "mvm/fw-api.h"
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/*
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* iwl_pcie_txq_update_byte_tbl - Set up entry in Tx byte-count array
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*/
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static void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans *trans,
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struct iwl_txq *txq, u16 byte_cnt,
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int num_tbs)
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{
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struct iwlagn_scd_bc_tbl *scd_bc_tbl;
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int write_ptr = txq->write_ptr;
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u8 filled_tfd_size, num_fetch_chunks;
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u16 len = byte_cnt;
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__le16 bc_ent;
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scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
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len = DIV_ROUND_UP(len, 4);
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if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
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return;
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filled_tfd_size = offsetof(struct iwl_tfh_tfd, tbs) +
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num_tbs * sizeof(struct iwl_tfh_tb);
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/*
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* filled_tfd_size contains the number of filled bytes in the TFD.
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* Dividing it by 64 will give the number of chunks to fetch
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* to SRAM- 0 for one chunk, 1 for 2 and so on.
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* If, for example, TFD contains only 3 TBs then 32 bytes
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* of the TFD are used, and only one chunk of 64 bytes should
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* be fetched
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*/
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num_fetch_chunks = DIV_ROUND_UP(filled_tfd_size, 64) - 1;
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bc_ent = cpu_to_le16(len | (num_fetch_chunks << 12));
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scd_bc_tbl[txq->id].tfd_offset[write_ptr] = bc_ent;
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}
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/*
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* iwl_pcie_gen2_txq_inc_wr_ptr - Send new write index to hardware
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*/
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static void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans,
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struct iwl_txq *txq)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u32 reg = 0;
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int txq_id = txq->id;
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lockdep_assert_held(&txq->lock);
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/*
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* explicitly wake up the NIC if:
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* 1. shadow registers aren't enabled
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* 2. NIC is woken up for CMD regardless of shadow outside this function
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* 3. there is a chance that the NIC is asleep
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*/
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if (!trans->cfg->base_params->shadow_reg_enable &&
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txq_id != trans_pcie->cmd_queue &&
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test_bit(STATUS_TPOWER_PMI, &trans->status)) {
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/*
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* wake up nic if it's powered down ...
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* uCode will wake up, and interrupt us again, so next
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* time we'll skip this part.
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*/
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reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
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if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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IWL_DEBUG_INFO(trans,
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"Tx queue %d requesting wakeup, GP1 = 0x%x\n",
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txq_id, reg);
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iwl_set_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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txq->need_update = true;
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return;
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}
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}
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/*
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* if not in power-save mode, uCode will never sleep when we're
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* trying to tx (during RFKILL, we're not trying to tx).
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*/
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IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
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if (!txq->block)
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iwl_write32(trans, HBUS_TARG_WRPTR,
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txq->write_ptr | (txq_id << 8));
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}
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static inline u8 iwl_pcie_gen2_get_num_tbs(struct iwl_trans *trans, void *_tfd)
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{
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if (trans->cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd = _tfd;
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return le16_to_cpu(tfd->num_tbs) & 0x1f;
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} else {
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struct iwl_tfd *tfd = _tfd;
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return tfd->num_tbs & 0x1f;
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}
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}
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static inline dma_addr_t iwl_pcie_gen2_tb_get_addr(struct iwl_trans *trans,
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void *_tfd, u8 idx)
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{
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if (trans->cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd = _tfd;
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struct iwl_tfh_tb *tb = &tfd->tbs[idx];
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return (dma_addr_t)(le64_to_cpu(tb->addr));
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} else {
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struct iwl_tfd *tfd = _tfd;
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struct iwl_tfd_tb *tb = &tfd->tbs[idx];
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dma_addr_t addr = get_unaligned_le32(&tb->lo);
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dma_addr_t hi_len;
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if (sizeof(dma_addr_t) <= sizeof(u32))
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return addr;
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hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
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/*
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* shift by 16 twice to avoid warnings on 32-bit
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* (where this code never runs anyway due to the
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* if statement above)
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*/
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return addr | ((hi_len << 16) << 16);
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}
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}
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static void iwl_pcie_gen2_tfd_unmap(struct iwl_trans *trans,
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struct iwl_cmd_meta *meta,
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struct iwl_txq *txq, int index)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int i, num_tbs;
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void *tfd = iwl_pcie_get_tfd(trans_pcie, txq, index);
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/* Sanity check on number of chunks */
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num_tbs = iwl_pcie_gen2_get_num_tbs(trans, tfd);
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if (num_tbs >= trans_pcie->max_tbs) {
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IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
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/* @todo issue fatal error, it is quite serious situation */
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return;
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}
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/* first TB is never freed - it's the bidirectional DMA data */
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for (i = 1; i < num_tbs; i++) {
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if (meta->tbs & BIT(i))
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dma_unmap_page(trans->dev,
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iwl_pcie_gen2_tb_get_addr(trans, tfd,
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i),
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iwl_pcie_gen2_tb_get_addr(trans, tfd,
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i),
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DMA_TO_DEVICE);
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else
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dma_unmap_single(trans->dev,
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iwl_pcie_gen2_tb_get_addr(trans, tfd,
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i),
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iwl_pcie_gen2_tb_get_addr(trans, tfd,
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i),
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DMA_TO_DEVICE);
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}
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if (trans->cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
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tfd_fh->num_tbs = 0;
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} else {
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struct iwl_tfd *tfd_fh = (void *)tfd;
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tfd_fh->num_tbs = 0;
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}
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}
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static void iwl_pcie_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
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{
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/* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
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* idx is bounded by n_window
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*/
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int rd_ptr = txq->read_ptr;
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int idx = get_cmd_index(txq, rd_ptr);
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lockdep_assert_held(&txq->lock);
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/* We have only q->n_window txq->entries, but we use
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* TFD_QUEUE_SIZE_MAX tfds
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*/
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iwl_pcie_gen2_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
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/* free SKB */
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if (txq->entries) {
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struct sk_buff *skb;
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skb = txq->entries[idx].skb;
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/* Can be called from irqs-disabled context
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* If skb is not NULL, it means that the whole queue is being
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* freed and that the queue is not empty - free the skb
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*/
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if (skb) {
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iwl_op_mode_free_skb(trans->op_mode, skb);
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txq->entries[idx].skb = NULL;
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}
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}
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}
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static inline void iwl_pcie_gen2_set_tb(struct iwl_trans *trans, void *tfd,
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u8 idx, dma_addr_t addr, u16 len)
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{
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if (trans->cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
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struct iwl_tfh_tb *tb = &tfd_fh->tbs[idx];
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put_unaligned_le64(addr, &tb->addr);
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tb->tb_len = cpu_to_le16(len);
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tfd_fh->num_tbs = cpu_to_le16(idx + 1);
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} else {
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struct iwl_tfd *tfd_fh = (void *)tfd;
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struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
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u16 hi_n_len = len << 4;
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put_unaligned_le32(addr, &tb->lo);
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hi_n_len |= iwl_get_dma_hi_addr(addr);
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tb->hi_n_len = cpu_to_le16(hi_n_len);
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tfd_fh->num_tbs = idx + 1;
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}
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}
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int iwl_pcie_gen2_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
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dma_addr_t addr, u16 len, bool reset)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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void *tfd;
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u32 num_tbs;
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tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr;
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if (reset)
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memset(tfd, 0, trans_pcie->tfd_size);
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num_tbs = iwl_pcie_gen2_get_num_tbs(trans, tfd);
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/* Each TFD can point to a maximum max_tbs Tx buffers */
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if (num_tbs >= trans_pcie->max_tbs) {
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IWL_ERR(trans, "Error can not send more than %d chunks\n",
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trans_pcie->max_tbs);
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return -EINVAL;
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}
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if (WARN(addr & ~IWL_TX_DMA_MASK,
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"Unaligned address = %llx\n", (unsigned long long)addr))
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return -EINVAL;
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iwl_pcie_gen2_set_tb(trans, tfd, num_tbs, addr, len);
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return num_tbs;
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}
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static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_txq *txq, u8 hdr_len,
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struct iwl_cmd_meta *out_meta,
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struct iwl_device_cmd *dev_cmd, u16 tb1_len)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u16 tb2_len;
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int i;
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/*
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* Set up TFD's third entry to point directly to remainder
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* of skb's head, if any
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*/
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tb2_len = skb_headlen(skb) - hdr_len;
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if (tb2_len > 0) {
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dma_addr_t tb2_phys = dma_map_single(trans->dev,
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skb->data + hdr_len,
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tb2_len, DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
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iwl_pcie_gen2_tfd_unmap(trans, out_meta, txq,
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txq->write_ptr);
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return -EINVAL;
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}
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iwl_pcie_gen2_build_tfd(trans, txq, tb2_phys, tb2_len, false);
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}
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/* set up the remaining entries to point to the data */
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for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
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const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
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dma_addr_t tb_phys;
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int tb_idx;
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if (!skb_frag_size(frag))
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continue;
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tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
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skb_frag_size(frag), DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
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iwl_pcie_gen2_tfd_unmap(trans, out_meta, txq,
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txq->write_ptr);
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return -EINVAL;
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}
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tb_idx = iwl_pcie_gen2_build_tfd(trans, txq, tb_phys,
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skb_frag_size(frag), false);
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out_meta->tbs |= BIT(tb_idx);
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}
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trace_iwlwifi_dev_tx(trans->dev, skb,
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iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr),
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trans_pcie->tfd_size,
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&dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
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skb->data + hdr_len, tb2_len);
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trace_iwlwifi_dev_tx_data(trans->dev, skb,
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hdr_len, skb->len - hdr_len);
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return 0;
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}
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#define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(TX_CMD_FLG_MH_PAD)
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int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_device_cmd *dev_cmd, int txq_id)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct ieee80211_hdr *hdr;
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struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
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struct iwl_cmd_meta *out_meta;
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struct iwl_txq *txq;
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dma_addr_t tb0_phys, tb1_phys, scratch_phys;
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void *tb1_addr;
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void *tfd;
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u16 len, tb1_len;
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bool wait_write_ptr;
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__le16 fc;
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u8 hdr_len;
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u16 wifi_seq;
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bool amsdu;
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txq = &trans_pcie->txq[txq_id];
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if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
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"TX on unused queue %d\n", txq_id))
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return -EINVAL;
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if (unlikely(trans_pcie->sw_csum_tx &&
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skb->ip_summed == CHECKSUM_PARTIAL)) {
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int offs = skb_checksum_start_offset(skb);
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int csum_offs = offs + skb->csum_offset;
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__wsum csum;
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if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
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return -1;
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csum = skb_checksum(skb, offs, skb->len - offs, 0);
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*(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
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skb->ip_summed = CHECKSUM_UNNECESSARY;
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}
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if (skb_is_nonlinear(skb) &&
|
||||
skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
|
||||
__skb_linearize(skb))
|
||||
return -ENOMEM;
|
||||
|
||||
/* mac80211 always puts the full header into the SKB's head,
|
||||
* so there's no need to check if it's readable there
|
||||
*/
|
||||
hdr = (struct ieee80211_hdr *)skb->data;
|
||||
fc = hdr->frame_control;
|
||||
hdr_len = ieee80211_hdrlen(fc);
|
||||
|
||||
spin_lock(&txq->lock);
|
||||
|
||||
if (iwl_queue_space(txq) < txq->high_mark) {
|
||||
iwl_stop_queue(trans, txq);
|
||||
|
||||
/* don't put the packet on the ring, if there is no room */
|
||||
if (unlikely(iwl_queue_space(txq) < 3)) {
|
||||
struct iwl_device_cmd **dev_cmd_ptr;
|
||||
|
||||
dev_cmd_ptr = (void *)((u8 *)skb->cb +
|
||||
trans_pcie->dev_cmd_offs);
|
||||
|
||||
*dev_cmd_ptr = dev_cmd;
|
||||
__skb_queue_tail(&txq->overflow_q, skb);
|
||||
|
||||
spin_unlock(&txq->lock);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* In AGG mode, the index in the ring must correspond to the WiFi
|
||||
* sequence number. This is a HW requirements to help the SCD to parse
|
||||
* the BA.
|
||||
* Check here that the packets are in the right place on the ring.
|
||||
*/
|
||||
wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
|
||||
WARN_ONCE(txq->ampdu &&
|
||||
(wifi_seq & 0xff) != txq->write_ptr,
|
||||
"Q: %d WiFi Seq %d tfdNum %d",
|
||||
txq_id, wifi_seq, txq->write_ptr);
|
||||
|
||||
/* Set up driver data for this TFD */
|
||||
txq->entries[txq->write_ptr].skb = skb;
|
||||
txq->entries[txq->write_ptr].cmd = dev_cmd;
|
||||
|
||||
dev_cmd->hdr.sequence =
|
||||
cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
|
||||
INDEX_TO_SEQ(txq->write_ptr)));
|
||||
|
||||
tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
|
||||
scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
|
||||
offsetof(struct iwl_tx_cmd, scratch);
|
||||
|
||||
tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
|
||||
tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
|
||||
|
||||
/* Set up first empty entry in queue's array of Tx/cmd buffers */
|
||||
out_meta = &txq->entries[txq->write_ptr].meta;
|
||||
out_meta->flags = 0;
|
||||
|
||||
/*
|
||||
* The second TB (tb1) points to the remainder of the TX command
|
||||
* and the 802.11 header - dword aligned size
|
||||
* (This calculation modifies the TX command, so do it before the
|
||||
* setup of the first TB)
|
||||
*/
|
||||
len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
|
||||
hdr_len - IWL_FIRST_TB_SIZE;
|
||||
/* do not align A-MSDU to dword as the subframe header aligns it */
|
||||
amsdu = ieee80211_is_data_qos(fc) &&
|
||||
(*ieee80211_get_qos_ctl(hdr) &
|
||||
IEEE80211_QOS_CTL_A_MSDU_PRESENT);
|
||||
if (trans_pcie->sw_csum_tx || !amsdu) {
|
||||
tb1_len = ALIGN(len, 4);
|
||||
/* Tell NIC about any 2-byte padding after MAC header */
|
||||
if (tb1_len != len)
|
||||
tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
|
||||
} else {
|
||||
tb1_len = len;
|
||||
}
|
||||
|
||||
/*
|
||||
* The first TB points to bi-directional DMA data, we'll
|
||||
* memcpy the data into it later.
|
||||
*/
|
||||
iwl_pcie_gen2_build_tfd(trans, txq, tb0_phys, IWL_FIRST_TB_SIZE, true);
|
||||
|
||||
/* there must be data left over for TB1 or this code must be changed */
|
||||
BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
|
||||
|
||||
/* map the data for TB1 */
|
||||
tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
|
||||
tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
|
||||
if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
|
||||
goto out_err;
|
||||
iwl_pcie_gen2_build_tfd(trans, txq, tb1_phys, tb1_len, false);
|
||||
|
||||
if (amsdu) {
|
||||
if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
|
||||
out_meta, dev_cmd,
|
||||
tb1_len)))
|
||||
goto out_err;
|
||||
} else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
|
||||
out_meta, dev_cmd, tb1_len))) {
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
/* building the A-MSDU might have changed this data, so memcpy it now */
|
||||
memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr,
|
||||
IWL_FIRST_TB_SIZE);
|
||||
|
||||
tfd = iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr);
|
||||
/* Set up entry for this TFD in Tx byte-count array */
|
||||
iwl_pcie_gen2_update_byte_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
|
||||
iwl_pcie_gen2_get_num_tbs(trans, tfd));
|
||||
|
||||
wait_write_ptr = ieee80211_has_morefrags(fc);
|
||||
|
||||
/* start timer if queue currently empty */
|
||||
if (txq->read_ptr == txq->write_ptr) {
|
||||
if (txq->wd_timeout) {
|
||||
/*
|
||||
* If the TXQ is active, then set the timer, if not,
|
||||
* set the timer in remainder so that the timer will
|
||||
* be armed with the right value when the station will
|
||||
* wake up.
|
||||
*/
|
||||
if (!txq->frozen)
|
||||
mod_timer(&txq->stuck_timer,
|
||||
jiffies + txq->wd_timeout);
|
||||
else
|
||||
txq->frozen_expiry_remainder = txq->wd_timeout;
|
||||
}
|
||||
IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id);
|
||||
iwl_trans_ref(trans);
|
||||
}
|
||||
|
||||
/* Tell device the write index *just past* this latest filled TFD */
|
||||
txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
|
||||
if (!wait_write_ptr)
|
||||
iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq);
|
||||
|
||||
/*
|
||||
* At this point the frame is "transmitted" successfully
|
||||
* and we will get a TX status notification eventually.
|
||||
*/
|
||||
spin_unlock(&txq->lock);
|
||||
return 0;
|
||||
out_err:
|
||||
spin_unlock(&txq->lock);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* iwl_pcie_gen2_txq_unmap - Unmap any remaining DMA mappings and free skb's
|
||||
|
||||
@ -71,7 +71,7 @@
|
||||
*
|
||||
***************************************************/
|
||||
|
||||
static int iwl_queue_space(const struct iwl_txq *q)
|
||||
int iwl_queue_space(const struct iwl_txq *q)
|
||||
{
|
||||
unsigned int max;
|
||||
unsigned int used;
|
||||
@ -185,6 +185,7 @@ static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
|
||||
__le16 bc_ent;
|
||||
struct iwl_tx_cmd *tx_cmd =
|
||||
(void *)txq->entries[txq->write_ptr].cmd->payload;
|
||||
u8 sta_id = tx_cmd->sta_id;
|
||||
|
||||
scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
|
||||
|
||||
@ -207,26 +208,7 @@ static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
|
||||
if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
|
||||
return;
|
||||
|
||||
if (trans->cfg->use_tfh) {
|
||||
u8 filled_tfd_size = offsetof(struct iwl_tfh_tfd, tbs) +
|
||||
num_tbs * sizeof(struct iwl_tfh_tb);
|
||||
/*
|
||||
* filled_tfd_size contains the number of filled bytes in the
|
||||
* TFD.
|
||||
* Dividing it by 64 will give the number of chunks to fetch
|
||||
* to SRAM- 0 for one chunk, 1 for 2 and so on.
|
||||
* If, for example, TFD contains only 3 TBs then 32 bytes
|
||||
* of the TFD are used, and only one chunk of 64 bytes should
|
||||
* be fetched
|
||||
*/
|
||||
u8 num_fetch_chunks = DIV_ROUND_UP(filled_tfd_size, 64) - 1;
|
||||
|
||||
bc_ent = cpu_to_le16(len | (num_fetch_chunks << 12));
|
||||
} else {
|
||||
u8 sta_id = tx_cmd->sta_id;
|
||||
|
||||
bc_ent = cpu_to_le16(len | (sta_id << 12));
|
||||
}
|
||||
bc_ent = cpu_to_le16(len | (sta_id << 12));
|
||||
|
||||
scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
|
||||
|
||||
@ -327,12 +309,6 @@ void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
|
||||
}
|
||||
}
|
||||
|
||||
static inline void *iwl_pcie_get_tfd(struct iwl_trans_pcie *trans_pcie,
|
||||
struct iwl_txq *txq, int idx)
|
||||
{
|
||||
return txq->tfds + trans_pcie->tfd_size * idx;
|
||||
}
|
||||
|
||||
static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
|
||||
void *_tfd, u8 idx)
|
||||
{
|
||||
@ -2104,10 +2080,10 @@ static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
|
||||
}
|
||||
}
|
||||
|
||||
static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
|
||||
struct iwl_txq *txq, u8 hdr_len,
|
||||
struct iwl_cmd_meta *out_meta,
|
||||
struct iwl_device_cmd *dev_cmd, u16 tb1_len)
|
||||
int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
|
||||
struct iwl_txq *txq, u8 hdr_len,
|
||||
struct iwl_cmd_meta *out_meta,
|
||||
struct iwl_device_cmd *dev_cmd, u16 tb1_len)
|
||||
{
|
||||
struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
|
||||
struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user