- Prevent error pointer dereference (Dan Carpenter)

- Fix PMU busyness values when using GuC mode (Umesh)
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmUMX88ACgkQ+mJfZA7r
 E8pq3ggAgJqK1dQxgw6/7ry7BJykmJ66RfqAR0ZttnXgtvwNl3/7Qbqku5vHEXaU
 fk3OByMlN+ihUNGoeIEPVsg+GXwkdq2ES847RsgriqR3+6DE1/Ed5IgBwemoeymR
 VZPFEb98115+DgyENIAytnTsIIkF1RCohWyklsiw3KWJ/RFMLmj0LKDAeRFEuPvx
 CDqGdAhx4uAmofc3JkxrBhBZwfXV6TN6aAoiDs2yu9gy5IKhqH0HFSRYrnRATWPS
 LyTCjp/xFdF7D2RjsXa4pQLBufzjT5Mcqj6TjQIh5QJh6T29Vy4qiO9+JjuOHWck
 P4WpidQq9RKOHJtnXOspWe2tOLkoYg==
 =CZzS
 -----END PGP SIGNATURE-----

Merge tag 'drm-intel-fixes-2023-09-21' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

- Prevent error pointer dereference (Dan Carpenter)
- Fix PMU busyness values when using GuC mode (Umesh)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZQxf267jxc7tiIlZ@intel.com
This commit is contained in:
Dave Airlie 2023-09-22 15:32:04 +10:00
commit ab2bff5993
3 changed files with 5 additions and 3 deletions

View File

@ -558,7 +558,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
DRIVER_CAPS(i915)->has_logical_contexts = true;
ewma__engine_latency_init(&engine->latency);
seqcount_init(&engine->stats.execlists.lock);
ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);

View File

@ -3550,6 +3550,8 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
logical_ring_default_vfuncs(engine);
logical_ring_default_irqs(engine);
seqcount_init(&engine->stats.execlists.lock);
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
rcs_submission_override(engine);

View File

@ -1094,6 +1094,9 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj)) {
obj = i915_gem_object_create_shmem(engine->i915, context_size);
if (IS_ERR(obj))
return ERR_CAST(obj);
/*
* Wa_22016122933: For Media version 13.0, all Media GT shared
* memory needs to be mapped as WC on CPU side and UC (PAT
@ -1102,8 +1105,6 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
if (intel_gt_needs_wa_22016122933(engine->gt))
i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
}
if (IS_ERR(obj))
return ERR_CAST(obj);
vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
if (IS_ERR(vma)) {