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DMAENGINE: ste_dma40: added support for link jobs in hw
If a new job is added on a physical channel that already has a job, the new job is linked in hw to the old job instead of queueing up the jobs. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Jonas Aaberg
Dan Williams
parent
3ae0267fd5
commit
aa182ae262
@ -92,6 +92,8 @@ struct d40_lli_pool {
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* @node: List entry.
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* @dir: The transfer direction of this job.
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* @is_in_client_list: true if the client owns this descriptor.
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* @is_hw_linked: true if this job will automatically be continued for
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* the previous one.
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*
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* This descriptor is used for both logical and physical transfers.
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*/
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@ -112,6 +114,7 @@ struct d40_desc {
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enum dma_data_direction dir;
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bool is_in_client_list;
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bool is_hw_linked;
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};
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/**
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@ -340,9 +343,6 @@ static int d40_pool_lli_alloc(struct d40_desc *d40d,
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align);
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d40d->lli_phy.dst = PTR_ALIGN(d40d->lli_phy.src + lli_len,
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align);
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d40d->lli_phy.src_addr = virt_to_phys(d40d->lli_phy.src);
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d40d->lli_phy.dst_addr = virt_to_phys(d40d->lli_phy.dst);
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}
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return 0;
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@ -357,22 +357,6 @@ static void d40_pool_lli_free(struct d40_desc *d40d)
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d40d->lli_log.dst = NULL;
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d40d->lli_phy.src = NULL;
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d40d->lli_phy.dst = NULL;
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d40d->lli_phy.src_addr = 0;
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d40d->lli_phy.dst_addr = 0;
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}
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static dma_cookie_t d40_assign_cookie(struct d40_chan *d40c,
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struct d40_desc *desc)
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{
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dma_cookie_t cookie = d40c->chan.cookie;
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if (++cookie < 0)
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cookie = 1;
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d40c->chan.cookie = cookie;
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desc->txd.cookie = cookie;
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return cookie;
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}
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static void d40_desc_remove(struct d40_desc *d40d)
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@ -443,6 +427,18 @@ static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
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return d;
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}
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static struct d40_desc *d40_last_queued(struct d40_chan *d40c)
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{
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struct d40_desc *d;
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if (list_empty(&d40c->queue))
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return NULL;
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list_for_each_entry(d, &d40c->queue, node)
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if (list_is_last(&d->node, &d40c->queue))
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break;
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return d;
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}
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/* Support functions for logical channels */
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static int d40_lcla_id_get(struct d40_chan *d40c)
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@ -729,6 +725,161 @@ static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
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d40d->lli_count += d40d->lli_tx_len;
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}
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static u32 d40_residue(struct d40_chan *d40c)
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{
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u32 num_elt;
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if (d40c->log_num != D40_PHY_CHAN)
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num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
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>> D40_MEM_LCSP2_ECNT_POS;
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else
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num_elt = (readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDELT) &
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D40_SREG_ELEM_PHY_ECNT_MASK) >>
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D40_SREG_ELEM_PHY_ECNT_POS;
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return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
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}
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static bool d40_tx_is_linked(struct d40_chan *d40c)
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{
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bool is_link;
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if (d40c->log_num != D40_PHY_CHAN)
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is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
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else
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is_link = readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDLNK) &
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D40_SREG_LNK_PHYS_LNK_MASK;
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return is_link;
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}
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static int d40_pause(struct dma_chan *chan)
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{
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struct d40_chan *d40c =
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container_of(chan, struct d40_chan, chan);
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int res = 0;
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unsigned long flags;
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spin_lock_irqsave(&d40c->lock, flags);
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res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
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if (res == 0) {
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if (d40c->log_num != D40_PHY_CHAN) {
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d40_config_set_event(d40c, false);
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/* Resume the other logical channels if any */
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if (d40_chan_has_events(d40c))
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res = d40_channel_execute_command(d40c,
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D40_DMA_RUN);
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}
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}
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spin_unlock_irqrestore(&d40c->lock, flags);
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return res;
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}
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static int d40_resume(struct dma_chan *chan)
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{
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struct d40_chan *d40c =
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container_of(chan, struct d40_chan, chan);
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int res = 0;
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unsigned long flags;
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spin_lock_irqsave(&d40c->lock, flags);
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if (d40c->base->rev == 0)
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if (d40c->log_num != D40_PHY_CHAN) {
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res = d40_channel_execute_command(d40c,
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D40_DMA_SUSPEND_REQ);
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goto no_suspend;
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}
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/* If bytes left to transfer or linked tx resume job */
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if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
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if (d40c->log_num != D40_PHY_CHAN)
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d40_config_set_event(d40c, true);
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res = d40_channel_execute_command(d40c, D40_DMA_RUN);
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}
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no_suspend:
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spin_unlock_irqrestore(&d40c->lock, flags);
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return res;
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}
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static void d40_tx_submit_log(struct d40_chan *d40c, struct d40_desc *d40d)
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{
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/* TODO: Write */
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}
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static void d40_tx_submit_phy(struct d40_chan *d40c, struct d40_desc *d40d)
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{
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struct d40_desc *d40d_prev = NULL;
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int i;
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u32 val;
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if (!list_empty(&d40c->queue))
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d40d_prev = d40_last_queued(d40c);
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else if (!list_empty(&d40c->active))
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d40d_prev = d40_first_active_get(d40c);
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if (!d40d_prev)
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return;
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/* Here we try to join this job with previous jobs */
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val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SSLNK);
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/* Figure out which link we're currently transmitting */
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for (i = 0; i < d40d_prev->lli_len; i++)
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if (val == d40d_prev->lli_phy.src[i].reg_lnk)
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break;
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val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SSELT) >> D40_SREG_ELEM_LOG_ECNT_POS;
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if (i == (d40d_prev->lli_len - 1) && val > 0) {
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/* Change the current one */
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writel(virt_to_phys(d40d->lli_phy.src),
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d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SSLNK);
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writel(virt_to_phys(d40d->lli_phy.dst),
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d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDLNK);
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d40d->is_hw_linked = true;
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} else if (i < d40d_prev->lli_len) {
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(void) dma_unmap_single(d40c->base->dev,
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virt_to_phys(d40d_prev->lli_phy.src),
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d40d_prev->lli_pool.size,
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DMA_TO_DEVICE);
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/* Keep the settings */
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val = d40d_prev->lli_phy.src[d40d_prev->lli_len - 1].reg_lnk &
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~D40_SREG_LNK_PHYS_LNK_MASK;
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d40d_prev->lli_phy.src[d40d_prev->lli_len - 1].reg_lnk =
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val | virt_to_phys(d40d->lli_phy.src);
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val = d40d_prev->lli_phy.dst[d40d_prev->lli_len - 1].reg_lnk &
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~D40_SREG_LNK_PHYS_LNK_MASK;
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d40d_prev->lli_phy.dst[d40d_prev->lli_len - 1].reg_lnk =
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val | virt_to_phys(d40d->lli_phy.dst);
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(void) dma_map_single(d40c->base->dev,
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d40d_prev->lli_phy.src,
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d40d_prev->lli_pool.size,
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DMA_TO_DEVICE);
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d40d->is_hw_linked = true;
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}
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}
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static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct d40_chan *d40c = container_of(tx->chan,
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@ -737,14 +888,28 @@ static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
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struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
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unsigned long flags;
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(void) d40_pause(&d40c->chan);
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spin_lock_irqsave(&d40c->lock, flags);
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tx->cookie = d40_assign_cookie(d40c, d40d);
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d40c->chan.cookie++;
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if (d40c->chan.cookie < 0)
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d40c->chan.cookie = 1;
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d40d->txd.cookie = d40c->chan.cookie;
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if (d40c->log_num == D40_PHY_CHAN)
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d40_tx_submit_phy(d40c, d40d);
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else
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d40_tx_submit_log(d40c, d40d);
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d40_desc_queue(d40c, d40d);
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spin_unlock_irqrestore(&d40c->lock, flags);
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(void) d40_resume(&d40c->chan);
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return tx->cookie;
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}
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@ -784,14 +949,20 @@ static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
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/* Add to active queue */
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d40_desc_submit(d40c, d40d);
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/* Initiate DMA job */
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d40_desc_load(d40c, d40d);
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/*
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* If this job is already linked in hw,
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* do not submit it.
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*/
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if (!d40d->is_hw_linked) {
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/* Initiate DMA job */
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d40_desc_load(d40c, d40d);
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/* Start dma job */
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err = d40_start(d40c);
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/* Start dma job */
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err = d40_start(d40c);
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if (err)
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return NULL;
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if (err)
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return NULL;
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}
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}
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return d40d;
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@ -1341,30 +1512,6 @@ static int d40_free_dma(struct d40_chan *d40c)
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return 0;
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}
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static int d40_pause(struct dma_chan *chan)
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{
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struct d40_chan *d40c =
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container_of(chan, struct d40_chan, chan);
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int res;
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unsigned long flags;
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spin_lock_irqsave(&d40c->lock, flags);
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res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
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if (res == 0) {
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if (d40c->log_num != D40_PHY_CHAN) {
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d40_config_set_event(d40c, false);
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/* Resume the other logical channels if any */
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if (d40_chan_has_events(d40c))
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res = d40_channel_execute_command(d40c,
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D40_DMA_RUN);
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}
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}
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spin_unlock_irqrestore(&d40c->lock, flags);
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return res;
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}
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static bool d40_is_paused(struct d40_chan *d40c)
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{
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bool is_paused = false;
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@ -1413,64 +1560,6 @@ _exit:
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}
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static bool d40_tx_is_linked(struct d40_chan *d40c)
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{
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bool is_link;
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if (d40c->log_num != D40_PHY_CHAN)
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is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
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else
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is_link = readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDLNK) &
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D40_SREG_LNK_PHYS_LNK_MASK;
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return is_link;
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}
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static u32 d40_residue(struct d40_chan *d40c)
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{
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u32 num_elt;
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if (d40c->log_num != D40_PHY_CHAN)
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num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
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>> D40_MEM_LCSP2_ECNT_POS;
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else
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num_elt = (readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDELT) &
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D40_SREG_ELEM_PHY_ECNT_MASK) >>
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D40_SREG_ELEM_PHY_ECNT_POS;
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return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
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}
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static int d40_resume(struct dma_chan *chan)
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{
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struct d40_chan *d40c =
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container_of(chan, struct d40_chan, chan);
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int res = 0;
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unsigned long flags;
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spin_lock_irqsave(&d40c->lock, flags);
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if (d40c->base->rev == 0)
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if (d40c->log_num != D40_PHY_CHAN) {
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res = d40_channel_execute_command(d40c,
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D40_DMA_SUSPEND_REQ);
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goto no_suspend;
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}
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/* If bytes left to transfer or linked tx resume job */
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if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
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if (d40c->log_num != D40_PHY_CHAN)
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d40_config_set_event(d40c, true);
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res = d40_channel_execute_command(d40c, D40_DMA_RUN);
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}
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no_suspend:
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spin_unlock_irqrestore(&d40c->lock, flags);
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return res;
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}
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static u32 stedma40_residue(struct dma_chan *chan)
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{
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struct d40_chan *d40c =
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@ -1607,7 +1696,7 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
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sgl_len,
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0,
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d40d->lli_phy.src,
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d40d->lli_phy.src_addr,
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virt_to_phys(d40d->lli_phy.src),
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d40c->src_def_cfg,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.src_info.psize);
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@ -1619,7 +1708,7 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
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sgl_len,
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0,
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d40d->lli_phy.dst,
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d40d->lli_phy.dst_addr,
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virt_to_phys(d40d->lli_phy.dst),
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d40c->dst_def_cfg,
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d40c->dma_cfg.dst_info.data_width,
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d40c->dma_cfg.dst_info.psize);
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@ -1679,6 +1768,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
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* use default configuration (memcpy)
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*/
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if (d40c->dma_cfg.channel_type == 0) {
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err = d40_config_memcpy(d40c);
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if (err) {
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dev_err(&d40c->chan.dev->device,
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@ -1957,7 +2047,7 @@ static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
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sgl_len,
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src_dev_addr,
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d40d->lli_phy.src,
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d40d->lli_phy.src_addr,
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virt_to_phys(d40d->lli_phy.src),
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d40c->src_def_cfg,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.src_info.psize);
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@ -1968,7 +2058,7 @@ static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
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sgl_len,
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dst_dev_addr,
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d40d->lli_phy.dst,
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d40d->lli_phy.dst_addr,
|
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virt_to_phys(d40d->lli_phy.dst),
|
||||
d40c->dst_def_cfg,
|
||||
d40c->dma_cfg.dst_info.data_width,
|
||||
d40c->dma_cfg.dst_info.psize);
|
||||
|
||||
@ -202,8 +202,6 @@ struct d40_phy_lli {
|
||||
*
|
||||
* @src: Register settings for src channel.
|
||||
* @dst: Register settings for dst channel.
|
||||
* @dst_addr: Physical destination address.
|
||||
* @src_addr: Physical source address.
|
||||
*
|
||||
* All DMA transfers have a source and a destination.
|
||||
*/
|
||||
@ -211,8 +209,6 @@ struct d40_phy_lli {
|
||||
struct d40_phy_lli_bidir {
|
||||
struct d40_phy_lli *src;
|
||||
struct d40_phy_lli *dst;
|
||||
dma_addr_t dst_addr;
|
||||
dma_addr_t src_addr;
|
||||
};
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user