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net: bcmgenet: add MDIO routines
This patch adds support for configuring the port multiplexer hardware which resides in front of the GENET Ethernet MAC controller. This allows us to support: - internal PHYs (using drivers/net/phy/bcm7xxx.c) - MoCA PHYs which are an entirely separate hardware block not covered here - external PHYs and switches Note that MoCA and switches are currently supported using the emulated "fixed PHY" driver. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Florian Fainelli
David S. Miller
parent
1c1008c793
commit
aa09677cba
464
drivers/net/ethernet/broadcom/genet/bcmmii.c
Normal file
464
drivers/net/ethernet/broadcom/genet/bcmmii.c
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@ -0,0 +1,464 @@
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/*
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* Broadcom GENET MDIO routines
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*
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* Copyright (c) 2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/wait.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/bitops.h>
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#include <linux/netdevice.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <linux/phy_fixed.h>
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#include <linux/brcmphy.h>
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#include <linux/of.h>
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#include <linux/of_net.h>
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#include <linux/of_mdio.h>
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#include "bcmgenet.h"
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/* read a value from the MII */
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static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
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{
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int ret;
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struct net_device *dev = bus->priv;
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struct bcmgenet_priv *priv = netdev_priv(dev);
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u32 reg;
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bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
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(location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
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/* Start MDIO transaction*/
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reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
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reg |= MDIO_START_BUSY;
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bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
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wait_event_timeout(priv->wq,
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!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
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& MDIO_START_BUSY),
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HZ / 100);
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ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
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if (ret & MDIO_READ_FAIL)
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return -EIO;
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return ret & 0xffff;
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}
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/* write a value to the MII */
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static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
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int location, u16 val)
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{
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struct net_device *dev = bus->priv;
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struct bcmgenet_priv *priv = netdev_priv(dev);
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u32 reg;
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bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
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(location << MDIO_REG_SHIFT) | (0xffff & val)),
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UMAC_MDIO_CMD);
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reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
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reg |= MDIO_START_BUSY;
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bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
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wait_event_timeout(priv->wq,
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!(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
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MDIO_START_BUSY),
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HZ / 100);
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return 0;
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}
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/* setup netdev link state when PHY link status change and
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* update UMAC and RGMII block when link up
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*/
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static void bcmgenet_mii_setup(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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struct phy_device *phydev = priv->phydev;
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u32 reg, cmd_bits = 0;
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unsigned int status_changed = 0;
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if (priv->old_link != phydev->link) {
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status_changed = 1;
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priv->old_link = phydev->link;
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}
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if (phydev->link) {
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/* program UMAC and RGMII block based on established link
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* speed, pause, and duplex.
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* the speed set in umac->cmd tell RGMII block which clock
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* 25MHz(100Mbps)/125MHz(1Gbps) to use for transmit.
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* receive clock is provided by PHY.
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*/
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reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
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reg &= ~OOB_DISABLE;
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reg |= RGMII_LINK;
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bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
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/* speed */
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if (phydev->speed == SPEED_1000)
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cmd_bits = UMAC_SPEED_1000;
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else if (phydev->speed == SPEED_100)
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cmd_bits = UMAC_SPEED_100;
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else
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cmd_bits = UMAC_SPEED_10;
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cmd_bits <<= CMD_SPEED_SHIFT;
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if (priv->old_duplex != phydev->duplex) {
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status_changed = 1;
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priv->old_duplex = phydev->duplex;
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}
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/* duplex */
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if (phydev->duplex != DUPLEX_FULL)
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cmd_bits |= CMD_HD_EN;
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if (priv->old_pause != phydev->pause) {
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status_changed = 1;
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priv->old_pause = phydev->pause;
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}
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/* pause capability */
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if (!phydev->pause)
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cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
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reg = bcmgenet_umac_readl(priv, UMAC_CMD);
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reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
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CMD_HD_EN |
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CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
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reg |= cmd_bits;
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bcmgenet_umac_writel(priv, reg, UMAC_CMD);
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}
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if (status_changed)
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phy_print_status(phydev);
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}
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void bcmgenet_mii_reset(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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if (priv->phydev) {
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phy_init_hw(priv->phydev);
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phy_start_aneg(priv->phydev);
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}
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}
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static void bcmgenet_ephy_power_up(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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u32 reg = 0;
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/* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
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if (!GENET_IS_V4(priv))
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return;
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reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
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reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
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reg |= EXT_GPHY_RESET;
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bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
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mdelay(2);
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reg &= ~EXT_GPHY_RESET;
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bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
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udelay(20);
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}
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static void bcmgenet_internal_phy_setup(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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u32 reg;
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/* Power up EPHY */
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bcmgenet_ephy_power_up(dev);
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/* enable APD */
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reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
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reg |= EXT_PWR_DN_EN_LD;
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bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
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bcmgenet_mii_reset(dev);
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}
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static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
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{
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u32 reg;
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/* Speed settings are set in bcmgenet_mii_setup() */
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reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
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reg |= LED_ACT_SOURCE_MAC;
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bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
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}
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int bcmgenet_mii_config(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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struct phy_device *phydev = priv->phydev;
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struct device *kdev = &priv->pdev->dev;
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const char *phy_name = NULL;
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u32 id_mode_dis = 0;
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u32 port_ctrl;
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u32 reg;
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priv->ext_phy = !phy_is_internal(priv->phydev) &&
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(priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
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if (phy_is_internal(priv->phydev))
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priv->phy_interface = PHY_INTERFACE_MODE_NA;
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switch (priv->phy_interface) {
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case PHY_INTERFACE_MODE_NA:
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case PHY_INTERFACE_MODE_MOCA:
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/* Irrespective of the actually configured PHY speed (100 or
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* 1000) GENETv4 only has an internal GPHY so we will just end
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* up masking the Gigabit features from what we support, not
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* switching to the EPHY
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*/
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if (GENET_IS_V4(priv))
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port_ctrl = PORT_MODE_INT_GPHY;
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else
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port_ctrl = PORT_MODE_INT_EPHY;
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bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
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if (phy_is_internal(priv->phydev)) {
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phy_name = "internal PHY";
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bcmgenet_internal_phy_setup(dev);
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} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
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phy_name = "MoCA";
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bcmgenet_moca_phy_setup(priv);
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}
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break;
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case PHY_INTERFACE_MODE_MII:
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phy_name = "external MII";
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phydev->supported &= PHY_BASIC_FEATURES;
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bcmgenet_sys_writel(priv,
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PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
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break;
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case PHY_INTERFACE_MODE_REVMII:
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phy_name = "external RvMII";
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/* of_mdiobus_register took care of reading the 'max-speed'
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* PHY property for us, effectively limiting the PHY supported
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* capabilities, use that knowledge to also configure the
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* Reverse MII interface correctly.
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*/
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if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
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PHY_BASIC_FEATURES)
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port_ctrl = PORT_MODE_EXT_RVMII_25;
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else
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port_ctrl = PORT_MODE_EXT_RVMII_50;
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bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
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break;
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case PHY_INTERFACE_MODE_RGMII:
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/* RGMII_NO_ID: TXC transitions at the same time as TXD
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* (requires PCB or receiver-side delay)
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* RGMII: Add 2ns delay on TXC (90 degree shift)
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*
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* ID is implicitly disabled for 100Mbps (RG)MII operation.
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*/
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id_mode_dis = BIT(16);
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/* fall through */
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case PHY_INTERFACE_MODE_RGMII_TXID:
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if (id_mode_dis)
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phy_name = "external RGMII (no delay)";
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else
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phy_name = "external RGMII (TX delay)";
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reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
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reg |= RGMII_MODE_EN | id_mode_dis;
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bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
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bcmgenet_sys_writel(priv,
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PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
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break;
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default:
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dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
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return -EINVAL;
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}
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dev_info(kdev, "configuring instance for %s\n", phy_name);
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return 0;
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}
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static int bcmgenet_mii_probe(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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struct phy_device *phydev;
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unsigned int phy_flags;
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int ret;
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if (priv->phydev) {
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pr_info("PHY already attached\n");
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return 0;
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}
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if (priv->phy_dn)
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phydev = of_phy_connect(dev, priv->phy_dn,
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bcmgenet_mii_setup, 0,
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priv->phy_interface);
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else
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phydev = of_phy_connect_fixed_link(dev,
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bcmgenet_mii_setup,
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priv->phy_interface);
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if (!phydev) {
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pr_err("could not attach to PHY\n");
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return -ENODEV;
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}
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priv->old_link = -1;
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priv->old_duplex = -1;
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priv->old_pause = -1;
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priv->phydev = phydev;
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/* Configure port multiplexer based on what the probed PHY device since
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* reading the 'max-speed' property determines the maximum supported
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* PHY speed which is needed for bcmgenet_mii_config() to configure
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* things appropriately.
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*/
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ret = bcmgenet_mii_config(dev);
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if (ret) {
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phy_disconnect(priv->phydev);
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return ret;
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}
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phy_flags = PHY_BRCM_100MBPS_WAR;
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/* workarounds are only needed for 100Mpbs PHYs, and
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* never on GENET V1 hardware
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*/
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if ((phydev->supported & PHY_GBIT_FEATURES) || GENET_IS_V1(priv))
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phy_flags = 0;
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phydev->dev_flags |= phy_flags;
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phydev->advertising = phydev->supported;
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/* The internal PHY has its link interrupts routed to the
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* Ethernet MAC ISRs
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*/
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if (phy_is_internal(priv->phydev))
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priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
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else
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priv->mii_bus->irq[phydev->addr] = PHY_POLL;
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||||||
|
pr_info("attached PHY at address %d [%s]\n",
|
||||||
|
phydev->addr, phydev->drv->name);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
|
||||||
|
{
|
||||||
|
struct mii_bus *bus;
|
||||||
|
|
||||||
|
if (priv->mii_bus)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
priv->mii_bus = mdiobus_alloc();
|
||||||
|
if (!priv->mii_bus) {
|
||||||
|
pr_err("failed to allocate\n");
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
bus = priv->mii_bus;
|
||||||
|
bus->priv = priv->dev;
|
||||||
|
bus->name = "bcmgenet MII bus";
|
||||||
|
bus->parent = &priv->pdev->dev;
|
||||||
|
bus->read = bcmgenet_mii_read;
|
||||||
|
bus->write = bcmgenet_mii_write;
|
||||||
|
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
|
||||||
|
priv->pdev->name, priv->pdev->id);
|
||||||
|
|
||||||
|
bus->irq = kzalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
|
||||||
|
if (!bus->irq) {
|
||||||
|
mdiobus_free(priv->mii_bus);
|
||||||
|
return -ENOMEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
|
||||||
|
{
|
||||||
|
struct device_node *dn = priv->pdev->dev.of_node;
|
||||||
|
struct device *kdev = &priv->pdev->dev;
|
||||||
|
struct device_node *mdio_dn;
|
||||||
|
char *compat;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
|
||||||
|
if (!compat)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
mdio_dn = of_find_compatible_node(dn, NULL, compat);
|
||||||
|
kfree(compat);
|
||||||
|
if (!mdio_dn) {
|
||||||
|
dev_err(kdev, "unable to find MDIO bus node\n");
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = of_mdiobus_register(priv->mii_bus, mdio_dn);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(kdev, "failed to register MDIO bus\n");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Fetch the PHY phandle */
|
||||||
|
priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
|
||||||
|
|
||||||
|
/* Get the link mode */
|
||||||
|
priv->phy_interface = of_get_phy_mode(dn);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int bcmgenet_mii_init(struct net_device *dev)
|
||||||
|
{
|
||||||
|
struct bcmgenet_priv *priv = netdev_priv(dev);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = bcmgenet_mii_alloc(priv);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = bcmgenet_mii_of_init(priv);
|
||||||
|
if (ret)
|
||||||
|
goto out_free;
|
||||||
|
|
||||||
|
ret = bcmgenet_mii_probe(dev);
|
||||||
|
if (ret)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
out:
|
||||||
|
mdiobus_unregister(priv->mii_bus);
|
||||||
|
out_free:
|
||||||
|
kfree(priv->mii_bus->irq);
|
||||||
|
mdiobus_free(priv->mii_bus);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
void bcmgenet_mii_exit(struct net_device *dev)
|
||||||
|
{
|
||||||
|
struct bcmgenet_priv *priv = netdev_priv(dev);
|
||||||
|
|
||||||
|
mdiobus_unregister(priv->mii_bus);
|
||||||
|
kfree(priv->mii_bus->irq);
|
||||||
|
mdiobus_free(priv->mii_bus);
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue
Block a user