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pinctrl: Bulk conversion to generic_handle_domain_irq()

Browse Source 
Wherever possible, replace constructs that match either
generic_handle_irq(irq_find_mapping()) or
generic_handle_irq(irq_linear_revmap()) to a single call to
generic_handle_domain_irq().

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Marc Zyngier 2021-05-04 17:42:18 +01:00
parent dbd1c54fc8
commit a9cb09b7be
28 changed files with 64 additions and 100 deletions
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5
drivers/pinctrl/actions/pinctrl-owl.c
View File

@ -833,7 +833,7 @@ static void owl_gpio_irq_handler(struct irq_desc *desc)
unsigned int parent = irq_desc_get_irq(desc);
const struct owl_gpio_port *port;
void __iomem *base;
unsigned int pin, irq, offset = 0, i;
unsigned int pin, offset = 0, i;
unsigned long pending_irq;
chained_irq_enter(chip, desc);
@ -849,8 +849,7 @@ static void owl_gpio_irq_handler(struct irq_desc *desc)
pending_irq = readl_relaxed(base + port->intc_pd);
for_each_set_bit(pin, &pending_irq, port->pins) {
irq = irq_find_mapping(domain, offset + pin);
generic_handle_irq(irq);
generic_handle_domain_irq(domain, offset + pin);
/* clear pending interrupt */
owl_gpio_update_reg(base + port->intc_pd, pin, true);

4
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@ -395,8 +395,8 @@ static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
events &= pc->enabled_irq_map[bank];
for_each_set_bit(offset, &events, 32) {
gpio = (32 * bank) + offset;
generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
gpio));
generic_handle_domain_irq(pc->gpio_chip.irq.domain,
gpio);
}
}

3
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
View File

@ -176,7 +176,6 @@ static void iproc_gpio_irq_handler(struct irq_desc *desc)
for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
unsigned pin = NGPIOS_PER_BANK * i + bit;
int child_irq = irq_find_mapping(gc->irq.domain, pin);
/*
* Clear the interrupt before invoking the
@ -185,7 +184,7 @@ static void iproc_gpio_irq_handler(struct irq_desc *desc)
writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
IPROC_GPIO_INT_CLR_OFFSET);
generic_handle_irq(child_irq);
generic_handle_domain_irq(gc->irq.domain, pin);
}
}

3
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
View File

@ -155,8 +155,7 @@ static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
int_bits = level | event;
for_each_set_bit(bit, &int_bits, gc->ngpio)
generic_handle_irq(
irq_linear_revmap(gc->irq.domain, bit));
generic_handle_domain_irq(gc->irq.domain, bit);
}
return int_bits ? IRQ_HANDLED : IRQ_NONE;

7
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -1444,7 +1444,6 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
u32 base, pin;
void __iomem *reg;
unsigned long pending;
unsigned int virq;
/* check from GPIO controller which pin triggered the interrupt */
for (base = 0; base < vg->chip.ngpio; base += 32) {
@ -1460,10 +1459,8 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
raw_spin_lock(&byt_lock);
pending = readl(reg);
raw_spin_unlock(&byt_lock);
for_each_set_bit(pin, &pending, 32) {
virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
generic_handle_irq(virq);
}
for_each_set_bit(pin, &pending, 32)
generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
}
chip->irq_eoi(data);
}

5
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -1409,11 +1409,10 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
raw_spin_unlock_irqrestore(&chv_lock, flags);
for_each_set_bit(intr_line, &pending, community->nirqs) {
unsigned int irq, offset;
unsigned int offset;
offset = cctx->intr_lines[intr_line];
irq = irq_find_mapping(gc->irq.domain, offset);
generic_handle_irq(irq);
generic_handle_domain_irq(gc->irq.domain, offset);
}
chained_irq_exit(chip, desc);

8
drivers/pinctrl/intel/pinctrl-lynxpoint.c
View File

@ -653,12 +653,8 @@ static void lp_gpio_irq_handler(struct irq_desc *desc)
/* Only interrupts that are enabled */
pending = ioread32(reg) & ioread32(ena);
for_each_set_bit(pin, &pending, 32) {
unsigned int irq;
irq = irq_find_mapping(lg->chip.irq.domain, base + pin);
generic_handle_irq(irq);
}
for_each_set_bit(pin, &pending, 32)
generic_handle_domain_irq(lg->chip.irq.domain, base + pin);
}
chip->irq_eoi(data);
}

5
drivers/pinctrl/mediatek/mtk-eint.c
View File

@ -319,7 +319,7 @@ static void mtk_eint_irq_handler(struct irq_desc *desc)
struct irq_chip *chip = irq_desc_get_chip(desc);
struct mtk_eint *eint = irq_desc_get_handler_data(desc);
unsigned int status, eint_num;
int offset, mask_offset, index, virq;
int offset, mask_offset, index;
void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat);
int dual_edge, start_level, curr_level;
@ -331,7 +331,6 @@ static void mtk_eint_irq_handler(struct irq_desc *desc)
offset = __ffs(status);
mask_offset = eint_num >> 5;
index = eint_num + offset;
virq = irq_find_mapping(eint->domain, index);
status &= ~BIT(offset);
/*
@ -361,7 +360,7 @@ static void mtk_eint_irq_handler(struct irq_desc *desc)
index);
}
generic_handle_irq(virq);
generic_handle_domain_irq(eint->domain, index);
if (dual_edge) {
curr_level = mtk_eint_flip_edge(eint, index);

2
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View File

@ -815,7 +815,7 @@ static void nmk_gpio_irq_handler(struct irq_desc *desc)
while (status) {
int bit = __ffs(status);
generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));
generic_handle_domain_irq(chip->irq.domain, bit);
status &= ~BIT(bit);
}

2
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View File

@ -231,7 +231,7 @@ static void npcmgpio_irq_handler(struct irq_desc *desc)
sts &= en;
for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK)
generic_handle_irq(irq_linear_revmap(gc->irq.domain, bit));
generic_handle_domain_irq(gc->irq.domain, bit);
chained_irq_exit(chip, desc);
}

6
drivers/pinctrl/pinctrl-amd.c
View File

@ -621,14 +621,12 @@ static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
if (!(regval & PIN_IRQ_PENDING) ||
!(regval & BIT(INTERRUPT_MASK_OFF)))
continue;
irq = irq_find_mapping(gc->irq.domain, irqnr + i);
if (irq != 0)
generic_handle_irq(irq);
generic_handle_domain_irq(gc->irq.domain, irqnr + i);
/* Clear interrupt.
* We must read the pin register again, in case the
* value was changed while executing
* generic_handle_irq() above.
* generic_handle_domain_irq() above.
* If we didn't find a mapping for the interrupt,
* disable it in order to avoid a system hang caused
* by an interrupt storm.

6
drivers/pinctrl/pinctrl-at91.c
View File

@ -1712,10 +1712,8 @@ static void gpio_irq_handler(struct irq_desc *desc)
continue;
}
for_each_set_bit(n, &isr, BITS_PER_LONG) {
generic_handle_irq(irq_find_mapping(
gpio_chip->irq.domain, n));
}
for_each_set_bit(n, &isr, BITS_PER_LONG)
generic_handle_domain_irq(gpio_chip->irq.domain, n);
}
chained_irq_exit(chip, desc);
/* now it may re-trigger */

2
drivers/pinctrl/pinctrl-equilibrium.c
View File

@ -155,7 +155,7 @@ static void eqbr_irq_handler(struct irq_desc *desc)
pins = readl(gctrl->membase + GPIO_IRNCR);
for_each_set_bit(offset, &pins, gc->ngpio)
generic_handle_irq(irq_find_mapping(gc->irq.domain, offset));
generic_handle_domain_irq(gc->irq.domain, offset);
chained_irq_exit(ic, desc);
}

2
drivers/pinctrl/pinctrl-ingenic.c
View File

@ -3080,7 +3080,7 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc)
flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
for_each_set_bit(i, &flag, 32)
generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
generic_handle_domain_irq(gc->irq.domain, i);
chained_irq_exit(irq_chip, desc);
}

2
drivers/pinctrl/pinctrl-microchip-sgpio.c
View File

@ -673,7 +673,7 @@ static void sgpio_irq_handler(struct irq_desc *desc)
for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
gpio = sgpio_addr_to_pin(priv, port, bit);
generic_handle_irq(irq_linear_revmap(chip->irq.domain, gpio));
generic_handle_domain_irq(chip->irq.domain, gpio);
}
chained_irq_exit(parent_chip, desc);

3
drivers/pinctrl/pinctrl-ocelot.c
View File

@ -1290,8 +1290,7 @@ static void ocelot_irq_handler(struct irq_desc *desc)
for_each_set_bit(irq, &irqs,
min(32U, info->desc->npins - 32 * i))
generic_handle_irq(irq_linear_revmap(chip->irq.domain,
irq + 32 * i));
generic_handle_domain_irq(chip->irq.domain, irq + 32 * i);
chained_irq_exit(parent_chip, desc);
}

2
drivers/pinctrl/pinctrl-oxnas.c
View File

@ -1055,7 +1055,7 @@ static void oxnas_gpio_irq_handler(struct irq_desc *desc)
stat = readl(bank->reg_base + IRQ_PENDING);
for_each_set_bit(pin, &stat, BITS_PER_LONG)
generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
generic_handle_domain_irq(gc->irq.domain, pin);
chained_irq_exit(chip, desc);
}

2
drivers/pinctrl/pinctrl-pic32.c
View File

@ -2101,7 +2101,7 @@ static void pic32_gpio_irq_handler(struct irq_desc *desc)
pending = pic32_gpio_get_pending(gc, stat);
for_each_set_bit(pin, &pending, BITS_PER_LONG)
generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
generic_handle_domain_irq(gc->irq.domain, pin);
chained_irq_exit(chip, desc);
}

2
drivers/pinctrl/pinctrl-pistachio.c
View File

@ -1306,7 +1306,7 @@ static void pistachio_gpio_irq_handler(struct irq_desc *desc)
pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
gpio_readl(bank, GPIO_INTERRUPT_EN);
for_each_set_bit(pin, &pending, 16)
generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
generic_handle_domain_irq(gc->irq.domain, pin);
chained_irq_exit(chip, desc);
}

15
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -2951,18 +2951,11 @@ static void rockchip_irq_demux(struct irq_desc *desc)
pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
while (pend) {
unsigned int irq, virq;
unsigned int irq;
int ret;
irq = __ffs(pend);
pend &= ~BIT(irq);
virq = irq_find_mapping(bank->domain, irq);
if (!virq) {
dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
continue;
}
dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
/*
* Triggering IRQ on both rising and falling edge
@ -2993,7 +2986,9 @@ static void rockchip_irq_demux(struct irq_desc *desc)
} while ((data & BIT(irq)) != (data_old & BIT(irq)));
}
generic_handle_irq(virq);
ret = generic_handle_domain_irq(bank->domain, irq);
if (unlikely(ret))
dev_err_ratelimited(bank->drvdata->dev, "unmapped irq %d\n", irq);
}
chained_irq_exit(chip, desc);

4
drivers/pinctrl/pinctrl-single.c
View File

@ -1491,8 +1491,8 @@ static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
mask = pcs->read(pcswi->reg);
raw_spin_unlock(&pcs->lock);
if (mask & pcs_soc->irq_status_mask) {
generic_handle_irq(irq_find_mapping(pcs->domain,
pcswi->hwirq));
generic_handle_domain_irq(pcs->domain,
pcswi->hwirq);
count++;
}
}

2
drivers/pinctrl/pinctrl-st.c
View File

@ -1420,7 +1420,7 @@ static void __gpio_irq_handler(struct st_gpio_bank *bank)
continue;
}
generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n));
generic_handle_domain_irq(bank->gpio_chip.irq.domain, n);
}
}
}

4
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -1177,7 +1177,6 @@ static void msm_gpio_irq_handler(struct irq_desc *desc)
const struct msm_pingroup *g;
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
struct irq_chip *chip = irq_desc_get_chip(desc);
int irq_pin;
int handled = 0;
u32 val;
int i;
@ -1192,8 +1191,7 @@ static void msm_gpio_irq_handler(struct irq_desc *desc)
g = &pctrl->soc->groups[i];
val = msm_readl_intr_status(pctrl, g);
if (val & BIT(g->intr_status_bit)) {
irq_pin = irq_find_mapping(gc->irq.domain, i);
generic_handle_irq(irq_pin);
generic_handle_domain_irq(gc->irq.domain, i);
handled++;
}
}

15
drivers/pinctrl/samsung/pinctrl-exynos.c
View File

@ -246,7 +246,8 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
{
struct samsung_pinctrl_drv_data *d = data;
struct samsung_pin_bank *bank = d->pin_banks;
unsigned int svc, group, pin, virq;
unsigned int svc, group, pin;
int ret;
svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
group = EXYNOS_SVC_GROUP(svc);
@ -256,10 +257,10 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
return IRQ_HANDLED;
bank += (group - 1);
virq = irq_linear_revmap(bank->irq_domain, pin);
if (!virq)
ret = generic_handle_domain_irq(bank->irq_domain, pin);
if (ret)
return IRQ_NONE;
generic_handle_irq(virq);
return IRQ_HANDLED;
}
@ -473,12 +474,10 @@ static void exynos_irq_eint0_15(struct irq_desc *desc)
struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
struct samsung_pin_bank *bank = eintd->bank;
struct irq_chip *chip = irq_desc_get_chip(desc);
int eint_irq;
chained_irq_enter(chip, desc);
eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
generic_handle_irq(eint_irq);
generic_handle_domain_irq(bank->irq_domain, eintd->irq);
chained_irq_exit(chip, desc);
}
@ -490,7 +489,7 @@ static inline void exynos_irq_demux_eint(unsigned int pend,
while (pend) {
irq = fls(pend) - 1;
generic_handle_irq(irq_find_mapping(domain, irq));
generic_handle_domain_irq(domain, irq);
pend &= ~(1 << irq);
}
}

25
drivers/pinctrl/samsung/pinctrl-s3c24xx.c
View File

@ -234,14 +234,12 @@ static void s3c2410_demux_eint0_3(struct irq_desc *desc)
{
struct irq_data *data = irq_desc_get_irq_data(desc);
struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
unsigned int virq;
int ret;
/* the first 4 eints have a simple 1 to 1 mapping */
virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
ret = generic_handle_domain_irq(eint_data->domains[data->hwirq], data->hwirq);
/* Something must be really wrong if an unmapped EINT is unmasked */
BUG_ON(!virq);
generic_handle_irq(virq);
BUG_ON(ret);
}
/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */
@ -290,16 +288,14 @@ static void s3c2412_demux_eint0_3(struct irq_desc *desc)
struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
struct irq_data *data = irq_desc_get_irq_data(desc);
struct irq_chip *chip = irq_data_get_irq_chip(data);
unsigned int virq;
int ret;
chained_irq_enter(chip, desc);
/* the first 4 eints have a simple 1 to 1 mapping */
virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
ret = generic_handle_domain_irq(eint_data->domains[data->hwirq], data->hwirq);
/* Something must be really wrong if an unmapped EINT is unmasked */
BUG_ON(!virq);
generic_handle_irq(virq);
BUG_ON(ret);
chained_irq_exit(chip, desc);
}
@ -364,15 +360,14 @@ static inline void s3c24xx_demux_eint(struct irq_desc *desc,
pend &= range;
while (pend) {
unsigned int virq, irq;
unsigned int irq;
int ret;
irq = __ffs(pend);
pend &= ~(1 << irq);
virq = irq_linear_revmap(data->domains[irq], irq - offset);
ret = generic_handle_domain_irq(data->domains[irq], irq - offset);
/* Something is really wrong if an unmapped EINT is unmasked */
BUG_ON(!virq);
generic_handle_irq(virq);
BUG_ON(ret);
}
chained_irq_exit(chip, desc);

17
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
View File

@ -414,7 +414,7 @@ static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
unsigned int svc;
unsigned int group;
unsigned int pin;
unsigned int virq;
int ret;
svc = readl(drvdata->virt_base + SERVICE_REG);
group = SVC_GROUP(svc);
@ -431,14 +431,12 @@ static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
pin -= 8;
}
virq = irq_linear_revmap(data->domains[group], pin);
ret = generic_handle_domain_irq(data->domains[group], pin);
/*
* Something must be really wrong if an unmapped EINT
* was unmasked...
*/
BUG_ON(!virq);
generic_handle_irq(virq);
BUG_ON(ret);
} while (1);
chained_irq_exit(chip, desc);
@ -607,18 +605,17 @@ static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range)
pend &= range;
while (pend) {
unsigned int virq, irq;
unsigned int irq;
int ret;
irq = fls(pend) - 1;
pend &= ~(1 << irq);
virq = irq_linear_revmap(data->domains[irq], data->pins[irq]);
ret = generic_handle_domain_irq(data->domains[irq], data->pins[irq]);
/*
* Something must be really wrong if an unmapped EINT
* was unmasked...
*/
BUG_ON(!virq);
generic_handle_irq(virq);
BUG_ON(ret);
}
chained_irq_exit(chip, desc);

3
drivers/pinctrl/spear/pinctrl-plgpio.c
View File

@ -400,8 +400,7 @@ static void plgpio_irq_handler(struct irq_desc *desc)
/* get correct irq line number */
pin = i * MAX_GPIO_PER_REG + pin;
generic_handle_irq(
irq_find_mapping(gc->irq.domain, pin));
generic_handle_domain_irq(gc->irq.domain, pin);
}
}
chained_irq_exit(irqchip, desc);

8
drivers/pinctrl/sunxi/pinctrl-sunxi.c
View File

@ -1149,11 +1149,9 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
if (val) {
int irqoffset;
for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
int pin_irq = irq_find_mapping(pctl->domain,
bank * IRQ_PER_BANK + irqoffset);
generic_handle_irq(pin_irq);
}
for_each_set_bit(irqoffset, &val, IRQ_PER_BANK)
generic_handle_domain_irq(pctl->domain,
bank * IRQ_PER_BANK + irqoffset);
}
chained_irq_exit(chip, desc);