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MN10300: Make the use of PIDR to mark TLB entries controllable
Make controllable the use of the PIDR register to mark TLB entries as belonging to particular processes. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
This commit is contained in:
Akira Takeuchi
David Howells
parent
492e675116
commit
a9bc60ebfd
@ -142,6 +142,9 @@ config FPU
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source "arch/mn10300/mm/Kconfig.cache"
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config MN10300_TLB_USE_PIDR
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def_bool y
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menu "Memory layout options"
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config KERNEL_RAM_BASE_ADDRESS
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@ -27,28 +27,22 @@
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#include <asm/tlbflush.h>
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#include <asm-generic/mm_hooks.h>
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#define MMU_CONTEXT_TLBPID_NR 256
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#define MMU_CONTEXT_TLBPID_MASK 0x000000ffUL
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#define MMU_CONTEXT_VERSION_MASK 0xffffff00UL
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#define MMU_CONTEXT_FIRST_VERSION 0x00000100UL
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#define MMU_NO_CONTEXT 0x00000000UL
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extern unsigned long mmu_context_cache[NR_CPUS];
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#define mm_context(mm) (mm->context.tlbpid[smp_processor_id()])
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#define MMU_CONTEXT_TLBPID_LOCK_NR 0
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#define enter_lazy_tlb(mm, tsk) do {} while (0)
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#ifdef CONFIG_SMP
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#define cpu_ran_vm(cpu, mm) \
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cpumask_set_cpu((cpu), mm_cpumask(mm))
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#define cpu_maybe_ran_vm(cpu, mm) \
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cpumask_test_and_set_cpu((cpu), mm_cpumask(mm))
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#else
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#define cpu_ran_vm(cpu, mm) do {} while (0)
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#define cpu_maybe_ran_vm(cpu, mm) true
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_MN10300_TLB_USE_PIDR
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extern unsigned long mmu_context_cache[NR_CPUS];
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#define mm_context(mm) (mm->context.tlbpid[smp_processor_id()])
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/*
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* allocate an MMU context
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/**
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* allocate_mmu_context - Allocate storage for the arch-specific MMU data
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* @mm: The userspace VM context being set up
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*/
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static inline unsigned long allocate_mmu_context(struct mm_struct *mm)
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{
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@ -100,35 +94,42 @@ static inline int init_new_context(struct task_struct *tsk,
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return 0;
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}
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/*
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* destroy context related info for an mm_struct that is about to be put to
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* rest
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*/
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#define destroy_context(mm) do { } while (0)
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/*
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* after we have set current->mm to a new value, this activates the context for
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* the new mm so we see the new mappings.
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*/
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static inline void activate_context(struct mm_struct *mm, int cpu)
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static inline void activate_context(struct mm_struct *mm)
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{
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PIDR = get_mmu_context(mm) & MMU_CONTEXT_TLBPID_MASK;
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}
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#else /* CONFIG_MN10300_TLB_USE_PIDR */
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/*
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* change between virtual memory sets
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#define init_new_context(tsk, mm) (0)
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#define activate_context(mm) local_flush_tlb()
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#endif /* CONFIG_MN10300_TLB_USE_PIDR */
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/**
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* destroy_context - Destroy mm context information
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* @mm: The MM being destroyed.
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*
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* Destroy context related info for an mm_struct that is about to be put to
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* rest
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*/
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#define destroy_context(mm) do {} while (0)
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/**
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* switch_mm - Change between userspace virtual memory contexts
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* @prev: The outgoing MM context.
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* @next: The incoming MM context.
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* @tsk: The incoming task.
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*/
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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int cpu = smp_processor_id();
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if (prev != next) {
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cpu_ran_vm(cpu, next);
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activate_context(next, cpu);
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PTBR = (unsigned long) next->pgd;
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} else if (!cpu_maybe_ran_vm(cpu, next)) {
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activate_context(next, cpu);
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activate_context(next);
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}
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}
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@ -13,6 +13,12 @@
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#include <asm/processor.h>
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struct tlb_state {
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struct mm_struct *active_mm;
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int state;
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};
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DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
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/**
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* local_flush_tlb - Flush the current MM's entries from the local CPU's TLBs
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*/
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@ -31,20 +37,51 @@ static inline void local_flush_tlb(void)
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/**
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* local_flush_tlb_all - Flush all entries from the local CPU's TLBs
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*/
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#define local_flush_tlb_all() local_flush_tlb()
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static inline void local_flush_tlb_all(void)
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{
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local_flush_tlb();
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}
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/**
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* local_flush_tlb_one - Flush one entry from the local CPU's TLBs
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*/
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#define local_flush_tlb_one(addr) local_flush_tlb()
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static inline void local_flush_tlb_one(unsigned long addr)
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{
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local_flush_tlb();
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}
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/**
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* local_flush_tlb_page - Flush a page's entry from the local CPU's TLBs
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* @mm: The MM to flush for
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* @addr: The address of the target page in RAM (not its page struct)
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*/
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extern void local_flush_tlb_page(struct mm_struct *mm, unsigned long addr);
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static inline
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void local_flush_tlb_page(struct mm_struct *mm, unsigned long addr)
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{
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unsigned long pteu, flags, cnx;
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addr &= PAGE_MASK;
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local_irq_save(flags);
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cnx = 1;
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#ifdef CONFIG_MN10300_TLB_USE_PIDR
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cnx = mm->context.tlbpid[smp_processor_id()];
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#endif
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if (cnx) {
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pteu = addr;
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#ifdef CONFIG_MN10300_TLB_USE_PIDR
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pteu |= cnx & xPTEU_PID;
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#endif
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IPTEU = pteu;
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DPTEU = pteu;
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if (IPTEL & xPTEL_V)
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IPTEL = 0;
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if (DPTEL & xPTEL_V)
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DPTEL = 0;
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}
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local_irq_restore(flags);
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}
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/*
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* TLB flushing:
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@ -13,40 +13,15 @@
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#ifdef CONFIG_MN10300_TLB_USE_PIDR
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/*
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* list of the MMU contexts last allocated on each CPU
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*/
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unsigned long mmu_context_cache[NR_CPUS] = {
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[0 ... NR_CPUS - 1] = MMU_CONTEXT_FIRST_VERSION * 2 - 1,
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[0 ... NR_CPUS - 1] =
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MMU_CONTEXT_FIRST_VERSION * 2 - (1 - MMU_CONTEXT_TLBPID_LOCK_NR),
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};
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/*
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* flush the specified TLB entry
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*/
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void local_flush_tlb_page(struct mm_struct *mm, unsigned long addr)
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{
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unsigned long pteu, cnx, flags;
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addr &= PAGE_MASK;
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/* make sure the context doesn't migrate and defend against
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* interference from vmalloc'd regions */
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local_irq_save(flags);
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cnx = mm_context(mm);
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if (cnx != MMU_NO_CONTEXT) {
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pteu = addr | (cnx & 0x000000ffUL);
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IPTEU = pteu;
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DPTEU = pteu;
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if (IPTEL & xPTEL_V)
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IPTEL = 0;
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if (DPTEL & xPTEL_V)
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DPTEL = 0;
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}
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local_irq_restore(flags);
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}
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#endif /* CONFIG_MN10300_TLB_USE_PIDR */
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/*
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* preemptively set a TLB entry
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@ -63,10 +38,16 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t *pte
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* interference from vmalloc'd regions */
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local_irq_save(flags);
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cnx = ~MMU_NO_CONTEXT;
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#ifdef CONFIG_MN10300_TLB_USE_PIDR
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cnx = mm_context(vma->vm_mm);
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#endif
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if (cnx != MMU_NO_CONTEXT) {
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pteu = addr | (cnx & 0x000000ffUL);
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pteu = addr;
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#ifdef CONFIG_MN10300_TLB_USE_PIDR
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pteu |= cnx & MMU_CONTEXT_TLBPID_MASK;
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#endif
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if (!(pte_val(pte) & _PAGE_NX)) {
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IPTEU = pteu;
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if (IPTEL & xPTEL_V)
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