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pinctrl: qcom: ipq4019: fix register offsets

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For this SoC the register offsets changed from previous versions to be
separated by a larger amount.

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Björn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Matthew McClintock 2016-03-23 17:04:58 -05:00 committed by Linus Walleij
parent cdbac7349f
commit a9b0b1fe9e
1 changed files with 5 additions and 5 deletions
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10
drivers/pinctrl/qcom/pinctrl-ipq4019.c
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@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99);
qca_mux_##f14 \ qca_mux_##f14 \
}, \ }, \
.nfuncs = 15, \ .nfuncs = 15, \
.ctl_reg = 0x1000 + 0x10 * id, \ .ctl_reg = 0x0 + 0x1000 * id, \
.io_reg = 0x1004 + 0x10 * id, \ .io_reg = 0x4 + 0x1000 * id, \
.intr_cfg_reg = 0x1008 + 0x10 * id, \ .intr_cfg_reg = 0x8 + 0x1000 * id, \
.intr_status_reg = 0x100c + 0x10 * id, \ .intr_status_reg = 0xc + 0x1000 * id, \
.intr_target_reg = 0x400 + 0x4 * id, \ .intr_target_reg = 0x8 + 0x1000 * id, \
.mux_bit = 2, \ .mux_bit = 2, \
.pull_bit = 0, \ .pull_bit = 0, \
.drv_bit = 6, \ .drv_bit = 6, \