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arm-cci: Add CCI-500 PMU support
CCI-500 provides 8 event counters which can count any of the supported events independently. The PMU event id is a 9-bit value made of two parts. bits [8:5] - Source port 0x0-0x6 Slave Ports 0x8-0xD Master Ports 0xf Global Events to CCI 0x7,0xe Reserved bits [0:4] - Event code (specific to each type of port) The generic CCI-500 controlling interface remains the same with CCI-400. However there are some differences in the PMU event counters. - No cycle counter - Upto 8 counters(4 in CCI-400) - Each counter area is 64K(4K in CCI400) - The counter0 starts at offset 0x10000 from the base of CCI Cc: Punit Agrawal <punit.agrawal@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@ -31,8 +31,9 @@ specific to ARM.
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- compatible
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Usage: required
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Value type: <string>
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Definition: must be set to
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Definition: must contain one of the following:
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"arm,cci-400"
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"arm,cci-500"
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- reg
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Usage: required
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@ -99,6 +100,7 @@ specific to ARM.
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"arm,cci-400-pmu,r1"
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"arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
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secure acces to CCI registers
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"arm,cci-500-pmu,r0"
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- reg:
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Usage: required
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Value type: Integer cells. A register entry, expressed
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@ -34,6 +34,20 @@ config ARM_CCI400_PORT_CTRL
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Low level power management driver for CCI400 cache coherent
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interconnect for ARM platforms.
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config ARM_CCI500_PMU
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bool "ARM CCI500 PMU support"
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default y
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depends on (ARM && CPU_V7) || ARM64
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depends on PERF_EVENTS
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select ARM_CCI_PMU
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help
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Support for PMU events monitoring on the ARM CCI-500 cache coherent
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interconnect. CCI-500 provides 8 independent event counters, which
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can count events pertaining to the slave/master interfaces as well
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as the internal events to the CCI.
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If unsure, say Y
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config ARM_CCN
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bool "ARM CCN driver support"
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depends on ARM || ARM64
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@ -51,6 +51,9 @@ static const struct cci_nb_ports cci400_ports = {
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static const struct of_device_id arm_cci_matches[] = {
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#ifdef CONFIG_ARM_CCI400_COMMON
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{.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
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#endif
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#ifdef CONFIG_ARM_CCI500_PMU
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{ .compatible = "arm,cci-500", },
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#endif
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{},
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};
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@ -89,6 +92,9 @@ static const struct of_device_id arm_cci_matches[] = {
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enum {
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CCI_IF_SLAVE,
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CCI_IF_MASTER,
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#ifdef CONFIG_ARM_CCI500_PMU
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CCI_IF_GLOBAL,
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#endif
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CCI_IF_MAX,
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};
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@ -144,6 +150,9 @@ enum cci_models {
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#ifdef CONFIG_ARM_CCI400_PMU
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CCI400_R0,
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CCI400_R1,
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#endif
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#ifdef CONFIG_ARM_CCI500_PMU
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CCI500_R0,
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#endif
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CCI_MODEL_MAX
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};
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@ -294,6 +303,101 @@ static inline struct cci_pmu_model *probe_cci_model(struct platform_device *pdev
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}
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#endif /* CONFIG_ARM_CCI400_PMU */
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#ifdef CONFIG_ARM_CCI500_PMU
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/*
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* CCI500 provides 8 independent event counters that can count
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* any of the events available.
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*
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* CCI500 PMU event id is an 9-bit value made of two parts.
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* bits [8:5] - Source for the event
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* 0x0-0x6 - Slave interfaces
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* 0x8-0xD - Master interfaces
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* 0xf - Global Events
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* 0x7,0xe - Reserved
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*
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* bits [4:0] - Event code (specific to type of interface)
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*/
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/* Port ids */
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#define CCI500_PORT_S0 0x0
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#define CCI500_PORT_S1 0x1
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#define CCI500_PORT_S2 0x2
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#define CCI500_PORT_S3 0x3
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#define CCI500_PORT_S4 0x4
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#define CCI500_PORT_S5 0x5
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#define CCI500_PORT_S6 0x6
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#define CCI500_PORT_M0 0x8
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#define CCI500_PORT_M1 0x9
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#define CCI500_PORT_M2 0xa
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#define CCI500_PORT_M3 0xb
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#define CCI500_PORT_M4 0xc
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#define CCI500_PORT_M5 0xd
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#define CCI500_PORT_GLOBAL 0xf
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#define CCI500_PMU_EVENT_MASK 0x1ffUL
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#define CCI500_PMU_EVENT_SOURCE_SHIFT 0x5
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#define CCI500_PMU_EVENT_SOURCE_MASK 0xf
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#define CCI500_PMU_EVENT_CODE_SHIFT 0x0
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#define CCI500_PMU_EVENT_CODE_MASK 0x1f
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#define CCI500_PMU_EVENT_SOURCE(event) \
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((event >> CCI500_PMU_EVENT_SOURCE_SHIFT) & CCI500_PMU_EVENT_SOURCE_MASK)
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#define CCI500_PMU_EVENT_CODE(event) \
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((event >> CCI500_PMU_EVENT_CODE_SHIFT) & CCI500_PMU_EVENT_CODE_MASK)
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#define CCI500_SLAVE_PORT_MIN_EV 0x00
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#define CCI500_SLAVE_PORT_MAX_EV 0x1f
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#define CCI500_MASTER_PORT_MIN_EV 0x00
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#define CCI500_MASTER_PORT_MAX_EV 0x06
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#define CCI500_GLOBAL_PORT_MIN_EV 0x00
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#define CCI500_GLOBAL_PORT_MAX_EV 0x0f
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static int cci500_validate_hw_event(struct cci_pmu *cci_pmu,
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unsigned long hw_event)
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{
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u32 ev_source = CCI500_PMU_EVENT_SOURCE(hw_event);
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u32 ev_code = CCI500_PMU_EVENT_CODE(hw_event);
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int if_type;
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if (hw_event & ~CCI500_PMU_EVENT_MASK)
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return -ENOENT;
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switch (ev_source) {
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case CCI500_PORT_S0:
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case CCI500_PORT_S1:
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case CCI500_PORT_S2:
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case CCI500_PORT_S3:
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case CCI500_PORT_S4:
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case CCI500_PORT_S5:
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case CCI500_PORT_S6:
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if_type = CCI_IF_SLAVE;
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break;
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case CCI500_PORT_M0:
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case CCI500_PORT_M1:
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case CCI500_PORT_M2:
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case CCI500_PORT_M3:
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case CCI500_PORT_M4:
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case CCI500_PORT_M5:
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if_type = CCI_IF_MASTER;
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break;
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case CCI500_PORT_GLOBAL:
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if_type = CCI_IF_GLOBAL;
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break;
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default:
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return -ENOENT;
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}
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if (ev_code >= cci_pmu->model->event_ranges[if_type].min &&
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ev_code <= cci_pmu->model->event_ranges[if_type].max)
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return hw_event;
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return -ENOENT;
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}
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#endif /* CONFIG_ARM_CCI500_PMU */
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static int pmu_is_valid_counter(struct cci_pmu *cci_pmu, int idx)
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{
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return 0 <= idx && idx <= CCI_PMU_CNTR_LAST(cci_pmu);
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@ -981,6 +1085,29 @@ static struct cci_pmu_model cci_pmu_models[] = {
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.get_event_idx = cci400_get_event_idx,
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},
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#endif
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#ifdef CONFIG_ARM_CCI500_PMU
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[CCI500_R0] = {
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.name = "CCI_500",
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.fixed_hw_cntrs = 0,
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.num_hw_cntrs = 8,
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.cntr_size = SZ_64K,
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.event_ranges = {
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[CCI_IF_SLAVE] = {
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CCI500_SLAVE_PORT_MIN_EV,
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CCI500_SLAVE_PORT_MAX_EV,
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},
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[CCI_IF_MASTER] = {
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CCI500_MASTER_PORT_MIN_EV,
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CCI500_MASTER_PORT_MAX_EV,
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},
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[CCI_IF_GLOBAL] = {
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CCI500_GLOBAL_PORT_MIN_EV,
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CCI500_GLOBAL_PORT_MAX_EV,
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},
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},
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.validate_hw_event = cci500_validate_hw_event,
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},
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#endif
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};
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static const struct of_device_id arm_cci_pmu_matches[] = {
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@ -997,6 +1124,12 @@ static const struct of_device_id arm_cci_pmu_matches[] = {
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.compatible = "arm,cci-400-pmu,r1",
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.data = &cci_pmu_models[CCI400_R1],
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},
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#endif
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#ifdef CONFIG_ARM_CCI500_PMU
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{
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.compatible = "arm,cci-500-pmu,r0",
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.data = &cci_pmu_models[CCI500_R0],
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},
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#endif
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{},
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};
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