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drm/amd/pm: Fix sienna cichlid incorrect OD volage after resume
Always setup overdrive tables after resume. Preserve only some user-defined settings in user_overdrive_table if they're set. Copy restored user_overdrive_table into od_table to get correct values. On cold boot, BTC was triggered and GfxVfCurve was calibrated. We got VfCurve settings (a). On resuming back, BTC will be triggered again and GfxVfCurve will be recalibrated. VfCurve settings (b) got may be different from those of cold boot. So if we reuse those VfCurve settings (a) got on cold boot on suspend, we can run into discrepencies. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1897 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2276 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Błażej Szczygieł <mumei6102@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -2143,16 +2143,9 @@ static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
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(OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
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OverDriveTable_t *user_od_table =
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(OverDriveTable_t *)smu->smu_table.user_overdrive_table;
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OverDriveTable_t user_od_table_bak;
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int ret = 0;
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/*
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* For S3/S4/Runpm resume, no need to setup those overdrive tables again as
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* - either they already have the default OD settings got during cold bootup
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* - or they have some user customized OD settings which cannot be overwritten
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*/
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if (smu->adev->in_suspend)
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return 0;
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ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
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0, (void *)boot_od_table, false);
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if (ret) {
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@ -2163,7 +2156,23 @@ static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
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sienna_cichlid_dump_od_table(smu, boot_od_table);
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memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
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memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
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/*
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* For S3/S4/Runpm resume, we need to setup those overdrive tables again,
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* but we have to preserve user defined values in "user_od_table".
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*/
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if (!smu->adev->in_suspend) {
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memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
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smu->user_dpm_profile.user_od = false;
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} else if (smu->user_dpm_profile.user_od) {
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memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t));
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memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
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user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin;
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user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax;
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user_od_table->UclkFmin = user_od_table_bak.UclkFmin;
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user_od_table->UclkFmax = user_od_table_bak.UclkFmax;
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user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset;
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}
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return 0;
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}
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@ -2373,6 +2382,20 @@ static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
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return ret;
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}
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static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
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{
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struct smu_table_context *table_context = &smu->smu_table;
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OverDriveTable_t *od_table = table_context->overdrive_table;
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OverDriveTable_t *user_od_table = table_context->user_overdrive_table;
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int res;
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res = smu_v11_0_restore_user_od_settings(smu);
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if (res == 0)
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memcpy(od_table, user_od_table, sizeof(OverDriveTable_t));
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return res;
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}
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static int sienna_cichlid_run_btc(struct smu_context *smu)
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{
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int res;
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@ -4400,7 +4423,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
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.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
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.set_default_od_settings = sienna_cichlid_set_default_od_settings,
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.od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
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.restore_user_od_settings = smu_v11_0_restore_user_od_settings,
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.restore_user_od_settings = sienna_cichlid_restore_user_od_settings,
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.run_btc = sienna_cichlid_run_btc,
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.set_power_source = smu_v11_0_set_power_source,
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.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
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