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ARM: mmp: add support for MMP3 SoC
Similar to MMP2, which this patch is based on. Known differencies from MMP2 are: * Two PJ4B cores instead of one PJ4 * Tauros 3 L2 cache controller instead of Tauros 2 * A GIC interrupt controller optionally used instead of the MMP one * A TWD local timer * Different USB2 PHY * A USB3 SS controller * More interrupt muxes Hard to tell what else is different, because documentation is not available. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
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Lubomir Rintel
parent
199c936e37
commit
a9372a5fb2
@ -1,13 +1,13 @@
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# SPDX-License-Identifier: GPL-2.0-only
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menuconfig ARCH_MMP
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bool "Marvell PXA168/910/MMP2"
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bool "Marvell PXA168/910/MMP2/MMP3"
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depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
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select GPIO_PXA
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select GPIOLIB
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select PINCTRL
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select PLAT_PXA
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help
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Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
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Support for Marvell's PXA168/PXA910(MMP), MMP2, and MMP3 processor lines.
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if ARCH_MMP
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@ -129,6 +129,24 @@ config MACH_MMP2_DT
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Include support for Marvell MMP2 based platforms using
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the device tree.
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config MACH_MMP3_DT
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bool "Support MMP3 (ARMv7) platforms"
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depends on ARCH_MULTI_V7
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select ARM_GIC
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select CACHE_L2X0
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select PINCTRL
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select PINCTRL_SINGLE
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select ARCH_HAS_RESET_CONTROLLER
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select CPU_PJ4B
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select PM_GENERIC_DOMAINS if PM
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select PM_GENERIC_DOMAINS_OF if PM && OF
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help
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Say 'Y' here if you want to include support for platforms
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with Marvell MMP3 processor, also known as PXA2128 or
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Armada 620.
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endmenu
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config CPU_PXA168
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@ -34,5 +34,6 @@ obj-$(CONFIG_MACH_FLINT) += flint.o
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obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
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obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o
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obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o
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obj-$(CONFIG_MACH_MMP3_DT) += mmp3.o
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obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
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obj-$(CONFIG_MACH_GPLUGD) += gplugd.o
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@ -18,6 +18,8 @@
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* MMP2 Z0 0x560f5811 0x00F00410
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* MMP2 Z1 0x560f5811 0x00E00410
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* MMP2 A0 0x560f5811 0x00A0A610
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* MMP3 A0 0x562f5842 0x00A02128
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* MMP3 B0 0x562f5842 0x00B02128
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*/
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extern unsigned int mmp_chip_id;
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@ -55,4 +57,29 @@ static inline int cpu_is_mmp2(void)
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#define cpu_is_mmp2() (0)
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#endif
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#ifdef CONFIG_MACH_MMP3_DT
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static inline int cpu_is_mmp3(void)
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{
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return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&
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((mmp_chip_id & 0xffff) == 0x2128);
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}
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static inline int cpu_is_mmp3_a0(void)
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{
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return (cpu_is_mmp3() &&
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((mmp_chip_id & 0x00ff0000) == 0x00a00000));
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}
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static inline int cpu_is_mmp3_b0(void)
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{
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return (cpu_is_mmp3() &&
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((mmp_chip_id & 0x00ff0000) == 0x00b00000));
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}
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#else
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#define cpu_is_mmp3() (0)
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#define cpu_is_mmp3_a0() (0)
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#define cpu_is_mmp3_b0() (0)
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#endif
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#endif /* __ASM_MACH_CPUTYPE_H */
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29
arch/arm/mach-mmp/mmp3.c
Normal file
29
arch/arm/mach-mmp/mmp3.c
Normal file
@ -0,0 +1,29 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Marvell MMP3 aka PXA2128 aka 88AP2128 support
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*
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* Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
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*/
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/of_platform.h>
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#include <linux/clk-provider.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "common.h"
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static const char *const mmp3_dt_board_compat[] __initconst = {
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"marvell,mmp3",
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NULL,
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};
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DT_MACHINE_START(MMP2_DT, "Marvell MMP3")
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.map_io = mmp2_map_io,
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.dt_compat = mmp3_dt_board_compat,
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.l2c_aux_val = 1 << L310_AUX_CTRL_FWA_SHIFT |
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L310_AUX_CTRL_DATA_PREFETCH |
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L310_AUX_CTRL_INSTR_PREFETCH,
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.l2c_aux_mask = 0xc20fffff,
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MACHINE_END
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@ -155,7 +155,8 @@ static void __init timer_config(void)
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__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
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ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
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ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?
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(TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
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(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
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__raw_writel(ccr, mmp_timer_base + TMR_CCR);
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@ -292,6 +292,11 @@ config COMMON_CLK_STM32H7
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help
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Support for stm32h7 SoC family clocks
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config COMMON_CLK_MMP2
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def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT)
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help
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Support for Marvell MMP2 and MMP3 SoC clocks
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config COMMON_CLK_BD718XX
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tristate "Clock driver for ROHM BD718x7 PMIC"
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depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528
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@ -8,7 +8,7 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
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obj-$(CONFIG_RESET_CONTROLLER) += reset.o
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obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
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obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o
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obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o
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obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
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obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
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