mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-23 12:14:10 +08:00
hexagon: simplify asm/io.h for !HAS_IOPORT
Hexagon fails to build after the final patch that makes CONFIG_HAS_IOPORT
optional:
In file included from arch/hexagon/include/asm/io.h:328:
include/asm-generic/io.h:854:18: error: static declaration of 'ioread8' follows non-static declaration
854 | static inline u8 ioread8(const volatile void __iomem *addr)
| ^
include/asm-generic/io.h:853:17: note: expanded from macro 'ioread8'
853 | #define ioread8 ioread8
| ^
include/asm-generic/iomap.h:29:21: note: previous declaration is here
29 | extern unsigned int ioread8(const void __iomem *);
| ^
As it turns out, most of its asm/io.h and lib/io.c files is redundant now,
and just removing all that makes it build again.
As with the other architectures, defining the __raw_readl()/__raw_writel()
type functions instead of the non-__raw ones is better here for consistency.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
6e3f5e626c
commit
a8cb1e92d2
@ -30,7 +30,6 @@ config HEXAGON
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select HAVE_ARCH_KGDB
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select HAVE_ARCH_TRACEHOOK
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select NEED_SG_DMA_LENGTH
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select NO_IOPORT_MAP
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select GENERIC_IOREMAP
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select GENERIC_SMP_IDLE_THREAD
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select STACKTRACE_SUPPORT
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@ -58,6 +57,9 @@ config EARLY_PRINTK
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config MMU
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def_bool y
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config NO_IOPORT_MAP
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def_bool y
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config GENERIC_CSUM
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def_bool y
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@ -8,38 +8,13 @@
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#ifndef _ASM_IO_H
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#define _ASM_IO_H
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <asm/iomap.h>
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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/*
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* We don't have PCI yet.
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* _IO_BASE is pointing at what should be unused virtual space.
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*/
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#define IO_SPACE_LIMIT 0xffff
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#define _IO_BASE ((void __iomem *)0xfe000000)
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#define IOMEM(x) ((void __force __iomem *)(x))
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extern int remap_area_pages(unsigned long start, unsigned long phys_addr,
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unsigned long end, unsigned long flags);
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/* Defined in lib/io.c, needed for smc91x driver. */
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extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
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extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
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extern void __raw_readsl(const void __iomem *addr, void *data, int wordlen);
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extern void __raw_writesl(void __iomem *addr, const void *data, int wordlen);
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#define readsw(p, d, l) __raw_readsw(p, d, l)
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#define writesw(p, d, l) __raw_writesw(p, d, l)
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#define readsl(p, d, l) __raw_readsl(p, d, l)
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#define writesl(p, d, l) __raw_writesl(p, d, l)
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/*
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* virt_to_phys - map virtual address to physical
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* @address: address to map
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@ -58,21 +33,12 @@ static inline void *phys_to_virt(unsigned long address)
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return __va(address);
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}
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/*
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* IO port access primitives. Hexagon doesn't have special IO access
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* instructions; all I/O is memory mapped.
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*
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* in/out are used for "ports", but we don't have "port instructions",
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* so these are really just memory mapped too.
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*/
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/*
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* readb - read byte from memory mapped device
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* @addr: pointer to memory
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*
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* Operates on "I/O bus memory space"
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*/
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static inline u8 readb(const volatile void __iomem *addr)
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 val;
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asm volatile(
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@ -82,8 +48,9 @@ static inline u8 readb(const volatile void __iomem *addr)
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);
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return val;
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}
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#define __raw_readb __raw_readb
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static inline u16 readw(const volatile void __iomem *addr)
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 val;
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asm volatile(
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@ -93,8 +60,9 @@ static inline u16 readw(const volatile void __iomem *addr)
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);
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return val;
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}
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#define __raw_readw __raw_readw
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static inline u32 readl(const volatile void __iomem *addr)
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 val;
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asm volatile(
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@ -104,6 +72,7 @@ static inline u32 readl(const volatile void __iomem *addr)
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);
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return val;
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}
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#define __raw_readl __raw_readl
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/*
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* writeb - write a byte to a memory location
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@ -111,7 +80,7 @@ static inline u32 readl(const volatile void __iomem *addr)
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* @addr: pointer to memory
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*
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*/
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static inline void writeb(u8 data, volatile void __iomem *addr)
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static inline void __raw_writeb(u8 data, volatile void __iomem *addr)
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{
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asm volatile(
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"memb(%0) = %1;"
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@ -120,8 +89,9 @@ static inline void writeb(u8 data, volatile void __iomem *addr)
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: "memory"
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);
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}
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#define __raw_writeb __raw_writeb
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static inline void writew(u16 data, volatile void __iomem *addr)
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static inline void __raw_writew(u16 data, volatile void __iomem *addr)
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{
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asm volatile(
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"memh(%0) = %1;"
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@ -131,8 +101,9 @@ static inline void writew(u16 data, volatile void __iomem *addr)
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);
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}
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#define __raw_writew __raw_writew
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static inline void writel(u32 data, volatile void __iomem *addr)
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static inline void __raw_writel(u32 data, volatile void __iomem *addr)
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{
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asm volatile(
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"memw(%0) = %1;"
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@ -141,26 +112,7 @@ static inline void writel(u32 data, volatile void __iomem *addr)
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: "memory"
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);
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}
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#define __raw_writeb writeb
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#define __raw_writew writew
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#define __raw_writel writel
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#define __raw_readb readb
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#define __raw_readw readw
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#define __raw_readl readl
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/*
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* http://comments.gmane.org/gmane.linux.ports.arm.kernel/117626
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*/
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#define readb_relaxed __raw_readb
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#define readw_relaxed __raw_readw
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#define readl_relaxed __raw_readl
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#define writeb_relaxed __raw_writeb
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#define writew_relaxed __raw_writew
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#define writel_relaxed __raw_writel
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#define __raw_writel __raw_writel
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/*
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* I/O memory mapping functions.
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@ -168,140 +120,6 @@ static inline void writel(u32 data, volatile void __iomem *addr)
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#define _PAGE_IOREMAP (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
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(__HEXAGON_C_DEV << 6))
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#define __raw_writel writel
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static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
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int count)
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{
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memcpy(dst, (void *) src, count);
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}
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static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
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int count)
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{
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memcpy((void *) dst, src, count);
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}
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static inline void memset_io(volatile void __iomem *addr, int value,
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size_t size)
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{
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memset((void __force *)addr, value, size);
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}
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#define PCI_IO_ADDR (volatile void __iomem *)
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/*
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* inb - read byte from I/O port or something
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* @port: address in I/O space
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*
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* Operates on "I/O bus I/O space"
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*/
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static inline u8 inb(unsigned long port)
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{
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return readb(_IO_BASE + (port & IO_SPACE_LIMIT));
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}
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static inline u16 inw(unsigned long port)
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{
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return readw(_IO_BASE + (port & IO_SPACE_LIMIT));
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}
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static inline u32 inl(unsigned long port)
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{
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return readl(_IO_BASE + (port & IO_SPACE_LIMIT));
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}
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/*
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* outb - write a byte to a memory location
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* @data: data to write to
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* @addr: address in I/O space
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*/
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static inline void outb(u8 data, unsigned long port)
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{
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writeb(data, _IO_BASE + (port & IO_SPACE_LIMIT));
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}
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static inline void outw(u16 data, unsigned long port)
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{
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writew(data, _IO_BASE + (port & IO_SPACE_LIMIT));
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}
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static inline void outl(u32 data, unsigned long port)
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{
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writel(data, _IO_BASE + (port & IO_SPACE_LIMIT));
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}
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#define outb_p outb
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#define outw_p outw
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#define outl_p outl
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#define inb_p inb
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#define inw_p inw
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#define inl_p inl
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static inline void insb(unsigned long port, void *buffer, int count)
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{
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if (count) {
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u8 *buf = buffer;
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do {
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u8 x = inb(port);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void insw(unsigned long port, void *buffer, int count)
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{
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if (count) {
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u16 *buf = buffer;
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do {
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u16 x = inw(port);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void insl(unsigned long port, void *buffer, int count)
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{
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if (count) {
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u32 *buf = buffer;
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do {
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u32 x = inw(port);
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*buf++ = x;
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} while (--count);
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}
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}
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static inline void outsb(unsigned long port, const void *buffer, int count)
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{
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if (count) {
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const u8 *buf = buffer;
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do {
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outb(*buf++, port);
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} while (--count);
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}
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}
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static inline void outsw(unsigned long port, const void *buffer, int count)
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{
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if (count) {
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const u16 *buf = buffer;
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do {
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outw(*buf++, port);
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} while (--count);
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}
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}
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static inline void outsl(unsigned long port, const void *buffer, int count)
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{
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if (count) {
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const u32 *buf = buffer;
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do {
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outl(*buf++, port);
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} while (--count);
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}
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}
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/*
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* These defines are necessary to use the generic io.h for filling in
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* the missing parts of the API contract. This is because the platform
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@ -310,23 +128,6 @@ static inline void outsl(unsigned long port, const void *buffer, int count)
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*/
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#define virt_to_phys virt_to_phys
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#define phys_to_virt phys_to_virt
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#define memset_io memset_io
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#define memcpy_fromio memcpy_fromio
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#define memcpy_toio memcpy_toio
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#define readb readb
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#define readw readw
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#define readl readl
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#define writeb writeb
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#define writew writew
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#define writel writel
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#define insb insb
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#define insw insw
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#define insl insl
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#define outsb outsb
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#define outsw outsw
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#define outsl outsl
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#include <asm-generic/io.h>
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#endif /* __KERNEL__ */
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#endif
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@ -2,5 +2,5 @@
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#
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# Makefile for hexagon-specific library files.
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#
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obj-y = checksum.o io.o memcpy.o memset.o memcpy_likely_aligned.o \
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obj-y = checksum.o memcpy.o memset.o memcpy_likely_aligned.o \
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divsi3.o modsi3.o udivsi3.o umodsi3.o
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@ -1,82 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* I/O access functions for Hexagon
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*
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* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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*/
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#include <asm/io.h>
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/* These are all FIFO routines! */
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/*
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* __raw_readsw - read words a short at a time
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* @addr: source address
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* @data: data address
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* @len: number of shorts to read
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*/
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void __raw_readsw(const void __iomem *addr, void *data, int len)
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{
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const volatile short int *src = (short int *) addr;
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short int *dst = (short int *) data;
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if ((u32)data & 0x1)
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panic("unaligned pointer to readsw");
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while (len-- > 0)
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*dst++ = *src;
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}
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EXPORT_SYMBOL(__raw_readsw);
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/*
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* __raw_writesw - read words a short at a time
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* @addr: source address
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* @data: data address
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* @len: number of shorts to read
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*/
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void __raw_writesw(void __iomem *addr, const void *data, int len)
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{
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const short int *src = (short int *)data;
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volatile short int *dst = (short int *)addr;
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if ((u32)data & 0x1)
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panic("unaligned pointer to writesw");
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while (len-- > 0)
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*dst = *src++;
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}
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EXPORT_SYMBOL(__raw_writesw);
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/* Pretty sure len is pre-adjusted for the length of the access already */
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void __raw_readsl(const void __iomem *addr, void *data, int len)
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{
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const volatile long *src = (long *) addr;
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long *dst = (long *) data;
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if ((u32)data & 0x3)
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panic("unaligned pointer to readsl");
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while (len-- > 0)
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*dst++ = *src;
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}
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EXPORT_SYMBOL(__raw_readsl);
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void __raw_writesl(void __iomem *addr, const void *data, int len)
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{
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const long *src = (long *)data;
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volatile long *dst = (long *)addr;
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if ((u32)data & 0x3)
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panic("unaligned pointer to writesl");
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while (len-- > 0)
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*dst = *src++;
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}
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EXPORT_SYMBOL(__raw_writesl);
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