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drm/radeon: add set_uvd_clocks callback for evergreen
v2: remove unneeded register definitions Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
23d33ba32b
commit
a8b4925c79
@ -131,6 +131,170 @@ done:
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return r;
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}
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static int evergreen_uvd_calc_post_div(unsigned target_freq,
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unsigned vco_freq,
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unsigned *div)
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{
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/* target larger than vco frequency ? */
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if (vco_freq < target_freq)
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return -1; /* forget it */
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/* Fclk = Fvco / PDIV */
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*div = vco_freq / target_freq;
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/* we alway need a frequency less than or equal the target */
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if ((vco_freq / *div) > target_freq)
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*div += 1;
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/* dividers above 5 must be even */
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if (*div > 5 && *div % 2)
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*div += 1;
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/* out of range ? */
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if (*div >= 128)
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return -1; /* forget it */
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return vco_freq / *div;
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}
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static int evergreen_uvd_send_upll_ctlreq(struct radeon_device *rdev)
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{
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unsigned i;
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/* assert UPLL_CTLREQ */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
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/* wait for CTLACK and CTLACK2 to get asserted */
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for (i = 0; i < 100; ++i) {
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uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
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if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
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break;
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mdelay(10);
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}
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if (i == 100)
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return -ETIMEDOUT;
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/* deassert UPLL_CTLREQ */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
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return 0;
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}
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int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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{
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/* start off with something large */
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int optimal_diff_score = 0x7FFFFFF;
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unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
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unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
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unsigned vco_freq;
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int r;
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/* loop through vco from low to high */
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for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {
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unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;
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int calc_clk, diff_score, diff_vclk, diff_dclk;
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unsigned vclk_div, dclk_div;
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/* fb div out of range ? */
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if (fb_div > 0x03FFFFFF)
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break; /* it can oly get worse */
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/* calc vclk with current vco freq. */
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calc_clk = evergreen_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
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if (calc_clk == -1)
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break; /* vco is too big, it has to stop. */
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diff_vclk = vclk - calc_clk;
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/* calc dclk with current vco freq. */
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calc_clk = evergreen_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
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if (calc_clk == -1)
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break; /* vco is too big, it has to stop. */
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diff_dclk = dclk - calc_clk;
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/* determine if this vco setting is better than current optimal settings */
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diff_score = abs(diff_vclk) + abs(diff_dclk);
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if (diff_score < optimal_diff_score) {
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optimal_fb_div = fb_div;
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optimal_vclk_div = vclk_div;
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optimal_dclk_div = dclk_div;
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optimal_vco_freq = vco_freq;
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optimal_diff_score = diff_score;
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if (optimal_diff_score == 0)
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break; /* it can't get better than this */
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}
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}
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/* set VCO_MODE to 1 */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
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/* toggle UPLL_SLEEP to 1 then back to 0 */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
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/* deassert UPLL_RESET */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
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mdelay(1);
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/* bypass vclk and dclk with bclk */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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/* put PLL in bypass mode */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
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r = evergreen_uvd_send_upll_ctlreq(rdev);
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if (r)
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return r;
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/* assert UPLL_RESET again */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
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/* disable spread spectrum. */
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WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
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/* set feedback divider */
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WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div), ~UPLL_FB_DIV_MASK);
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/* set ref divider to 0 */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
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if (optimal_vco_freq < 187500)
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WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
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else
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WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
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/* set PDIV_A and PDIV_B */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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UPLL_PDIV_A(optimal_vclk_div) | UPLL_PDIV_B(optimal_dclk_div),
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~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
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/* give the PLL some time to settle */
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mdelay(15);
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/* deassert PLL_RESET */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
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mdelay(15);
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/* switch from bypass mode to normal mode */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
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r = evergreen_uvd_send_upll_ctlreq(rdev);
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if (r)
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return r;
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/* switch VCLK and DCLK selection */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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mdelay(100);
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return 0;
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}
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void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
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{
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u16 ctl, v;
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@ -53,6 +53,33 @@
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#define RCU_IND_INDEX 0x100
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#define RCU_IND_DATA 0x104
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/* discrete uvd clocks */
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#define CG_UPLL_FUNC_CNTL 0x718
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# define UPLL_RESET_MASK 0x00000001
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# define UPLL_SLEEP_MASK 0x00000002
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# define UPLL_BYPASS_EN_MASK 0x00000004
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# define UPLL_CTLREQ_MASK 0x00000008
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# define UPLL_REF_DIV_MASK 0x001F0000
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# define UPLL_VCO_MODE_MASK 0x00000200
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# define UPLL_CTLACK_MASK 0x40000000
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# define UPLL_CTLACK2_MASK 0x80000000
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#define CG_UPLL_FUNC_CNTL_2 0x71c
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# define UPLL_PDIV_A(x) ((x) << 0)
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# define UPLL_PDIV_A_MASK 0x0000007F
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# define UPLL_PDIV_B(x) ((x) << 8)
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# define UPLL_PDIV_B_MASK 0x00007F00
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# define VCLK_SRC_SEL(x) ((x) << 20)
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# define VCLK_SRC_SEL_MASK 0x01F00000
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# define DCLK_SRC_SEL(x) ((x) << 25)
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# define DCLK_SRC_SEL_MASK 0x3E000000
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#define CG_UPLL_FUNC_CNTL_3 0x720
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# define UPLL_FB_DIV(x) ((x) << 0)
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# define UPLL_FB_DIV_MASK 0x01FFFFFF
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#define CG_UPLL_FUNC_CNTL_4 0x854
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# define UPLL_SPARE_ISPARE9 0x00020000
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#define CG_UPLL_SPREAD_SPECTRUM 0x79c
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# define SSEN_MASK 0x00000001
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/* fusion uvd clocks */
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#define CG_DCLK_CNTL 0x610
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# define DCLK_DIVIDER_MASK 0x7f
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@ -1278,6 +1278,7 @@ static struct radeon_asic evergreen_asic = {
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.get_pcie_lanes = &r600_get_pcie_lanes,
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.set_pcie_lanes = &r600_set_pcie_lanes,
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.set_clock_gating = NULL,
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.set_uvd_clocks = &evergreen_set_uvd_clocks,
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},
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.pflip = {
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.pre_page_flip = &evergreen_pre_page_flip,
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@ -1469,6 +1470,7 @@ static struct radeon_asic btc_asic = {
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.get_pcie_lanes = NULL,
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.set_pcie_lanes = NULL,
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.set_clock_gating = NULL,
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.set_uvd_clocks = &evergreen_set_uvd_clocks,
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},
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.pflip = {
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.pre_page_flip = &evergreen_pre_page_flip,
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@ -1607,6 +1609,7 @@ static struct radeon_asic cayman_asic = {
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.get_pcie_lanes = NULL,
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.set_pcie_lanes = NULL,
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.set_clock_gating = NULL,
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.set_uvd_clocks = &evergreen_set_uvd_clocks,
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},
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.pflip = {
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.pre_page_flip = &evergreen_pre_page_flip,
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@ -460,6 +460,7 @@ extern void evergreen_pm_finish(struct radeon_device *rdev);
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extern void sumo_pm_init_profile(struct radeon_device *rdev);
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extern void btc_pm_init_profile(struct radeon_device *rdev);
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int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
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extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
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extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
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