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drm fixes for 5.12-rc7

Browse Source 
amdgpu:
 - DCN3 fix
 - Fix CAC setting regression for TOPAZ
 - Fix ttm regression
 
 radeon:
 - Fix ttm regression
 
 msm:
 - a5xx/a6xx timestamp fix
 - microcode version check
 - fail path fix
 - block programming fix
 - error removal fix.
 
 i915:
 - Fix invalid access to ACPI _DSM objects
 
 xen:
 - Fix use-after-free in xen.
 - minor duplicate defintion cleanup
 
 vc4:
 - Reduce fifo threshold on hvs4 to fix a fifo full error.
 - minor redunantant assignment cleanup
 
 panel:
 - Disable TE support for Droid4 and N950.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJgcK0TAAoJEAx081l5xIa+MHYP/1n6jp0eI7A4E5Ogix5yYKaH
 V3ebXRkiadVEMsJZWOKFDmAA+DWdBtP+Et0K0gHV7dj73e08QqBm9UofMprqzooF
 +5kXVHwe57+P55hr7xz86o5R+Pja4D3JZ17b963h7PRMH2++iEF6+WovK95B3aNk
 Onz77+lKlYYyz1Rtnf9GiU5eps47tdMmF1joHdm+3QddM/S76rbZMQ4P0AW8iw4A
 xz2GB3Z8h6jwujzXRt2rijjOJJWrrgs5X7M//vC/qF7YSxtEclF1IHH1FRYqvy93
 qbbAgI4QOB/9WuJyTPQgrLrlSTF0Y829p7uTjCABreZ/IYs4J/TwopvzLHuH7Pfo
 tSSx6Xp1vV1kuPYF1D+d4hcFEJZXXpDWGf4CAMaAsDBmOAPmVLPiuir8Q9fn2w6u
 OrjQku+EVyzcnKp89vdm8uX8zz5qAqnl1nuhhjzH2z5S1VndYhIlTuVT4CV75f44
 7Qk+qNxmrJcjxzRYke9dr4rx1iw/0fEJV3Zjgnk1w7DAIjtbXlIh4xKzkYxLnHvh
 uKoQ5YljypL3/n0BciJVuok4144PTRyJdyK3ngrS9rRfcqhbSTs4BW/kCKv6PoOj
 yTB4J8oDRIhUHMaOCqVvRfSbM2Tb7uOUN9CgskpFisvgNg7MIl0SY6xpcnhNHBQL
 IinQGgcBmDxhIGQ968vh
 =gQ9i
 -----END PGP SIGNATURE-----

Merge tag 'drm-fixes-2021-04-10' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Was relatively quiet this week, but still a few pulls came in, pretty
  much small fixes across the board, a couple of regression fixes in the
  amdgpu/radeon code, msm has a few minor fixes across the board, a
  panel regression fix also.

  amdgpu:
   - DCN3 fix
   - Fix CAC setting regression for TOPAZ
   - Fix ttm regression

  radeon:
   - Fix ttm regression

  msm:
   - a5xx/a6xx timestamp fix
   - microcode version check
   - fail path fix
   - block programming fix
   - error removal fix

  i915:
   - Fix invalid access to ACPI _DSM objects

  xen:
   - Fix use-after-free in xen
   - minor duplicate defintion cleanup

  vc4:
   - Reduce fifo threshold on hvs4 to fix a fifo full error
   - minor redunantant assignment cleanup

  panel:
   - Disable TE support for Droid4 and N950"

* tag 'drm-fixes-2021-04-10' of git://anongit.freedesktop.org/drm/drm:
  drm/vc4: crtc: Reduce PV fifo threshold on hvs4
  drm/vc4: plane: Remove redundant assignment
  drm/amdgpu/smu7: fix CAC setting on TOPAZ
  drm/radeon: Fix size overflow
  drm/amdgpu: Fix size overflow
  drm/i915: Fix invalid access to ACPI _DSM objects
  drm/amd/display: Add missing mask for DCN3
  drm/panel: panel-dsi-cm: disable TE for now
  drm/msm/disp/dpu1: program 3d_merge only if block is attached
  drm/msm: a6xx: fix version check for the A650 SQE microcode
  drm/msm: Fix a5xx/a6xx timestamps
  drm/msm: Fix removal of valid error case when checking speed_bin
  drm/msm: Set drvdata to NULL when msm_drm_init() fails
  drivers: gpu: drm: xen_drm_front_drm_info is declared twice
  gpu/xen: Fix a use after free in xen_drm_drv_init
This commit is contained in:
Linus Torvalds 2021-04-09 12:56:10 -07:00
commit a85f165e1f
14 changed files with 74 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
View File

@ -906,7 +906,7 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
/* Allocate an SG array and squash pages into it */
r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
ttm->num_pages << PAGE_SHIFT,
(u64)ttm->num_pages << PAGE_SHIFT,
GFP_KERNEL);
if (r)
goto release_sg;

1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
View File

@ -134,6 +134,7 @@
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK, mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\

3
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -1224,7 +1224,8 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
(hwmgr->chip_id == CHIP_POLARIS10) ||
(hwmgr->chip_id == CHIP_POLARIS11) ||
(hwmgr->chip_id == CHIP_POLARIS12) ||
(hwmgr->chip_id == CHIP_TONGA))
(hwmgr->chip_id == CHIP_TONGA) ||
(hwmgr->chip_id == CHIP_TOPAZ))
PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);

22
drivers/gpu/drm/i915/display/intel_acpi.c
View File

@ -84,13 +84,31 @@ static void intel_dsm_platform_mux_info(acpi_handle dhandle)
return;
}
if (!pkg->package.count) {
DRM_DEBUG_DRIVER("no connection in _DSM\n");
return;
}
connector_count = &pkg->package.elements[0];
DRM_DEBUG_DRIVER("MUX info connectors: %lld\n",
(unsigned long long)connector_count->integer.value);
for (i = 1; i < pkg->package.count; i++) {
union acpi_object *obj = &pkg->package.elements[i];
union acpi_object *connector_id = &obj->package.elements[0];
union acpi_object *info = &obj->package.elements[1];
union acpi_object *connector_id;
union acpi_object *info;
if (obj->type != ACPI_TYPE_PACKAGE || obj->package.count < 2) {
DRM_DEBUG_DRIVER("Invalid object for MUX #%d\n", i);
continue;
}
connector_id = &obj->package.elements[0];
info = &obj->package.elements[1];
if (info->type != ACPI_TYPE_BUFFER || info->buffer.length < 4) {
DRM_DEBUG_DRIVER("Invalid info for MUX obj #%d\n", i);
continue;
}
DRM_DEBUG_DRIVER("Connector id: 0x%016llx\n",
(unsigned long long)connector_id->integer.value);
DRM_DEBUG_DRIVER(" port id: %s\n",

4
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
View File

@ -1386,8 +1386,8 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
{
*value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_CP_0_LO,
REG_A5XX_RBBM_PERFCTR_CP_0_HI);
*value = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO,
REG_A5XX_RBBM_ALWAYSON_COUNTER_HI);
return 0;
}

18
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View File

@ -567,17 +567,17 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,
} else {
/*
* a650 tier targets don't need whereami but still need to be
* equal to or newer than 1.95 for other security fixes
* equal to or newer than 0.95 for other security fixes
*/
if (adreno_is_a650(adreno_gpu)) {
if ((buf[0] & 0xfff) >= 0x195) {
if ((buf[0] & 0xfff) >= 0x095) {
ret = true;
goto out;
}
DRM_DEV_ERROR(&gpu->pdev->dev,
"a650 SQE ucode is too old. Have version %x need at least %x\n",
buf[0] & 0xfff, 0x195);
buf[0] & 0xfff, 0x095);
}
/*
@ -1228,8 +1228,8 @@ static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
/* Force the GPU power on so we can read this register */
a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
*value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
REG_A6XX_RBBM_PERFCTR_CP_0_HI);
*value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
REG_A6XX_CP_ALWAYS_ON_COUNTER_HI);
a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
mutex_unlock(&perfcounter_oob);
@ -1406,7 +1406,13 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
int ret;
ret = nvmem_cell_read_u16(dev, "speed_bin", &speedbin);
if (ret) {
/*
* -ENOENT means that the platform doesn't support speedbin which is
* fine
*/
if (ret == -ENOENT) {
return 0;
} else if (ret) {
DRM_DEV_ERROR(dev,
"failed to read speed-bin (%d). Some OPPs may not be supported by hardware",
ret);

4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
View File

@ -496,7 +496,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
DPU_REG_WRITE(c, CTL_TOP, mode_sel);
DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0));
if (cfg->merge_3d)
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
BIT(cfg->merge_3d - MERGE_3D_0));
}
static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,

1
drivers/gpu/drm/msm/msm_drv.c
View File

@ -570,6 +570,7 @@ err_free_priv:
kfree(priv);
err_put_drm_dev:
drm_dev_put(ddev);
platform_set_drvdata(pdev, NULL);
return ret;
}

12
drivers/gpu/drm/panel/panel-dsi-cm.c
View File

@ -37,6 +37,7 @@ struct dsic_panel_data {
u32 height_mm;
u32 max_hs_rate;
u32 max_lp_rate;
bool te_support;
};
struct panel_drv_data {
@ -334,9 +335,11 @@ static int dsicm_power_on(struct panel_drv_data *ddata)
if (r)
goto err;
r = mipi_dsi_dcs_set_tear_on(ddata->dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
if (r)
goto err;
if (ddata->panel_data->te_support) {
r = mipi_dsi_dcs_set_tear_on(ddata->dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
if (r)
goto err;
}
/* possible panel bug */
msleep(100);
@ -619,6 +622,7 @@ static const struct dsic_panel_data taal_data = {
.height_mm = 0,
.max_hs_rate = 300000000,
.max_lp_rate = 10000000,
.te_support = true,
};
static const struct dsic_panel_data himalaya_data = {
@ -629,6 +633,7 @@ static const struct dsic_panel_data himalaya_data = {
.height_mm = 88,
.max_hs_rate = 300000000,
.max_lp_rate = 10000000,
.te_support = false,
};
static const struct dsic_panel_data droid4_data = {
@ -639,6 +644,7 @@ static const struct dsic_panel_data droid4_data = {
.height_mm = 89,
.max_hs_rate = 300000000,
.max_lp_rate = 10000000,
.te_support = false,
};
static const struct of_device_id dsicm_of_match[] = {

4
drivers/gpu/drm/radeon/radeon_ttm.c
View File

@ -364,7 +364,7 @@ static int radeon_ttm_tt_pin_userptr(struct ttm_bo_device *bdev, struct ttm_tt *
if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
/* check that we only pin down anonymous memory
to prevent problems with writeback */
unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
unsigned long end = gtt->userptr + (u64)ttm->num_pages * PAGE_SIZE;
struct vm_area_struct *vma;
vma = find_vma(gtt->usermm, gtt->userptr);
if (!vma || vma->vm_file || vma->vm_end < end)
@ -386,7 +386,7 @@ static int radeon_ttm_tt_pin_userptr(struct ttm_bo_device *bdev, struct ttm_tt *
} while (pinned < ttm->num_pages);
r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
ttm->num_pages << PAGE_SHIFT,
(u64)ttm->num_pages << PAGE_SHIFT,
GFP_KERNEL);
if (r)
goto release_sg;

17
drivers/gpu/drm/vc4/vc4_crtc.c
View File

@ -210,6 +210,7 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
{
const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
u32 fifo_len_bytes = pv_data->fifo_depth;
/*
@ -238,6 +239,22 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
if (crtc_data->hvs_output == 5)
return 32;
/*
* It looks like in some situations, we will overflow
* the PixelValve FIFO (with the bit 10 of PV stat being
* set) and stall the HVS / PV, eventually resulting in
* a page flip timeout.
*
* Displaying the video overlay during a playback with
* Kodi on an RPi3 seems to be a great solution with a
* failure rate around 50%.
*
* Removing 1 from the FIFO full level however
* seems to completely remove that issue.
*/
if (!vc4->hvs->hvs5)
return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
}
}

1
drivers/gpu/drm/vc4/vc4_plane.c
View File

@ -1146,7 +1146,6 @@ static void vc4_plane_atomic_async_update(struct drm_plane *plane,
plane->state->src_y = state->src_y;
plane->state->src_w = state->src_w;
plane->state->src_h = state->src_h;
plane->state->src_h = state->src_h;
plane->state->alpha = state->alpha;
plane->state->pixel_blend_mode = state->pixel_blend_mode;
plane->state->rotation = state->rotation;

6
drivers/gpu/drm/xen/xen_drm_front.c
View File

@ -521,7 +521,7 @@ static int xen_drm_drv_init(struct xen_drm_front_info *front_info)
drm_dev = drm_dev_alloc(&xen_drm_driver, dev);
if (IS_ERR(drm_dev)) {
ret = PTR_ERR(drm_dev);
goto fail;
goto fail_dev;
}
drm_info->drm_dev = drm_dev;
@ -551,8 +551,10 @@ fail_modeset:
drm_kms_helper_poll_fini(drm_dev);
drm_mode_config_cleanup(drm_dev);
drm_dev_put(drm_dev);
fail:
fail_dev:
kfree(drm_info);
front_info->drm_info = NULL;
fail:
return ret;
}

1
drivers/gpu/drm/xen/xen_drm_front_conn.h
View File

@ -16,7 +16,6 @@
struct drm_connector;
struct xen_drm_front_drm_info;
struct xen_drm_front_drm_info;
int xen_drm_front_conn_init(struct xen_drm_front_drm_info *drm_info,
struct drm_connector *connector);